1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
10 model = "Microchip PolarFire SoC";
11 compatible = "microchip,mpfs";
18 compatible = "sifive,e51", "sifive,rocket0", "riscv";
20 i-cache-block-size = <64>;
22 i-cache-size = <16384>;
24 riscv,isa = "rv64imac";
25 clocks = <&clkcfg CLK_CPU>;
28 cpu0_intc: interrupt-controller {
29 #interrupt-cells = <1>;
30 compatible = "riscv,cpu-intc";
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
37 d-cache-block-size = <64>;
39 d-cache-size = <32768>;
43 i-cache-block-size = <64>;
45 i-cache-size = <32768>;
48 mmu-type = "riscv,sv39";
50 riscv,isa = "rv64imafdc";
51 clocks = <&clkcfg CLK_CPU>;
55 cpu1_intc: interrupt-controller {
56 #interrupt-cells = <1>;
57 compatible = "riscv,cpu-intc";
63 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
64 d-cache-block-size = <64>;
66 d-cache-size = <32768>;
70 i-cache-block-size = <64>;
72 i-cache-size = <32768>;
75 mmu-type = "riscv,sv39";
77 riscv,isa = "rv64imafdc";
78 clocks = <&clkcfg CLK_CPU>;
82 cpu2_intc: interrupt-controller {
83 #interrupt-cells = <1>;
84 compatible = "riscv,cpu-intc";
90 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
91 d-cache-block-size = <64>;
93 d-cache-size = <32768>;
97 i-cache-block-size = <64>;
99 i-cache-size = <32768>;
102 mmu-type = "riscv,sv39";
104 riscv,isa = "rv64imafdc";
105 clocks = <&clkcfg CLK_CPU>;
109 cpu3_intc: interrupt-controller {
110 #interrupt-cells = <1>;
111 compatible = "riscv,cpu-intc";
112 interrupt-controller;
117 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
118 d-cache-block-size = <64>;
120 d-cache-size = <32768>;
124 i-cache-block-size = <64>;
126 i-cache-size = <32768>;
129 mmu-type = "riscv,sv39";
131 riscv,isa = "rv64imafdc";
132 clocks = <&clkcfg CLK_CPU>;
135 cpu4_intc: interrupt-controller {
136 #interrupt-cells = <1>;
137 compatible = "riscv,cpu-intc";
138 interrupt-controller;
144 compatible = "fixed-clock";
148 syscontroller: syscontroller {
149 compatible = "microchip,mpfs-sys-controller";
154 #address-cells = <2>;
156 compatible = "simple-bus";
159 cctrllr: cache-controller@2010000 {
160 compatible = "sifive,fu540-c000-ccache", "cache";
161 reg = <0x0 0x2010000 0x0 0x1000>;
162 cache-block-size = <64>;
165 cache-size = <2097152>;
167 interrupt-parent = <&plic>;
168 interrupts = <1>, <2>, <3>;
171 clint: clint@2000000 {
172 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
173 reg = <0x0 0x2000000 0x0 0xC000>;
174 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
175 <&cpu1_intc 3>, <&cpu1_intc 7>,
176 <&cpu2_intc 3>, <&cpu2_intc 7>,
177 <&cpu3_intc 3>, <&cpu3_intc 7>,
178 <&cpu4_intc 3>, <&cpu4_intc 7>;
181 plic: interrupt-controller@c000000 {
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
183 reg = <0x0 0xc000000 0x0 0x4000000>;
184 #address-cells = <0>;
185 #interrupt-cells = <1>;
186 interrupt-controller;
187 interrupts-extended = <&cpu0_intc 11>,
188 <&cpu1_intc 11>, <&cpu1_intc 9>,
189 <&cpu2_intc 11>, <&cpu2_intc 9>,
190 <&cpu3_intc 11>, <&cpu3_intc 9>,
191 <&cpu4_intc 11>, <&cpu4_intc 9>;
195 pdma: dma-controller@3000000 {
196 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
197 reg = <0x0 0x3000000 0x0 0x8000>;
198 interrupt-parent = <&plic>;
199 interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
204 clkcfg: clkcfg@20002000 {
205 compatible = "microchip,mpfs-clkcfg";
206 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
211 mmuart0: serial@20000000 {
212 compatible = "ns16550a";
213 reg = <0x0 0x20000000 0x0 0x400>;
216 interrupt-parent = <&plic>;
218 current-speed = <115200>;
219 clocks = <&clkcfg CLK_MMUART0>;
220 status = "disabled"; /* Reserved for the HSS */
223 mmuart1: serial@20100000 {
224 compatible = "ns16550a";
225 reg = <0x0 0x20100000 0x0 0x400>;
228 interrupt-parent = <&plic>;
230 current-speed = <115200>;
231 clocks = <&clkcfg CLK_MMUART1>;
235 mmuart2: serial@20102000 {
236 compatible = "ns16550a";
237 reg = <0x0 0x20102000 0x0 0x400>;
240 interrupt-parent = <&plic>;
242 current-speed = <115200>;
243 clocks = <&clkcfg CLK_MMUART2>;
247 mmuart3: serial@20104000 {
248 compatible = "ns16550a";
249 reg = <0x0 0x20104000 0x0 0x400>;
252 interrupt-parent = <&plic>;
254 current-speed = <115200>;
255 clocks = <&clkcfg CLK_MMUART3>;
259 mmuart4: serial@20106000 {
260 compatible = "ns16550a";
261 reg = <0x0 0x20106000 0x0 0x400>;
264 interrupt-parent = <&plic>;
266 clocks = <&clkcfg CLK_MMUART4>;
267 current-speed = <115200>;
271 /* Common node entry for emmc/sd */
273 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
274 reg = <0x0 0x20008000 0x0 0x1000>;
275 interrupt-parent = <&plic>;
277 clocks = <&clkcfg CLK_MMC>;
278 max-frequency = <200000000>;
283 compatible = "microchip,mpfs-spi";
284 #address-cells = <1>;
286 reg = <0x0 0x20108000 0x0 0x1000>;
287 interrupt-parent = <&plic>;
289 clocks = <&clkcfg CLK_SPI0>;
290 spi-max-frequency = <25000000>;
295 compatible = "microchip,mpfs-spi";
296 #address-cells = <1>;
298 reg = <0x0 0x20109000 0x0 0x1000>;
299 interrupt-parent = <&plic>;
301 clocks = <&clkcfg CLK_SPI1>;
302 spi-max-frequency = <25000000>;
307 compatible = "microchip,mpfs-qspi";
308 #address-cells = <1>;
310 reg = <0x0 0x21000000 0x0 0x1000>;
311 interrupt-parent = <&plic>;
313 clocks = <&clkcfg CLK_QSPI>;
314 spi-max-frequency = <25000000>;
319 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
320 reg = <0x0 0x2010a000 0x0 0x1000>;
321 #address-cells = <1>;
323 interrupt-parent = <&plic>;
325 clocks = <&clkcfg CLK_I2C0>;
326 clock-frequency = <100000>;
331 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
332 reg = <0x0 0x2010b000 0x0 0x1000>;
333 #address-cells = <1>;
335 interrupt-parent = <&plic>;
337 clocks = <&clkcfg CLK_I2C1>;
338 clock-frequency = <100000>;
342 mac0: ethernet@20110000 {
343 compatible = "cdns,macb";
344 reg = <0x0 0x20110000 0x0 0x2000>;
345 #address-cells = <1>;
347 interrupt-parent = <&plic>;
348 interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
349 local-mac-address = [00 00 00 00 00 00];
350 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
351 clock-names = "pclk", "hclk";
355 mac1: ethernet@20112000 {
356 compatible = "cdns,macb";
357 reg = <0x0 0x20112000 0x0 0x2000>;
358 #address-cells = <1>;
360 interrupt-parent = <&plic>;
361 interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
362 local-mac-address = [00 00 00 00 00 00];
363 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
364 clock-names = "pclk", "hclk";
368 gpio0: gpio@20120000 {
369 compatible = "microchip,mpfs-gpio";
370 reg = <0x0 0x20120000 0x0 0x1000>;
371 interrupt-parent = <&plic>;
372 interrupt-controller;
373 #interrupt-cells = <1>;
374 clocks = <&clkcfg CLK_GPIO0>;
380 gpio1: gpio@20121000 {
381 compatible = "microchip,mpfs-gpio";
382 reg = <0x0 0x20121000 0x0 0x1000>;
383 interrupt-parent = <&plic>;
384 interrupt-controller;
385 #interrupt-cells = <1>;
386 clocks = <&clkcfg CLK_GPIO1>;
392 gpio2: gpio@20122000 {
393 compatible = "microchip,mpfs-gpio";
394 reg = <0x0 0x20122000 0x0 0x1000>;
395 interrupt-parent = <&plic>;
396 interrupt-controller;
397 #interrupt-cells = <1>;
398 clocks = <&clkcfg CLK_GPIO2>;
405 compatible = "microchip,mpfs-rtc";
406 reg = <0x0 0x20124000 0x0 0x1000>;
407 interrupt-parent = <&plic>;
408 interrupts = <80>, <81>;
409 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
410 clock-names = "rtc", "rtcref";
415 compatible = "microchip,mpfs-musb";
416 reg = <0x0 0x20201000 0x0 0x1000>;
417 interrupt-parent = <&plic>;
418 interrupts = <86>, <87>;
419 clocks = <&clkcfg CLK_USB>;
420 interrupt-names = "dma","mc";
424 pcie: pcie@2000000000 {
425 compatible = "microchip,pcie-host-1.0";
426 #address-cells = <0x3>;
427 #interrupt-cells = <0x1>;
430 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
431 reg-names = "cfg", "apb";
432 bus-range = <0x0 0x7f>;
433 interrupt-parent = <&plic>;
435 interrupt-map = <0 0 0 1 &pcie_intc 0>,
436 <0 0 0 2 &pcie_intc 1>,
437 <0 0 0 3 &pcie_intc 2>,
438 <0 0 0 4 &pcie_intc 3>;
439 interrupt-map-mask = <0 0 0 7>;
440 clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
441 clock-names = "fic0", "fic1", "fic3";
442 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
443 msi-parent = <&pcie>;
445 microchip,axi-m-atr0 = <0x10 0x0>;
447 pcie_intc: legacy-interrupt-controller {
448 #address-cells = <0>;
449 #interrupt-cells = <1>;
450 interrupt-controller;
454 mbox: mailbox@37020000 {
455 compatible = "microchip,mpfs-mailbox";
456 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
457 interrupt-parent = <&plic>;