1 menu "CPU errata selection"
6 select RISCV_ALTERNATIVE
8 All SiFive errata Kconfig depend on this Kconfig. Disabling
9 this Kconfig will disable all SiFive errata. Please say "Y"
10 here if your platform uses SiFive CPU cores.
12 Otherwise, please say "N" here to avoid unnecessary overhead.
14 config ERRATA_SIFIVE_CIP_453
15 bool "Apply SiFive errata CIP-453"
16 depends on ERRATA_SIFIVE && 64BIT
19 This will apply the SiFive CIP-453 errata to add sign extension
20 to the $badaddr when exception type is instruction page fault
21 and instruction access fault.
23 If you don't know what to do here, say "Y".
25 config ERRATA_SIFIVE_CIP_1200
26 bool "Apply SiFive errata CIP-1200"
27 depends on ERRATA_SIFIVE && 64BIT
30 This will apply the SiFive CIP-1200 errata to repalce all
31 "sfence.vma addr" with "sfence.vma" to ensure that the addr
32 has been flushed from TLB.
34 If you don't know what to do here, say "Y".
38 select RISCV_ALTERNATIVE
40 All T-HEAD errata Kconfig depend on this Kconfig. Disabling
41 this Kconfig will disable all T-HEAD errata. Please say "Y"
42 here if your platform uses T-HEAD CPU cores.
44 Otherwise, please say "N" here to avoid unnecessary overhead.
46 config ERRATA_THEAD_PBMT
47 bool "Apply T-Head memory type errata"
48 depends on ERRATA_THEAD && 64BIT
49 select RISCV_ALTERNATIVE_EARLY
52 This will apply the memory type errata to handle the non-standard
53 memory type bits in page-table-entries on T-Head SoCs.
55 If you don't know what to do here, say "Y".