1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_QEMU_VIRT
15 bool "Support QEMU Virt Board"
17 config TARGET_SIFIVE_FU540
18 bool "Support SiFive FU540 Board"
23 bool "Do not enable icache"
26 Do not enable instruction cache in U-Boot.
28 config SPL_SYS_ICACHE_OFF
29 bool "Do not enable icache in SPL"
31 default SYS_ICACHE_OFF
33 Do not enable instruction cache in SPL.
36 bool "Do not enable dcache"
39 Do not enable data cache in U-Boot.
41 config SPL_SYS_DCACHE_OFF
42 bool "Do not enable dcache in SPL"
44 default SYS_DCACHE_OFF
46 Do not enable data cache in SPL.
48 # board-specific options below
49 source "board/AndesTech/ax25-ae350/Kconfig"
50 source "board/emulation/qemu-riscv/Kconfig"
51 source "board/sifive/fu540/Kconfig"
53 # platform-specific options below
54 source "arch/riscv/cpu/ax25/Kconfig"
55 source "arch/riscv/cpu/generic/Kconfig"
57 # architecture-specific options below
67 Choose this option to target the RV32I base integer instruction set.
74 Choose this option to target the RV64I base integer instruction set.
83 bool "medium low code model"
85 U-Boot and its statically defined symbols must lie within a single 2 GiB
86 address range and must lie between absolute addresses -2 GiB and +2 GiB.
89 bool "medium any code model"
91 U-Boot and its statically defined symbols must be within any single 2 GiB
103 Choose this option to build U-Boot for RISC-V M-Mode.
108 Choose this option to build U-Boot for RISC-V S-Mode.
113 bool "Emit compressed instructions"
116 Adds "C" to the ISA subsets that the toolchain is allowed to emit
117 when building U-Boot, which results in compressed instructions in the
131 depends on RISCV_MMODE
135 The SiFive CLINT block holds memory-mapped control and status registers
136 associated with software and timer interrupts.
140 depends on RISCV_MMODE
144 The Andes PLIC block holds memory-mapped claim and pending registers
145 associated with software interrupt.
149 depends on RISCV_MMODE
153 The Andes PLMT block holds memory-mapped mtime register
154 associated with timer tick.
158 default y if RISCV_SMODE
160 The provides the riscv_get_time() API that is implemented using the
161 standard rdtime instruction. This is the case for S-mode U-Boot, and
162 is useful for processors that support rdtime in M-mode too.
164 config SYS_MALLOC_F_LEN
168 bool "Symmetric Multi-Processing"
170 This enables support for systems with more than one CPU. If
171 you say N here, U-Boot will run on single and multiprocessor
172 machines, but will use only one CPU of a multiprocessor
173 machine. If you say Y here, U-Boot will run on many, but not
174 all, single processor machines.
177 int "Maximum number of CPUs (2-32)"
182 On multiprocessor machines, U-Boot sets up a stack for each CPU.
183 Stack memory is pre-allocated. U-Boot must therefore know the
184 maximum number of CPUs that may be present.
188 default y if RISCV_SMODE
194 XIP (eXecute In Place) is a method for executing code directly
195 from a NOR flash memory without copying the code to ram.
196 Say yes here if U-Boot boots from flash directly.
198 config STACK_SIZE_SHIFT