1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_FU540
21 bool "Support SiFive FU540 Board"
23 config TARGET_SIPEED_MAIX
24 bool "Support Sipeed Maix Board"
29 bool "Do not enable icache"
32 Do not enable instruction cache in U-Boot.
34 config SPL_SYS_ICACHE_OFF
35 bool "Do not enable icache in SPL"
37 default SYS_ICACHE_OFF
39 Do not enable instruction cache in SPL.
42 bool "Do not enable dcache"
45 Do not enable data cache in U-Boot.
47 config SPL_SYS_DCACHE_OFF
48 bool "Do not enable dcache in SPL"
50 default SYS_DCACHE_OFF
52 Do not enable data cache in SPL.
54 # board-specific options below
55 source "board/AndesTech/ax25-ae350/Kconfig"
56 source "board/emulation/qemu-riscv/Kconfig"
57 source "board/microchip/mpfs_icicle/Kconfig"
58 source "board/sifive/fu540/Kconfig"
59 source "board/sipeed/maix/Kconfig"
61 # platform-specific options below
62 source "arch/riscv/cpu/ax25/Kconfig"
63 source "arch/riscv/cpu/fu540/Kconfig"
64 source "arch/riscv/cpu/generic/Kconfig"
66 # architecture-specific options below
76 Choose this option to target the RV32I base integer instruction set.
83 Choose this option to target the RV64I base integer instruction set.
92 bool "medium low code model"
94 U-Boot and its statically defined symbols must lie within a single 2 GiB
95 address range and must lie between absolute addresses -2 GiB and +2 GiB.
98 bool "medium any code model"
100 U-Boot and its statically defined symbols must be within any single 2 GiB
112 Choose this option to build U-Boot for RISC-V M-Mode.
117 Choose this option to build U-Boot for RISC-V S-Mode.
122 prompt "SPL Run Mode"
123 default SPL_RISCV_MMODE
126 config SPL_RISCV_MMODE
129 Choose this option to build U-Boot SPL for RISC-V M-Mode.
131 config SPL_RISCV_SMODE
134 Choose this option to build U-Boot SPL for RISC-V S-Mode.
139 bool "Emit compressed instructions"
142 Adds "C" to the ISA subsets that the toolchain is allowed to emit
143 when building U-Boot, which results in compressed instructions in the
155 config DMA_ADDR_T_64BIT
161 depends on RISCV_MMODE || SPL_RISCV_MMODE
163 The SiFive CLINT block holds memory-mapped control and status registers
164 associated with software and timer interrupts.
168 depends on RISCV_MMODE || SPL_RISCV_MMODE
171 select SPL_REGMAP if SPL
172 select SPL_SYSCON if SPL
174 The Andes PLIC block holds memory-mapped claim and pending registers
175 associated with software interrupt.
177 config SYS_MALLOC_F_LEN
181 bool "Symmetric Multi-Processing"
182 depends on SBI_V01 || !RISCV_SMODE
184 This enables support for systems with more than one CPU. If
185 you say N here, U-Boot will run on single and multiprocessor
186 machines, but will use only one CPU of a multiprocessor
187 machine. If you say Y here, U-Boot will run on many, but not
188 all, single processor machines.
191 bool "Symmetric Multi-Processing in SPL"
192 depends on SPL && SPL_RISCV_MMODE
195 This enables support for systems with more than one CPU in SPL.
196 If you say N here, U-Boot SPL will run on single and multiprocessor
197 machines, but will use only one CPU of a multiprocessor
198 machine. If you say Y here, U-Boot SPL will run on many, but not
199 all, single processor machines.
202 int "Maximum number of CPUs (2-32)"
204 depends on SMP || SPL_SMP
207 On multiprocessor machines, U-Boot sets up a stack for each CPU.
208 Stack memory is pre-allocated. U-Boot must therefore know the
209 maximum number of CPUs that may be present.
213 default y if RISCV_SMODE || SPL_RISCV_SMODE
220 bool "SBI v0.1 support"
223 This config allows kernel to use SBI v0.1 APIs. This will be
224 deprecated in future once legacy M-mode software are no longer in use.
227 bool "SBI v0.2 support"
230 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
231 scalable and extendable to handle future needs for RISC-V supervisor
232 interfaces. For example, with SBI v0.2 HSM extension, only a single
233 hart need to boot and enter operating system. The booting hart can
234 bring up secondary harts one by one afterwards.
236 Choose this option if OpenSBI v0.7 or above release is used together
244 default y if RISCV_SMODE || SPL_RISCV_SMODE
250 XIP (eXecute In Place) is a method for executing code directly
251 from a NOR flash memory without copying the code to ram.
252 Say yes here if U-Boot boots from flash directly.
255 bool "Show registers on unhandled exception"
257 config RISCV_PRIV_1_9
258 bool "Use version 1.9 of the RISC-V priviledged specification"
260 Older versions of the RISC-V priviledged specification had
261 separate counter enable CSRs for each privilege mode. Writing
262 to the unified mcounteren CSR on a processor implementing the
263 old specification will result in an illegal instruction
264 exception. In addition to counter CSR changes, the way virtual
265 memory is configured was also changed.
267 config STACK_SIZE_SHIFT
271 config OF_BOARD_FIXUP
272 default y if OF_SEPARATE && RISCV_SMODE