1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
23 config TARGET_SIFIVE_UNMATCHED
24 bool "Support SiFive Unmatched Board"
25 select SYS_CACHE_SHIFT_6
27 config TARGET_SIPEED_MAIX
28 bool "Support Sipeed Maix Board"
29 select SYS_CACHE_SHIFT_6
31 config TARGET_OPENPITON_RISCV64
32 bool "Support RISC-V cores on OpenPiton SoC"
37 bool "Do not enable icache"
40 Do not enable instruction cache in U-Boot.
42 config SPL_SYS_ICACHE_OFF
43 bool "Do not enable icache in SPL"
45 default SYS_ICACHE_OFF
47 Do not enable instruction cache in SPL.
50 bool "Do not enable dcache"
53 Do not enable data cache in U-Boot.
55 config SPL_SYS_DCACHE_OFF
56 bool "Do not enable dcache in SPL"
58 default SYS_DCACHE_OFF
60 Do not enable data cache in SPL.
62 # board-specific options below
63 source "board/AndesTech/ax25-ae350/Kconfig"
64 source "board/emulation/qemu-riscv/Kconfig"
65 source "board/microchip/mpfs_icicle/Kconfig"
66 source "board/sifive/unleashed/Kconfig"
67 source "board/sifive/unmatched/Kconfig"
68 source "board/openpiton/riscv64/Kconfig"
69 source "board/sipeed/maix/Kconfig"
71 # platform-specific options below
72 source "arch/riscv/cpu/ax25/Kconfig"
73 source "arch/riscv/cpu/fu540/Kconfig"
74 source "arch/riscv/cpu/fu740/Kconfig"
75 source "arch/riscv/cpu/generic/Kconfig"
77 # architecture-specific options below
87 Choose this option to target the RV32I base integer instruction set.
94 Choose this option to target the RV64I base integer instruction set.
100 default CMODEL_MEDLOW
103 bool "medium low code model"
105 U-Boot and its statically defined symbols must lie within a single 2 GiB
106 address range and must lie between absolute addresses -2 GiB and +2 GiB.
109 bool "medium any code model"
111 U-Boot and its statically defined symbols must be within any single 2 GiB
123 Choose this option to build U-Boot for RISC-V M-Mode.
128 Choose this option to build U-Boot for RISC-V S-Mode.
133 prompt "SPL Run Mode"
134 default SPL_RISCV_MMODE
137 config SPL_RISCV_MMODE
140 Choose this option to build U-Boot SPL for RISC-V M-Mode.
142 config SPL_RISCV_SMODE
145 Choose this option to build U-Boot SPL for RISC-V S-Mode.
150 bool "Emit compressed instructions"
153 Adds "C" to the ISA subsets that the toolchain is allowed to emit
154 when building U-Boot, which results in compressed instructions in the
166 config DMA_ADDR_T_64BIT
172 depends on RISCV_MMODE
174 The SiFive CLINT block holds memory-mapped control and status registers
175 associated with software and timer interrupts.
177 config SPL_SIFIVE_CLINT
179 depends on SPL_RISCV_MMODE
181 The SiFive CLINT block holds memory-mapped control and status registers
182 associated with software and timer interrupts.
186 depends on RISCV_MMODE || SPL_RISCV_MMODE
189 select SPL_REGMAP if SPL
190 select SPL_SYSCON if SPL
192 The Andes PLIC block holds memory-mapped claim and pending registers
193 associated with software interrupt.
195 config SYS_MALLOC_F_LEN
199 bool "Symmetric Multi-Processing"
200 depends on SBI_V01 || !RISCV_SMODE
202 This enables support for systems with more than one CPU. If
203 you say N here, U-Boot will run on single and multiprocessor
204 machines, but will use only one CPU of a multiprocessor
205 machine. If you say Y here, U-Boot will run on many, but not
206 all, single processor machines.
209 bool "Symmetric Multi-Processing in SPL"
210 depends on SPL && SPL_RISCV_MMODE
213 This enables support for systems with more than one CPU in SPL.
214 If you say N here, U-Boot SPL will run on single and multiprocessor
215 machines, but will use only one CPU of a multiprocessor
216 machine. If you say Y here, U-Boot SPL will run on many, but not
217 all, single processor machines.
220 int "Maximum number of CPUs (2-32)"
222 depends on SMP || SPL_SMP
225 On multiprocessor machines, U-Boot sets up a stack for each CPU.
226 Stack memory is pre-allocated. U-Boot must therefore know the
227 maximum number of CPUs that may be present.
231 default y if RISCV_SMODE || SPL_RISCV_SMODE
238 bool "SBI v0.1 support"
241 This config allows kernel to use SBI v0.1 APIs. This will be
242 deprecated in future once legacy M-mode software are no longer in use.
245 bool "SBI v0.2 support"
248 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
249 scalable and extendable to handle future needs for RISC-V supervisor
250 interfaces. For example, with SBI v0.2 HSM extension, only a single
251 hart need to boot and enter operating system. The booting hart can
252 bring up secondary harts one by one afterwards.
254 Choose this option if OpenSBI v0.7 or above release is used together
262 default y if RISCV_SMODE || SPL_RISCV_SMODE
268 XIP (eXecute In Place) is a method for executing code directly
269 from a NOR flash memory without copying the code to ram.
270 Say yes here if U-Boot boots from flash directly.
273 bool "Show registers on unhandled exception"
275 config RISCV_PRIV_1_9
276 bool "Use version 1.9 of the RISC-V priviledged specification"
278 Older versions of the RISC-V priviledged specification had
279 separate counter enable CSRs for each privilege mode. Writing
280 to the unified mcounteren CSR on a processor implementing the
281 old specification will result in an illegal instruction
282 exception. In addition to counter CSR changes, the way virtual
283 memory is configured was also changed.
285 config STACK_SIZE_SHIFT
289 config OF_BOARD_FIXUP
290 default y if OF_SEPARATE && RISCV_SMODE
292 menu "Use assembly optimized implementation of memory routines"
294 config USE_ARCH_MEMCPY
295 bool "Use an assembly optimized implementation of memcpy"
298 Enable the generation of an optimized version of memcpy.
299 Such an implementation may be faster under some conditions
300 but may increase the binary size.
302 config SPL_USE_ARCH_MEMCPY
303 bool "Use an assembly optimized implementation of memcpy for SPL"
304 default y if USE_ARCH_MEMCPY
307 Enable the generation of an optimized version of memcpy.
308 Such an implementation may be faster under some conditions
309 but may increase the binary size.
311 config TPL_USE_ARCH_MEMCPY
312 bool "Use an assembly optimized implementation of memcpy for TPL"
313 default y if USE_ARCH_MEMCPY
316 Enable the generation of an optimized version of memcpy.
317 Such an implementation may be faster under some conditions
318 but may increase the binary size.
320 config USE_ARCH_MEMMOVE
321 bool "Use an assembly optimized implementation of memmove"
324 Enable the generation of an optimized version of memmove.
325 Such an implementation may be faster under some conditions
326 but may increase the binary size.
328 config SPL_USE_ARCH_MEMMOVE
329 bool "Use an assembly optimized implementation of memmove for SPL"
330 default y if USE_ARCH_MEMCPY
333 Enable the generation of an optimized version of memmove.
334 Such an implementation may be faster under some conditions
335 but may increase the binary size.
337 config TPL_USE_ARCH_MEMMOVE
338 bool "Use an assembly optimized implementation of memmove for TPL"
339 default y if USE_ARCH_MEMCPY
342 Enable the generation of an optimized version of memmove.
343 Such an implementation may be faster under some conditions
344 but may increase the binary size.
346 config USE_ARCH_MEMSET
347 bool "Use an assembly optimized implementation of memset"
350 Enable the generation of an optimized version of memset.
351 Such an implementation may be faster under some conditions
352 but may increase the binary size.
354 config SPL_USE_ARCH_MEMSET
355 bool "Use an assembly optimized implementation of memset for SPL"
356 default y if USE_ARCH_MEMSET
359 Enable the generation of an optimized version of memset.
360 Such an implementation may be faster under some conditions
361 but may increase the binary size.
363 config TPL_USE_ARCH_MEMSET
364 bool "Use an assembly optimized implementation of memset for TPL"
365 default y if USE_ARCH_MEMSET
368 Enable the generation of an optimized version of memset.
369 Such an implementation may be faster under some conditions
370 but may increase the binary size.