1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
23 config TARGET_SIFIVE_UNMATCHED
24 bool "Support SiFive Unmatched Board"
26 config TARGET_SIPEED_MAIX
27 bool "Support Sipeed Maix Board"
32 bool "Do not enable icache"
35 Do not enable instruction cache in U-Boot.
37 config SPL_SYS_ICACHE_OFF
38 bool "Do not enable icache in SPL"
40 default SYS_ICACHE_OFF
42 Do not enable instruction cache in SPL.
45 bool "Do not enable dcache"
48 Do not enable data cache in U-Boot.
50 config SPL_SYS_DCACHE_OFF
51 bool "Do not enable dcache in SPL"
53 default SYS_DCACHE_OFF
55 Do not enable data cache in SPL.
57 # board-specific options below
58 source "board/AndesTech/ax25-ae350/Kconfig"
59 source "board/emulation/qemu-riscv/Kconfig"
60 source "board/microchip/mpfs_icicle/Kconfig"
61 source "board/sifive/unleashed/Kconfig"
62 source "board/sifive/unmatched/Kconfig"
63 source "board/sipeed/maix/Kconfig"
65 # platform-specific options below
66 source "arch/riscv/cpu/ax25/Kconfig"
67 source "arch/riscv/cpu/fu540/Kconfig"
68 source "arch/riscv/cpu/fu740/Kconfig"
69 source "arch/riscv/cpu/generic/Kconfig"
71 # architecture-specific options below
81 Choose this option to target the RV32I base integer instruction set.
88 Choose this option to target the RV64I base integer instruction set.
97 bool "medium low code model"
99 U-Boot and its statically defined symbols must lie within a single 2 GiB
100 address range and must lie between absolute addresses -2 GiB and +2 GiB.
103 bool "medium any code model"
105 U-Boot and its statically defined symbols must be within any single 2 GiB
117 Choose this option to build U-Boot for RISC-V M-Mode.
122 Choose this option to build U-Boot for RISC-V S-Mode.
127 prompt "SPL Run Mode"
128 default SPL_RISCV_MMODE
131 config SPL_RISCV_MMODE
134 Choose this option to build U-Boot SPL for RISC-V M-Mode.
136 config SPL_RISCV_SMODE
139 Choose this option to build U-Boot SPL for RISC-V S-Mode.
144 bool "Emit compressed instructions"
147 Adds "C" to the ISA subsets that the toolchain is allowed to emit
148 when building U-Boot, which results in compressed instructions in the
160 config DMA_ADDR_T_64BIT
166 depends on RISCV_MMODE
168 The SiFive CLINT block holds memory-mapped control and status registers
169 associated with software and timer interrupts.
171 config SPL_SIFIVE_CLINT
173 depends on SPL_RISCV_MMODE
175 The SiFive CLINT block holds memory-mapped control and status registers
176 associated with software and timer interrupts.
180 depends on RISCV_MMODE || SPL_RISCV_MMODE
183 select SPL_REGMAP if SPL
184 select SPL_SYSCON if SPL
186 The Andes PLIC block holds memory-mapped claim and pending registers
187 associated with software interrupt.
189 config SYS_MALLOC_F_LEN
193 bool "Symmetric Multi-Processing"
194 depends on SBI_V01 || !RISCV_SMODE
196 This enables support for systems with more than one CPU. If
197 you say N here, U-Boot will run on single and multiprocessor
198 machines, but will use only one CPU of a multiprocessor
199 machine. If you say Y here, U-Boot will run on many, but not
200 all, single processor machines.
203 bool "Symmetric Multi-Processing in SPL"
204 depends on SPL && SPL_RISCV_MMODE
207 This enables support for systems with more than one CPU in SPL.
208 If you say N here, U-Boot SPL will run on single and multiprocessor
209 machines, but will use only one CPU of a multiprocessor
210 machine. If you say Y here, U-Boot SPL will run on many, but not
211 all, single processor machines.
214 int "Maximum number of CPUs (2-32)"
216 depends on SMP || SPL_SMP
219 On multiprocessor machines, U-Boot sets up a stack for each CPU.
220 Stack memory is pre-allocated. U-Boot must therefore know the
221 maximum number of CPUs that may be present.
225 default y if RISCV_SMODE || SPL_RISCV_SMODE
232 bool "SBI v0.1 support"
235 This config allows kernel to use SBI v0.1 APIs. This will be
236 deprecated in future once legacy M-mode software are no longer in use.
239 bool "SBI v0.2 support"
242 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
243 scalable and extendable to handle future needs for RISC-V supervisor
244 interfaces. For example, with SBI v0.2 HSM extension, only a single
245 hart need to boot and enter operating system. The booting hart can
246 bring up secondary harts one by one afterwards.
248 Choose this option if OpenSBI v0.7 or above release is used together
256 default y if RISCV_SMODE || SPL_RISCV_SMODE
262 XIP (eXecute In Place) is a method for executing code directly
263 from a NOR flash memory without copying the code to ram.
264 Say yes here if U-Boot boots from flash directly.
267 bool "Show registers on unhandled exception"
269 config RISCV_PRIV_1_9
270 bool "Use version 1.9 of the RISC-V priviledged specification"
272 Older versions of the RISC-V priviledged specification had
273 separate counter enable CSRs for each privilege mode. Writing
274 to the unified mcounteren CSR on a processor implementing the
275 old specification will result in an illegal instruction
276 exception. In addition to counter CSR changes, the way virtual
277 memory is configured was also changed.
279 config STACK_SIZE_SHIFT
283 config OF_BOARD_FIXUP
284 default y if OF_SEPARATE && RISCV_SMODE
286 menu "Use assembly optimized implementation of memory routines"
288 config USE_ARCH_MEMCPY
289 bool "Use an assembly optimized implementation of memcpy"
292 Enable the generation of an optimized version of memcpy.
293 Such an implementation may be faster under some conditions
294 but may increase the binary size.
296 config SPL_USE_ARCH_MEMCPY
297 bool "Use an assembly optimized implementation of memcpy for SPL"
298 default y if USE_ARCH_MEMCPY
301 Enable the generation of an optimized version of memcpy.
302 Such an implementation may be faster under some conditions
303 but may increase the binary size.
305 config TPL_USE_ARCH_MEMCPY
306 bool "Use an assembly optimized implementation of memcpy for TPL"
307 default y if USE_ARCH_MEMCPY
310 Enable the generation of an optimized version of memcpy.
311 Such an implementation may be faster under some conditions
312 but may increase the binary size.
314 config USE_ARCH_MEMMOVE
315 bool "Use an assembly optimized implementation of memmove"
318 Enable the generation of an optimized version of memmove.
319 Such an implementation may be faster under some conditions
320 but may increase the binary size.
322 config SPL_USE_ARCH_MEMMOVE
323 bool "Use an assembly optimized implementation of memmove for SPL"
324 default y if USE_ARCH_MEMCPY
327 Enable the generation of an optimized version of memmove.
328 Such an implementation may be faster under some conditions
329 but may increase the binary size.
331 config TPL_USE_ARCH_MEMMOVE
332 bool "Use an assembly optimized implementation of memmove for TPL"
333 default y if USE_ARCH_MEMCPY
336 Enable the generation of an optimized version of memmove.
337 Such an implementation may be faster under some conditions
338 but may increase the binary size.
340 config USE_ARCH_MEMSET
341 bool "Use an assembly optimized implementation of memset"
344 Enable the generation of an optimized version of memset.
345 Such an implementation may be faster under some conditions
346 but may increase the binary size.
348 config SPL_USE_ARCH_MEMSET
349 bool "Use an assembly optimized implementation of memset for SPL"
350 default y if USE_ARCH_MEMSET
353 Enable the generation of an optimized version of memset.
354 Such an implementation may be faster under some conditions
355 but may increase the binary size.
357 config TPL_USE_ARCH_MEMSET
358 bool "Use an assembly optimized implementation of memset for TPL"
359 default y if USE_ARCH_MEMSET
362 Enable the generation of an optimized version of memset.
363 Such an implementation may be faster under some conditions
364 but may increase the binary size.