1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
23 config TARGET_SIPEED_MAIX
24 bool "Support Sipeed Maix Board"
29 bool "Do not enable icache"
32 Do not enable instruction cache in U-Boot.
34 config SPL_SYS_ICACHE_OFF
35 bool "Do not enable icache in SPL"
37 default SYS_ICACHE_OFF
39 Do not enable instruction cache in SPL.
42 bool "Do not enable dcache"
45 Do not enable data cache in U-Boot.
47 config SPL_SYS_DCACHE_OFF
48 bool "Do not enable dcache in SPL"
50 default SYS_DCACHE_OFF
52 Do not enable data cache in SPL.
54 # board-specific options below
55 source "board/AndesTech/ax25-ae350/Kconfig"
56 source "board/emulation/qemu-riscv/Kconfig"
57 source "board/microchip/mpfs_icicle/Kconfig"
58 source "board/sifive/unleashed/Kconfig"
59 source "board/sipeed/maix/Kconfig"
61 # platform-specific options below
62 source "arch/riscv/cpu/ax25/Kconfig"
63 source "arch/riscv/cpu/fu540/Kconfig"
64 source "arch/riscv/cpu/fu740/Kconfig"
65 source "arch/riscv/cpu/generic/Kconfig"
67 # architecture-specific options below
77 Choose this option to target the RV32I base integer instruction set.
84 Choose this option to target the RV64I base integer instruction set.
93 bool "medium low code model"
95 U-Boot and its statically defined symbols must lie within a single 2 GiB
96 address range and must lie between absolute addresses -2 GiB and +2 GiB.
99 bool "medium any code model"
101 U-Boot and its statically defined symbols must be within any single 2 GiB
113 Choose this option to build U-Boot for RISC-V M-Mode.
118 Choose this option to build U-Boot for RISC-V S-Mode.
123 prompt "SPL Run Mode"
124 default SPL_RISCV_MMODE
127 config SPL_RISCV_MMODE
130 Choose this option to build U-Boot SPL for RISC-V M-Mode.
132 config SPL_RISCV_SMODE
135 Choose this option to build U-Boot SPL for RISC-V S-Mode.
140 bool "Emit compressed instructions"
143 Adds "C" to the ISA subsets that the toolchain is allowed to emit
144 when building U-Boot, which results in compressed instructions in the
156 config DMA_ADDR_T_64BIT
162 depends on RISCV_MMODE
164 The SiFive CLINT block holds memory-mapped control and status registers
165 associated with software and timer interrupts.
167 config SPL_SIFIVE_CLINT
169 depends on SPL_RISCV_MMODE
171 The SiFive CLINT block holds memory-mapped control and status registers
172 associated with software and timer interrupts.
176 depends on RISCV_MMODE || SPL_RISCV_MMODE
179 select SPL_REGMAP if SPL
180 select SPL_SYSCON if SPL
182 The Andes PLIC block holds memory-mapped claim and pending registers
183 associated with software interrupt.
185 config SYS_MALLOC_F_LEN
189 bool "Symmetric Multi-Processing"
190 depends on SBI_V01 || !RISCV_SMODE
192 This enables support for systems with more than one CPU. If
193 you say N here, U-Boot will run on single and multiprocessor
194 machines, but will use only one CPU of a multiprocessor
195 machine. If you say Y here, U-Boot will run on many, but not
196 all, single processor machines.
199 bool "Symmetric Multi-Processing in SPL"
200 depends on SPL && SPL_RISCV_MMODE
203 This enables support for systems with more than one CPU in SPL.
204 If you say N here, U-Boot SPL will run on single and multiprocessor
205 machines, but will use only one CPU of a multiprocessor
206 machine. If you say Y here, U-Boot SPL will run on many, but not
207 all, single processor machines.
210 int "Maximum number of CPUs (2-32)"
212 depends on SMP || SPL_SMP
215 On multiprocessor machines, U-Boot sets up a stack for each CPU.
216 Stack memory is pre-allocated. U-Boot must therefore know the
217 maximum number of CPUs that may be present.
221 default y if RISCV_SMODE || SPL_RISCV_SMODE
228 bool "SBI v0.1 support"
231 This config allows kernel to use SBI v0.1 APIs. This will be
232 deprecated in future once legacy M-mode software are no longer in use.
235 bool "SBI v0.2 support"
238 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
239 scalable and extendable to handle future needs for RISC-V supervisor
240 interfaces. For example, with SBI v0.2 HSM extension, only a single
241 hart need to boot and enter operating system. The booting hart can
242 bring up secondary harts one by one afterwards.
244 Choose this option if OpenSBI v0.7 or above release is used together
252 default y if RISCV_SMODE || SPL_RISCV_SMODE
258 XIP (eXecute In Place) is a method for executing code directly
259 from a NOR flash memory without copying the code to ram.
260 Say yes here if U-Boot boots from flash directly.
263 bool "Show registers on unhandled exception"
265 config RISCV_PRIV_1_9
266 bool "Use version 1.9 of the RISC-V priviledged specification"
268 Older versions of the RISC-V priviledged specification had
269 separate counter enable CSRs for each privilege mode. Writing
270 to the unified mcounteren CSR on a processor implementing the
271 old specification will result in an illegal instruction
272 exception. In addition to counter CSR changes, the way virtual
273 memory is configured was also changed.
275 config STACK_SIZE_SHIFT
279 config OF_BOARD_FIXUP
280 default y if OF_SEPARATE && RISCV_SMODE
282 menu "Use assembly optimized implementation of memory routines"
284 config USE_ARCH_MEMCPY
285 bool "Use an assembly optimized implementation of memcpy"
288 Enable the generation of an optimized version of memcpy.
289 Such an implementation may be faster under some conditions
290 but may increase the binary size.
292 config SPL_USE_ARCH_MEMCPY
293 bool "Use an assembly optimized implementation of memcpy for SPL"
294 default y if USE_ARCH_MEMCPY
297 Enable the generation of an optimized version of memcpy.
298 Such an implementation may be faster under some conditions
299 but may increase the binary size.
301 config TPL_USE_ARCH_MEMCPY
302 bool "Use an assembly optimized implementation of memcpy for TPL"
303 default y if USE_ARCH_MEMCPY
306 Enable the generation of an optimized version of memcpy.
307 Such an implementation may be faster under some conditions
308 but may increase the binary size.
310 config USE_ARCH_MEMMOVE
311 bool "Use an assembly optimized implementation of memmove"
314 Enable the generation of an optimized version of memmove.
315 Such an implementation may be faster under some conditions
316 but may increase the binary size.
318 config SPL_USE_ARCH_MEMMOVE
319 bool "Use an assembly optimized implementation of memmove for SPL"
320 default y if USE_ARCH_MEMCPY
323 Enable the generation of an optimized version of memmove.
324 Such an implementation may be faster under some conditions
325 but may increase the binary size.
327 config TPL_USE_ARCH_MEMMOVE
328 bool "Use an assembly optimized implementation of memmove for TPL"
329 default y if USE_ARCH_MEMCPY
332 Enable the generation of an optimized version of memmove.
333 Such an implementation may be faster under some conditions
334 but may increase the binary size.
336 config USE_ARCH_MEMSET
337 bool "Use an assembly optimized implementation of memset"
340 Enable the generation of an optimized version of memset.
341 Such an implementation may be faster under some conditions
342 but may increase the binary size.
344 config SPL_USE_ARCH_MEMSET
345 bool "Use an assembly optimized implementation of memset for SPL"
346 default y if USE_ARCH_MEMSET
349 Enable the generation of an optimized version of memset.
350 Such an implementation may be faster under some conditions
351 but may increase the binary size.
353 config TPL_USE_ARCH_MEMSET
354 bool "Use an assembly optimized implementation of memset for TPL"
355 default y if USE_ARCH_MEMSET
358 Enable the generation of an optimized version of memset.
359 Such an implementation may be faster under some conditions
360 but may increase the binary size.