1 menu "RISC-V architecture"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
23 config TARGET_SIFIVE_UNMATCHED
24 bool "Support SiFive Unmatched Board"
25 select SYS_CACHE_SHIFT_6
27 config TARGET_STARFIVE_VISIONFIVE2
28 bool "Support StarFive VisionFive2 Board"
30 config TARGET_TH1520_LPI4A
31 bool "Support Sipeed's TH1520 Lichee PI 4A Board"
32 select SYS_CACHE_SHIFT_6
34 config TARGET_SIPEED_MAIX
35 bool "Support Sipeed Maix Board"
36 select SYS_CACHE_SHIFT_6
38 config TARGET_OPENPITON_RISCV64
39 bool "Support RISC-V cores on OpenPiton SoC"
44 bool "Do not enable icache"
46 Do not enable instruction cache in U-Boot.
48 config SPL_SYS_ICACHE_OFF
49 bool "Do not enable icache in SPL"
51 default SYS_ICACHE_OFF
53 Do not enable instruction cache in SPL.
56 bool "Do not enable dcache"
58 Do not enable data cache in U-Boot.
60 config SPL_SYS_DCACHE_OFF
61 bool "Do not enable dcache in SPL"
63 default SYS_DCACHE_OFF
65 Do not enable data cache in SPL.
67 config SPL_ZERO_MEM_BEFORE_USE
68 bool "Zero memory before use"
72 Zero stack/GD/malloc area in SPL before using them, this is needed for
73 Sifive core devices that uses L2 cache to store SPL.
75 # board-specific options below
76 source "board/AndesTech/ae350/Kconfig"
77 source "board/emulation/qemu-riscv/Kconfig"
78 source "board/microchip/mpfs_icicle/Kconfig"
79 source "board/sifive/unleashed/Kconfig"
80 source "board/sifive/unmatched/Kconfig"
81 source "board/thead/th1520_lpi4a/Kconfig"
82 source "board/openpiton/riscv64/Kconfig"
83 source "board/sipeed/maix/Kconfig"
84 source "board/starfive/visionfive2/Kconfig"
86 # platform-specific options below
87 source "arch/riscv/cpu/andesv5/Kconfig"
88 source "arch/riscv/cpu/fu540/Kconfig"
89 source "arch/riscv/cpu/fu740/Kconfig"
90 source "arch/riscv/cpu/generic/Kconfig"
91 source "arch/riscv/cpu/jh7110/Kconfig"
93 # architecture-specific options below
103 Choose this option to target the RV32I base integer instruction set.
110 Choose this option to target the RV64I base integer instruction set.
116 default CMODEL_MEDLOW
119 bool "medium low code model"
121 U-Boot and its statically defined symbols must lie within a single 2 GiB
122 address range and must lie between absolute addresses -2 GiB and +2 GiB.
125 bool "medium any code model"
127 U-Boot and its statically defined symbols must be within any single 2 GiB
139 Choose this option to build U-Boot for RISC-V M-Mode.
144 Choose this option to build U-Boot for RISC-V S-Mode.
149 prompt "SPL Run Mode"
150 default SPL_RISCV_MMODE
153 config SPL_RISCV_MMODE
156 Choose this option to build U-Boot SPL for RISC-V M-Mode.
158 config SPL_RISCV_SMODE
161 Choose this option to build U-Boot SPL for RISC-V S-Mode.
166 bool "Emit compressed instructions"
169 Adds "C" to the ISA subsets that the toolchain is allowed to emit
170 when building U-Boot, which results in compressed instructions in the
174 bool "Standard extension for Single-Precision Floating Point"
177 Adds "F" to the ISA string passed to the compiler.
180 bool "Standard extension for Double-Precision Floating Point"
181 depends on RISCV_ISA_F
184 Adds "D" to the ISA string passed to the compiler and changes the
185 riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
197 config DMA_ADDR_T_64BIT
203 depends on RISCV_MMODE
207 The RISC-V ACLINT block holds memory-mapped control and status registers
208 associated with software and timer interrupts.
210 config SPL_RISCV_ACLINT
212 depends on SPL_RISCV_MMODE
216 The RISC-V ACLINT block holds memory-mapped control and status registers
217 associated with software and timer interrupts.
222 This enables the operations to configure SiFive cache
226 depends on RISCV_MMODE || SPL_RISCV_MMODE
229 select SPL_REGMAP if SPL
230 select SPL_SYSCON if SPL
232 The Andes PLICSW block holds memory-mapped claim and pending
233 registers associated with software interrupt.
236 bool "Symmetric Multi-Processing"
237 depends on SBI_V01 || !RISCV_SMODE
239 This enables support for systems with more than one CPU. If
240 you say N here, U-Boot will run on single and multiprocessor
241 machines, but will use only one CPU of a multiprocessor
242 machine. If you say Y here, U-Boot will run on many, but not
243 all, single processor machines.
246 bool "Symmetric Multi-Processing in SPL"
247 depends on SPL && SPL_RISCV_MMODE
250 This enables support for systems with more than one CPU in SPL.
251 If you say N here, U-Boot SPL will run on single and multiprocessor
252 machines, but will use only one CPU of a multiprocessor
253 machine. If you say Y here, U-Boot SPL will run on many, but not
254 all, single processor machines.
257 int "Maximum number of CPUs (2-32)"
259 depends on SMP || SPL_SMP
262 On multiprocessor machines, U-Boot sets up a stack for each CPU.
263 Stack memory is pre-allocated. U-Boot must therefore know the
264 maximum number of CPUs that may be present.
268 default y if RISCV_SMODE || SPL_RISCV_SMODE
275 bool "SBI v0.1 support"
278 This config allows kernel to use SBI v0.1 APIs. This will be
279 deprecated in future once legacy M-mode software are no longer in use.
282 bool "SBI v0.2 or later support"
285 The SBI specification introduced the concept of extensions in version
286 v0.2. With this configuration option U-Boot can detect and use SBI
287 extensions. With the HSM extension introduced in SBI 0.2, only a
288 single hart needs to boot and enter the operating system. The booting
289 hart can bring up secondary harts one by one afterwards.
291 Choose this option if OpenSBI release v0.7 or above is used together
299 default y if RISCV_SMODE || SPL_RISCV_SMODE
305 XIP (eXecute In Place) is a method for executing code directly
306 from a NOR flash memory without copying the code to ram.
307 Say yes here if U-Boot boots from flash directly.
310 bool "Enable XIP mode for SPL"
312 If SPL starts in read-only memory (XIP for example) then we shouldn't
313 rely on lock variables (for example hart_lottery and available_harts_lock),
314 this affects only SPL, other stages should proceed as non-XIP.
316 config AVAILABLE_HARTS
317 bool "Send IPI by available harts"
320 By default, IPI sending mechanism will depend on available_harts.
321 If disable this, it will send IPI by CPUs node numbers of device tree.
324 bool "Show registers on unhandled exception"
326 config RISCV_PRIV_1_9
327 bool "Use version 1.9 of the RISC-V priviledged specification"
329 Older versions of the RISC-V priviledged specification had
330 separate counter enable CSRs for each privilege mode. Writing
331 to the unified mcounteren CSR on a processor implementing the
332 old specification will result in an illegal instruction
333 exception. In addition to counter CSR changes, the way virtual
334 memory is configured was also changed.
336 config STACK_SIZE_SHIFT
340 config OF_BOARD_FIXUP
341 default y if OF_SEPARATE && RISCV_SMODE
343 menu "Use assembly optimized implementation of memory routines"
345 config USE_ARCH_MEMCPY
346 bool "Use an assembly optimized implementation of memcpy"
349 Enable the generation of an optimized version of memcpy.
350 Such an implementation may be faster under some conditions
351 but may increase the binary size.
353 config SPL_USE_ARCH_MEMCPY
354 bool "Use an assembly optimized implementation of memcpy for SPL"
355 default y if USE_ARCH_MEMCPY
358 Enable the generation of an optimized version of memcpy.
359 Such an implementation may be faster under some conditions
360 but may increase the binary size.
362 config TPL_USE_ARCH_MEMCPY
363 bool "Use an assembly optimized implementation of memcpy for TPL"
364 default y if USE_ARCH_MEMCPY
367 Enable the generation of an optimized version of memcpy.
368 Such an implementation may be faster under some conditions
369 but may increase the binary size.
371 config USE_ARCH_MEMMOVE
372 bool "Use an assembly optimized implementation of memmove"
375 Enable the generation of an optimized version of memmove.
376 Such an implementation may be faster under some conditions
377 but may increase the binary size.
379 config SPL_USE_ARCH_MEMMOVE
380 bool "Use an assembly optimized implementation of memmove for SPL"
381 default y if USE_ARCH_MEMCPY
384 Enable the generation of an optimized version of memmove.
385 Such an implementation may be faster under some conditions
386 but may increase the binary size.
388 config TPL_USE_ARCH_MEMMOVE
389 bool "Use an assembly optimized implementation of memmove for TPL"
390 default y if USE_ARCH_MEMCPY
393 Enable the generation of an optimized version of memmove.
394 Such an implementation may be faster under some conditions
395 but may increase the binary size.
397 config USE_ARCH_MEMSET
398 bool "Use an assembly optimized implementation of memset"
401 Enable the generation of an optimized version of memset.
402 Such an implementation may be faster under some conditions
403 but may increase the binary size.
405 config SPL_USE_ARCH_MEMSET
406 bool "Use an assembly optimized implementation of memset for SPL"
407 default y if USE_ARCH_MEMSET
410 Enable the generation of an optimized version of memset.
411 Such an implementation may be faster under some conditions
412 but may increase the binary size.
414 config TPL_USE_ARCH_MEMSET
415 bool "Use an assembly optimized implementation of memset for TPL"
416 default y if USE_ARCH_MEMSET
419 Enable the generation of an optimized version of memset.
420 Such an implementation may be faster under some conditions
421 but may increase the binary size.