1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
23 config TARGET_SIFIVE_UNMATCHED
24 bool "Support SiFive Unmatched Board"
26 config TARGET_SIPEED_MAIX
27 bool "Support Sipeed Maix Board"
29 config TARGET_OPENPITON_RISCV64
30 bool "Support RISC-V cores on OpenPiton SoC"
35 bool "Do not enable icache"
38 Do not enable instruction cache in U-Boot.
40 config SPL_SYS_ICACHE_OFF
41 bool "Do not enable icache in SPL"
43 default SYS_ICACHE_OFF
45 Do not enable instruction cache in SPL.
48 bool "Do not enable dcache"
51 Do not enable data cache in U-Boot.
53 config SPL_SYS_DCACHE_OFF
54 bool "Do not enable dcache in SPL"
56 default SYS_DCACHE_OFF
58 Do not enable data cache in SPL.
60 # board-specific options below
61 source "board/AndesTech/ax25-ae350/Kconfig"
62 source "board/emulation/qemu-riscv/Kconfig"
63 source "board/microchip/mpfs_icicle/Kconfig"
64 source "board/sifive/unleashed/Kconfig"
65 source "board/sifive/unmatched/Kconfig"
66 source "board/openpiton/riscv64/Kconfig"
67 source "board/sipeed/maix/Kconfig"
69 # platform-specific options below
70 source "arch/riscv/cpu/ax25/Kconfig"
71 source "arch/riscv/cpu/fu540/Kconfig"
72 source "arch/riscv/cpu/fu740/Kconfig"
73 source "arch/riscv/cpu/generic/Kconfig"
75 # architecture-specific options below
85 Choose this option to target the RV32I base integer instruction set.
92 Choose this option to target the RV64I base integer instruction set.
101 bool "medium low code model"
103 U-Boot and its statically defined symbols must lie within a single 2 GiB
104 address range and must lie between absolute addresses -2 GiB and +2 GiB.
107 bool "medium any code model"
109 U-Boot and its statically defined symbols must be within any single 2 GiB
121 Choose this option to build U-Boot for RISC-V M-Mode.
126 Choose this option to build U-Boot for RISC-V S-Mode.
131 prompt "SPL Run Mode"
132 default SPL_RISCV_MMODE
135 config SPL_RISCV_MMODE
138 Choose this option to build U-Boot SPL for RISC-V M-Mode.
140 config SPL_RISCV_SMODE
143 Choose this option to build U-Boot SPL for RISC-V S-Mode.
148 bool "Emit compressed instructions"
151 Adds "C" to the ISA subsets that the toolchain is allowed to emit
152 when building U-Boot, which results in compressed instructions in the
164 config DMA_ADDR_T_64BIT
170 depends on RISCV_MMODE
172 The SiFive CLINT block holds memory-mapped control and status registers
173 associated with software and timer interrupts.
175 config SPL_SIFIVE_CLINT
177 depends on SPL_RISCV_MMODE
179 The SiFive CLINT block holds memory-mapped control and status registers
180 associated with software and timer interrupts.
184 depends on RISCV_MMODE || SPL_RISCV_MMODE
187 select SPL_REGMAP if SPL
188 select SPL_SYSCON if SPL
190 The Andes PLIC block holds memory-mapped claim and pending registers
191 associated with software interrupt.
193 config SYS_MALLOC_F_LEN
197 bool "Symmetric Multi-Processing"
198 depends on SBI_V01 || !RISCV_SMODE
200 This enables support for systems with more than one CPU. If
201 you say N here, U-Boot will run on single and multiprocessor
202 machines, but will use only one CPU of a multiprocessor
203 machine. If you say Y here, U-Boot will run on many, but not
204 all, single processor machines.
207 bool "Symmetric Multi-Processing in SPL"
208 depends on SPL && SPL_RISCV_MMODE
211 This enables support for systems with more than one CPU in SPL.
212 If you say N here, U-Boot SPL will run on single and multiprocessor
213 machines, but will use only one CPU of a multiprocessor
214 machine. If you say Y here, U-Boot SPL will run on many, but not
215 all, single processor machines.
218 int "Maximum number of CPUs (2-32)"
220 depends on SMP || SPL_SMP
223 On multiprocessor machines, U-Boot sets up a stack for each CPU.
224 Stack memory is pre-allocated. U-Boot must therefore know the
225 maximum number of CPUs that may be present.
229 default y if RISCV_SMODE || SPL_RISCV_SMODE
236 bool "SBI v0.1 support"
239 This config allows kernel to use SBI v0.1 APIs. This will be
240 deprecated in future once legacy M-mode software are no longer in use.
243 bool "SBI v0.2 support"
246 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
247 scalable and extendable to handle future needs for RISC-V supervisor
248 interfaces. For example, with SBI v0.2 HSM extension, only a single
249 hart need to boot and enter operating system. The booting hart can
250 bring up secondary harts one by one afterwards.
252 Choose this option if OpenSBI v0.7 or above release is used together
260 default y if RISCV_SMODE || SPL_RISCV_SMODE
266 XIP (eXecute In Place) is a method for executing code directly
267 from a NOR flash memory without copying the code to ram.
268 Say yes here if U-Boot boots from flash directly.
271 bool "Show registers on unhandled exception"
273 config RISCV_PRIV_1_9
274 bool "Use version 1.9 of the RISC-V priviledged specification"
276 Older versions of the RISC-V priviledged specification had
277 separate counter enable CSRs for each privilege mode. Writing
278 to the unified mcounteren CSR on a processor implementing the
279 old specification will result in an illegal instruction
280 exception. In addition to counter CSR changes, the way virtual
281 memory is configured was also changed.
283 config STACK_SIZE_SHIFT
287 config OF_BOARD_FIXUP
288 default y if OF_SEPARATE && RISCV_SMODE
290 menu "Use assembly optimized implementation of memory routines"
292 config USE_ARCH_MEMCPY
293 bool "Use an assembly optimized implementation of memcpy"
296 Enable the generation of an optimized version of memcpy.
297 Such an implementation may be faster under some conditions
298 but may increase the binary size.
300 config SPL_USE_ARCH_MEMCPY
301 bool "Use an assembly optimized implementation of memcpy for SPL"
302 default y if USE_ARCH_MEMCPY
305 Enable the generation of an optimized version of memcpy.
306 Such an implementation may be faster under some conditions
307 but may increase the binary size.
309 config TPL_USE_ARCH_MEMCPY
310 bool "Use an assembly optimized implementation of memcpy for TPL"
311 default y if USE_ARCH_MEMCPY
314 Enable the generation of an optimized version of memcpy.
315 Such an implementation may be faster under some conditions
316 but may increase the binary size.
318 config USE_ARCH_MEMMOVE
319 bool "Use an assembly optimized implementation of memmove"
322 Enable the generation of an optimized version of memmove.
323 Such an implementation may be faster under some conditions
324 but may increase the binary size.
326 config SPL_USE_ARCH_MEMMOVE
327 bool "Use an assembly optimized implementation of memmove for SPL"
328 default y if USE_ARCH_MEMCPY
331 Enable the generation of an optimized version of memmove.
332 Such an implementation may be faster under some conditions
333 but may increase the binary size.
335 config TPL_USE_ARCH_MEMMOVE
336 bool "Use an assembly optimized implementation of memmove for TPL"
337 default y if USE_ARCH_MEMCPY
340 Enable the generation of an optimized version of memmove.
341 Such an implementation may be faster under some conditions
342 but may increase the binary size.
344 config USE_ARCH_MEMSET
345 bool "Use an assembly optimized implementation of memset"
348 Enable the generation of an optimized version of memset.
349 Such an implementation may be faster under some conditions
350 but may increase the binary size.
352 config SPL_USE_ARCH_MEMSET
353 bool "Use an assembly optimized implementation of memset for SPL"
354 default y if USE_ARCH_MEMSET
357 Enable the generation of an optimized version of memset.
358 Such an implementation may be faster under some conditions
359 but may increase the binary size.
361 config TPL_USE_ARCH_MEMSET
362 bool "Use an assembly optimized implementation of memset for TPL"
363 default y if USE_ARCH_MEMSET
366 Enable the generation of an optimized version of memset.
367 Such an implementation may be faster under some conditions
368 but may increase the binary size.