1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
23 config TARGET_SIFIVE_UNMATCHED
24 bool "Support SiFive Unmatched Board"
25 select SYS_CACHE_SHIFT_6
27 config TARGET_SIPEED_MAIX
28 bool "Support Sipeed Maix Board"
29 select SYS_CACHE_SHIFT_6
31 config TARGET_OPENPITON_RISCV64
32 bool "Support RISC-V cores on OpenPiton SoC"
37 bool "Do not enable icache"
39 Do not enable instruction cache in U-Boot.
41 config SPL_SYS_ICACHE_OFF
42 bool "Do not enable icache in SPL"
44 default SYS_ICACHE_OFF
46 Do not enable instruction cache in SPL.
49 bool "Do not enable dcache"
51 Do not enable data cache in U-Boot.
53 config SPL_SYS_DCACHE_OFF
54 bool "Do not enable dcache in SPL"
56 default SYS_DCACHE_OFF
58 Do not enable data cache in SPL.
60 # board-specific options below
61 source "board/AndesTech/ax25-ae350/Kconfig"
62 source "board/emulation/qemu-riscv/Kconfig"
63 source "board/microchip/mpfs_icicle/Kconfig"
64 source "board/sifive/unleashed/Kconfig"
65 source "board/sifive/unmatched/Kconfig"
66 source "board/openpiton/riscv64/Kconfig"
67 source "board/sipeed/maix/Kconfig"
69 # platform-specific options below
70 source "arch/riscv/cpu/ax25/Kconfig"
71 source "arch/riscv/cpu/fu540/Kconfig"
72 source "arch/riscv/cpu/fu740/Kconfig"
73 source "arch/riscv/cpu/generic/Kconfig"
75 # architecture-specific options below
85 Choose this option to target the RV32I base integer instruction set.
92 Choose this option to target the RV64I base integer instruction set.
101 bool "medium low code model"
103 U-Boot and its statically defined symbols must lie within a single 2 GiB
104 address range and must lie between absolute addresses -2 GiB and +2 GiB.
107 bool "medium any code model"
109 U-Boot and its statically defined symbols must be within any single 2 GiB
121 Choose this option to build U-Boot for RISC-V M-Mode.
126 Choose this option to build U-Boot for RISC-V S-Mode.
131 prompt "SPL Run Mode"
132 default SPL_RISCV_MMODE
135 config SPL_RISCV_MMODE
138 Choose this option to build U-Boot SPL for RISC-V M-Mode.
140 config SPL_RISCV_SMODE
143 Choose this option to build U-Boot SPL for RISC-V S-Mode.
148 bool "Emit compressed instructions"
151 Adds "C" to the ISA subsets that the toolchain is allowed to emit
152 when building U-Boot, which results in compressed instructions in the
156 bool "Standard extension for Single-Precision Floating Point"
159 Adds "F" to the ISA string passed to the compiler.
162 bool "Standard extension for Double-Precision Floating Point"
163 depends on RISCV_ISA_F
166 Adds "D" to the ISA string passed to the compiler and changes the
167 riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
179 config DMA_ADDR_T_64BIT
185 depends on RISCV_MMODE
187 The SiFive CLINT block holds memory-mapped control and status registers
188 associated with software and timer interrupts.
190 config SPL_SIFIVE_CLINT
192 depends on SPL_RISCV_MMODE
194 The SiFive CLINT block holds memory-mapped control and status registers
195 associated with software and timer interrupts.
200 This enables the operations to configure SiFive cache
204 depends on RISCV_MMODE || SPL_RISCV_MMODE
207 select SPL_REGMAP if SPL
208 select SPL_SYSCON if SPL
210 The Andes PLIC block holds memory-mapped claim and pending registers
211 associated with software interrupt.
214 bool "Symmetric Multi-Processing"
215 depends on SBI_V01 || !RISCV_SMODE
217 This enables support for systems with more than one CPU. If
218 you say N here, U-Boot will run on single and multiprocessor
219 machines, but will use only one CPU of a multiprocessor
220 machine. If you say Y here, U-Boot will run on many, but not
221 all, single processor machines.
224 bool "Symmetric Multi-Processing in SPL"
225 depends on SPL && SPL_RISCV_MMODE
228 This enables support for systems with more than one CPU in SPL.
229 If you say N here, U-Boot SPL will run on single and multiprocessor
230 machines, but will use only one CPU of a multiprocessor
231 machine. If you say Y here, U-Boot SPL will run on many, but not
232 all, single processor machines.
235 int "Maximum number of CPUs (2-32)"
237 depends on SMP || SPL_SMP
240 On multiprocessor machines, U-Boot sets up a stack for each CPU.
241 Stack memory is pre-allocated. U-Boot must therefore know the
242 maximum number of CPUs that may be present.
246 default y if RISCV_SMODE || SPL_RISCV_SMODE
253 bool "SBI v0.1 support"
256 This config allows kernel to use SBI v0.1 APIs. This will be
257 deprecated in future once legacy M-mode software are no longer in use.
260 bool "SBI v0.2 support"
263 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
264 scalable and extendable to handle future needs for RISC-V supervisor
265 interfaces. For example, with SBI v0.2 HSM extension, only a single
266 hart need to boot and enter operating system. The booting hart can
267 bring up secondary harts one by one afterwards.
269 Choose this option if OpenSBI v0.7 or above release is used together
277 default y if RISCV_SMODE || SPL_RISCV_SMODE
283 XIP (eXecute In Place) is a method for executing code directly
284 from a NOR flash memory without copying the code to ram.
285 Say yes here if U-Boot boots from flash directly.
288 bool "Enable XIP mode for SPL"
290 If SPL starts in read-only memory (XIP for example) then we shouldn't
291 rely on lock variables (for example hart_lottery and available_harts_lock),
292 this affects only SPL, other stages should proceed as non-XIP.
294 config AVAILABLE_HARTS
295 bool "Send IPI by available harts"
298 By default, IPI sending mechanism will depend on available_harts.
299 If disable this, it will send IPI by CPUs node numbers of device tree.
302 bool "Show registers on unhandled exception"
304 config RISCV_PRIV_1_9
305 bool "Use version 1.9 of the RISC-V priviledged specification"
307 Older versions of the RISC-V priviledged specification had
308 separate counter enable CSRs for each privilege mode. Writing
309 to the unified mcounteren CSR on a processor implementing the
310 old specification will result in an illegal instruction
311 exception. In addition to counter CSR changes, the way virtual
312 memory is configured was also changed.
314 config STACK_SIZE_SHIFT
318 config OF_BOARD_FIXUP
319 default y if OF_SEPARATE && RISCV_SMODE
321 menu "Use assembly optimized implementation of memory routines"
323 config USE_ARCH_MEMCPY
324 bool "Use an assembly optimized implementation of memcpy"
327 Enable the generation of an optimized version of memcpy.
328 Such an implementation may be faster under some conditions
329 but may increase the binary size.
331 config SPL_USE_ARCH_MEMCPY
332 bool "Use an assembly optimized implementation of memcpy for SPL"
333 default y if USE_ARCH_MEMCPY
336 Enable the generation of an optimized version of memcpy.
337 Such an implementation may be faster under some conditions
338 but may increase the binary size.
340 config TPL_USE_ARCH_MEMCPY
341 bool "Use an assembly optimized implementation of memcpy for TPL"
342 default y if USE_ARCH_MEMCPY
345 Enable the generation of an optimized version of memcpy.
346 Such an implementation may be faster under some conditions
347 but may increase the binary size.
349 config USE_ARCH_MEMMOVE
350 bool "Use an assembly optimized implementation of memmove"
353 Enable the generation of an optimized version of memmove.
354 Such an implementation may be faster under some conditions
355 but may increase the binary size.
357 config SPL_USE_ARCH_MEMMOVE
358 bool "Use an assembly optimized implementation of memmove for SPL"
359 default y if USE_ARCH_MEMCPY
362 Enable the generation of an optimized version of memmove.
363 Such an implementation may be faster under some conditions
364 but may increase the binary size.
366 config TPL_USE_ARCH_MEMMOVE
367 bool "Use an assembly optimized implementation of memmove for TPL"
368 default y if USE_ARCH_MEMCPY
371 Enable the generation of an optimized version of memmove.
372 Such an implementation may be faster under some conditions
373 but may increase the binary size.
375 config USE_ARCH_MEMSET
376 bool "Use an assembly optimized implementation of memset"
379 Enable the generation of an optimized version of memset.
380 Such an implementation may be faster under some conditions
381 but may increase the binary size.
383 config SPL_USE_ARCH_MEMSET
384 bool "Use an assembly optimized implementation of memset for SPL"
385 default y if USE_ARCH_MEMSET
388 Enable the generation of an optimized version of memset.
389 Such an implementation may be faster under some conditions
390 but may increase the binary size.
392 config TPL_USE_ARCH_MEMSET
393 bool "Use an assembly optimized implementation of memset for TPL"
394 default y if USE_ARCH_MEMSET
397 Enable the generation of an optimized version of memset.
398 Such an implementation may be faster under some conditions
399 but may increase the binary size.