1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_UNLEASHED
21 bool "Support SiFive Unleashed Board"
23 config TARGET_SIPEED_MAIX
24 bool "Support Sipeed Maix Board"
29 bool "Do not enable icache"
32 Do not enable instruction cache in U-Boot.
34 config SPL_SYS_ICACHE_OFF
35 bool "Do not enable icache in SPL"
37 default SYS_ICACHE_OFF
39 Do not enable instruction cache in SPL.
42 bool "Do not enable dcache"
45 Do not enable data cache in U-Boot.
47 config SPL_SYS_DCACHE_OFF
48 bool "Do not enable dcache in SPL"
50 default SYS_DCACHE_OFF
52 Do not enable data cache in SPL.
54 # board-specific options below
55 source "board/AndesTech/ax25-ae350/Kconfig"
56 source "board/emulation/qemu-riscv/Kconfig"
57 source "board/microchip/mpfs_icicle/Kconfig"
58 source "board/sifive/unleashed/Kconfig"
59 source "board/sipeed/maix/Kconfig"
61 # platform-specific options below
62 source "arch/riscv/cpu/ax25/Kconfig"
63 source "arch/riscv/cpu/fu540/Kconfig"
64 source "arch/riscv/cpu/generic/Kconfig"
66 # architecture-specific options below
76 Choose this option to target the RV32I base integer instruction set.
83 Choose this option to target the RV64I base integer instruction set.
92 bool "medium low code model"
94 U-Boot and its statically defined symbols must lie within a single 2 GiB
95 address range and must lie between absolute addresses -2 GiB and +2 GiB.
98 bool "medium any code model"
100 U-Boot and its statically defined symbols must be within any single 2 GiB
112 Choose this option to build U-Boot for RISC-V M-Mode.
117 Choose this option to build U-Boot for RISC-V S-Mode.
122 prompt "SPL Run Mode"
123 default SPL_RISCV_MMODE
126 config SPL_RISCV_MMODE
129 Choose this option to build U-Boot SPL for RISC-V M-Mode.
131 config SPL_RISCV_SMODE
134 Choose this option to build U-Boot SPL for RISC-V S-Mode.
139 bool "Emit compressed instructions"
142 Adds "C" to the ISA subsets that the toolchain is allowed to emit
143 when building U-Boot, which results in compressed instructions in the
155 config DMA_ADDR_T_64BIT
161 depends on RISCV_MMODE
163 The SiFive CLINT block holds memory-mapped control and status registers
164 associated with software and timer interrupts.
166 config SPL_SIFIVE_CLINT
168 depends on SPL_RISCV_MMODE
170 The SiFive CLINT block holds memory-mapped control and status registers
171 associated with software and timer interrupts.
175 depends on RISCV_MMODE || SPL_RISCV_MMODE
178 select SPL_REGMAP if SPL
179 select SPL_SYSCON if SPL
181 The Andes PLIC block holds memory-mapped claim and pending registers
182 associated with software interrupt.
184 config SYS_MALLOC_F_LEN
188 bool "Symmetric Multi-Processing"
189 depends on SBI_V01 || !RISCV_SMODE
191 This enables support for systems with more than one CPU. If
192 you say N here, U-Boot will run on single and multiprocessor
193 machines, but will use only one CPU of a multiprocessor
194 machine. If you say Y here, U-Boot will run on many, but not
195 all, single processor machines.
198 bool "Symmetric Multi-Processing in SPL"
199 depends on SPL && SPL_RISCV_MMODE
202 This enables support for systems with more than one CPU in SPL.
203 If you say N here, U-Boot SPL will run on single and multiprocessor
204 machines, but will use only one CPU of a multiprocessor
205 machine. If you say Y here, U-Boot SPL will run on many, but not
206 all, single processor machines.
209 int "Maximum number of CPUs (2-32)"
211 depends on SMP || SPL_SMP
214 On multiprocessor machines, U-Boot sets up a stack for each CPU.
215 Stack memory is pre-allocated. U-Boot must therefore know the
216 maximum number of CPUs that may be present.
220 default y if RISCV_SMODE || SPL_RISCV_SMODE
227 bool "SBI v0.1 support"
230 This config allows kernel to use SBI v0.1 APIs. This will be
231 deprecated in future once legacy M-mode software are no longer in use.
234 bool "SBI v0.2 support"
237 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
238 scalable and extendable to handle future needs for RISC-V supervisor
239 interfaces. For example, with SBI v0.2 HSM extension, only a single
240 hart need to boot and enter operating system. The booting hart can
241 bring up secondary harts one by one afterwards.
243 Choose this option if OpenSBI v0.7 or above release is used together
251 default y if RISCV_SMODE || SPL_RISCV_SMODE
257 XIP (eXecute In Place) is a method for executing code directly
258 from a NOR flash memory without copying the code to ram.
259 Say yes here if U-Boot boots from flash directly.
262 bool "Show registers on unhandled exception"
264 config RISCV_PRIV_1_9
265 bool "Use version 1.9 of the RISC-V priviledged specification"
267 Older versions of the RISC-V priviledged specification had
268 separate counter enable CSRs for each privilege mode. Writing
269 to the unified mcounteren CSR on a processor implementing the
270 old specification will result in an illegal instruction
271 exception. In addition to counter CSR changes, the way virtual
272 memory is configured was also changed.
274 config STACK_SIZE_SHIFT
278 config OF_BOARD_FIXUP
279 default y if OF_SEPARATE && RISCV_SMODE
281 menu "Use assembly optimized implementation of memory routines"
283 config USE_ARCH_MEMCPY
284 bool "Use an assembly optimized implementation of memcpy"
287 Enable the generation of an optimized version of memcpy.
288 Such an implementation may be faster under some conditions
289 but may increase the binary size.
291 config SPL_USE_ARCH_MEMCPY
292 bool "Use an assembly optimized implementation of memcpy for SPL"
293 default y if USE_ARCH_MEMCPY
296 Enable the generation of an optimized version of memcpy.
297 Such an implementation may be faster under some conditions
298 but may increase the binary size.
300 config TPL_USE_ARCH_MEMCPY
301 bool "Use an assembly optimized implementation of memcpy for TPL"
302 default y if USE_ARCH_MEMCPY
305 Enable the generation of an optimized version of memcpy.
306 Such an implementation may be faster under some conditions
307 but may increase the binary size.
309 config USE_ARCH_MEMMOVE
310 bool "Use an assembly optimized implementation of memmove"
313 Enable the generation of an optimized version of memmove.
314 Such an implementation may be faster under some conditions
315 but may increase the binary size.
317 config SPL_USE_ARCH_MEMMOVE
318 bool "Use an assembly optimized implementation of memmove for SPL"
319 default y if USE_ARCH_MEMCPY
322 Enable the generation of an optimized version of memmove.
323 Such an implementation may be faster under some conditions
324 but may increase the binary size.
326 config TPL_USE_ARCH_MEMMOVE
327 bool "Use an assembly optimized implementation of memmove for TPL"
328 default y if USE_ARCH_MEMCPY
331 Enable the generation of an optimized version of memmove.
332 Such an implementation may be faster under some conditions
333 but may increase the binary size.
335 config USE_ARCH_MEMSET
336 bool "Use an assembly optimized implementation of memset"
339 Enable the generation of an optimized version of memset.
340 Such an implementation may be faster under some conditions
341 but may increase the binary size.
343 config SPL_USE_ARCH_MEMSET
344 bool "Use an assembly optimized implementation of memset for SPL"
345 default y if USE_ARCH_MEMSET
348 Enable the generation of an optimized version of memset.
349 Such an implementation may be faster under some conditions
350 but may increase the binary size.
352 config TPL_USE_ARCH_MEMSET
353 bool "Use an assembly optimized implementation of memset for TPL"
354 default y if USE_ARCH_MEMSET
357 Enable the generation of an optimized version of memset.
358 Such an implementation may be faster under some conditions
359 but may increase the binary size.