1 menu "RISC-V architecture"
11 config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
14 config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
17 config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
20 config TARGET_SIFIVE_FU540
21 bool "Support SiFive FU540 Board"
23 config TARGET_SIPEED_MAIX
24 bool "Support Sipeed Maix Board"
29 bool "Do not enable icache"
32 Do not enable instruction cache in U-Boot.
34 config SPL_SYS_ICACHE_OFF
35 bool "Do not enable icache in SPL"
37 default SYS_ICACHE_OFF
39 Do not enable instruction cache in SPL.
42 bool "Do not enable dcache"
45 Do not enable data cache in U-Boot.
47 config SPL_SYS_DCACHE_OFF
48 bool "Do not enable dcache in SPL"
50 default SYS_DCACHE_OFF
52 Do not enable data cache in SPL.
54 # board-specific options below
55 source "board/AndesTech/ax25-ae350/Kconfig"
56 source "board/emulation/qemu-riscv/Kconfig"
57 source "board/microchip/mpfs_icicle/Kconfig"
58 source "board/sifive/fu540/Kconfig"
59 source "board/sipeed/maix/Kconfig"
61 # platform-specific options below
62 source "arch/riscv/cpu/ax25/Kconfig"
63 source "arch/riscv/cpu/fu540/Kconfig"
64 source "arch/riscv/cpu/generic/Kconfig"
66 # architecture-specific options below
76 Choose this option to target the RV32I base integer instruction set.
83 Choose this option to target the RV64I base integer instruction set.
92 bool "medium low code model"
94 U-Boot and its statically defined symbols must lie within a single 2 GiB
95 address range and must lie between absolute addresses -2 GiB and +2 GiB.
98 bool "medium any code model"
100 U-Boot and its statically defined symbols must be within any single 2 GiB
112 Choose this option to build U-Boot for RISC-V M-Mode.
117 Choose this option to build U-Boot for RISC-V S-Mode.
122 prompt "SPL Run Mode"
123 default SPL_RISCV_MMODE
126 config SPL_RISCV_MMODE
129 Choose this option to build U-Boot SPL for RISC-V M-Mode.
131 config SPL_RISCV_SMODE
134 Choose this option to build U-Boot SPL for RISC-V S-Mode.
139 bool "Emit compressed instructions"
142 Adds "C" to the ISA subsets that the toolchain is allowed to emit
143 when building U-Boot, which results in compressed instructions in the
157 depends on RISCV_MMODE || SPL_RISCV_MMODE
159 The SiFive CLINT block holds memory-mapped control and status registers
160 associated with software and timer interrupts.
164 depends on RISCV_MMODE || SPL_RISCV_MMODE
167 select SPL_REGMAP if SPL
168 select SPL_SYSCON if SPL
170 The Andes PLIC block holds memory-mapped claim and pending registers
171 associated with software interrupt.
173 config SYS_MALLOC_F_LEN
177 bool "Symmetric Multi-Processing"
178 depends on SBI_V01 || !RISCV_SMODE
180 This enables support for systems with more than one CPU. If
181 you say N here, U-Boot will run on single and multiprocessor
182 machines, but will use only one CPU of a multiprocessor
183 machine. If you say Y here, U-Boot will run on many, but not
184 all, single processor machines.
187 bool "Symmetric Multi-Processing in SPL"
188 depends on SPL && SPL_RISCV_MMODE
191 This enables support for systems with more than one CPU in SPL.
192 If you say N here, U-Boot SPL will run on single and multiprocessor
193 machines, but will use only one CPU of a multiprocessor
194 machine. If you say Y here, U-Boot SPL will run on many, but not
195 all, single processor machines.
198 int "Maximum number of CPUs (2-32)"
200 depends on SMP || SPL_SMP
203 On multiprocessor machines, U-Boot sets up a stack for each CPU.
204 Stack memory is pre-allocated. U-Boot must therefore know the
205 maximum number of CPUs that may be present.
209 default y if RISCV_SMODE || SPL_RISCV_SMODE
216 bool "SBI v0.1 support"
219 This config allows kernel to use SBI v0.1 APIs. This will be
220 deprecated in future once legacy M-mode software are no longer in use.
223 bool "SBI v0.2 support"
226 This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
227 scalable and extendable to handle future needs for RISC-V supervisor
228 interfaces. For example, with SBI v0.2 HSM extension, only a single
229 hart need to boot and enter operating system. The booting hart can
230 bring up secondary harts one by one afterwards.
232 Choose this option if OpenSBI v0.7 or above release is used together
240 default y if RISCV_SMODE || SPL_RISCV_SMODE
246 XIP (eXecute In Place) is a method for executing code directly
247 from a NOR flash memory without copying the code to ram.
248 Say yes here if U-Boot boots from flash directly.
251 bool "Show registers on unhandled exception"
253 config RISCV_PRIV_1_9
254 bool "Use version 1.9 of the RISC-V priviledged specification"
256 Older versions of the RISC-V priviledged specification had
257 separate counter enable CSRs for each privilege mode. Writing
258 to the unified mcounteren CSR on a processor implementing the
259 old specification will result in an illegal instruction
260 exception. In addition to counter CSR changes, the way virtual
261 memory is configured was also changed.
263 config STACK_SIZE_SHIFT
267 config OF_BOARD_FIXUP
268 default y if OF_SEPARATE && RISCV_SMODE