2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/bootmem.h>
17 #include <linux/msi.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/of_platform.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/hw_irq.h>
24 #include <asm/ppc-pci.h>
31 struct fsl_msi_feature {
36 struct fsl_msi_cascade_data {
37 struct fsl_msi *msi_data;
41 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
43 return in_be32(base + (reg >> 2));
47 * We do not need this actually. The MSIR register has been read once
48 * in the cascade interrupt. So, this MSI interrupt has been acked
50 static void fsl_msi_end_irq(struct irq_data *d)
54 static struct irq_chip fsl_msi_chip = {
55 .irq_mask = mask_msi_irq,
56 .irq_unmask = unmask_msi_irq,
57 .irq_ack = fsl_msi_end_irq,
61 static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
64 struct fsl_msi *msi_data = h->host_data;
65 struct irq_chip *chip = &fsl_msi_chip;
67 irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
69 set_irq_chip_data(virq, msi_data);
70 set_irq_chip_and_handler(virq, chip, handle_edge_irq);
75 static struct irq_host_ops fsl_msi_host_ops = {
76 .map = fsl_msi_host_map,
79 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
83 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
84 msi_data->irqhost->of_node);
88 rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
90 msi_bitmap_free(&msi_data->bitmap);
97 static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
99 if (type == PCI_CAP_ID_MSIX)
100 pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
105 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
107 struct msi_desc *entry;
108 struct fsl_msi *msi_data;
110 list_for_each_entry(entry, &pdev->msi_list, list) {
111 if (entry->irq == NO_IRQ)
113 msi_data = get_irq_data(entry->irq);
114 set_irq_msi(entry->irq, NULL);
115 msi_bitmap_free_hwirqs(&msi_data->bitmap,
116 virq_to_hw(entry->irq), 1);
117 irq_dispose_mapping(entry->irq);
123 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
125 struct fsl_msi *fsl_msi_data)
127 struct fsl_msi *msi_data = fsl_msi_data;
128 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
129 u64 base = fsl_pci_immrbar_base(hose);
131 msg->address_lo = msi_data->msi_addr_lo + lower_32_bits(base);
132 msg->address_hi = msi_data->msi_addr_hi + upper_32_bits(base);
136 pr_debug("%s: allocated srs: %d, ibs: %d\n",
137 __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
140 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
142 int rc, hwirq = -ENOMEM;
144 struct msi_desc *entry;
146 struct fsl_msi *msi_data;
148 list_for_each_entry(entry, &pdev->msi_list, list) {
149 list_for_each_entry(msi_data, &msi_head, list) {
150 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
157 pr_debug("%s: fail allocating msi interrupt\n",
162 virq = irq_create_mapping(msi_data->irqhost, hwirq);
164 if (virq == NO_IRQ) {
165 pr_debug("%s: fail mapping hwirq 0x%x\n",
167 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
171 set_irq_data(virq, msi_data);
172 set_irq_msi(virq, entry);
174 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
175 write_msi_msg(virq, &msg);
180 /* free by the caller of this function */
184 static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
186 struct irq_chip *chip = get_irq_desc_chip(desc);
187 unsigned int cascade_irq;
188 struct fsl_msi *msi_data;
193 struct fsl_msi_cascade_data *cascade_data;
195 cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
196 msi_data = cascade_data->msi_data;
198 raw_spin_lock(&desc->lock);
199 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
200 if (chip->irq_mask_ack)
201 chip->irq_mask_ack(&desc->irq_data);
203 chip->irq_mask(&desc->irq_data);
204 chip->irq_ack(&desc->irq_data);
208 if (unlikely(desc->status & IRQ_INPROGRESS))
211 msir_index = cascade_data->index;
213 if (msir_index >= NR_MSI_REG)
214 cascade_irq = NO_IRQ;
216 desc->status |= IRQ_INPROGRESS;
217 switch (msi_data->feature & FSL_PIC_IP_MASK) {
218 case FSL_PIC_IP_MPIC:
219 msir_value = fsl_msi_read(msi_data->msi_regs,
222 case FSL_PIC_IP_IPIC:
223 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
228 intr_index = ffs(msir_value) - 1;
230 cascade_irq = irq_linear_revmap(msi_data->irqhost,
231 msir_index * IRQS_PER_MSI_REG +
232 intr_index + have_shift);
233 if (cascade_irq != NO_IRQ)
234 generic_handle_irq(cascade_irq);
235 have_shift += intr_index + 1;
236 msir_value = msir_value >> (intr_index + 1);
238 desc->status &= ~IRQ_INPROGRESS;
240 switch (msi_data->feature & FSL_PIC_IP_MASK) {
241 case FSL_PIC_IP_MPIC:
242 chip->irq_eoi(&desc->irq_data);
244 case FSL_PIC_IP_IPIC:
245 if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
246 chip->irq_unmask(&desc->irq_data);
250 raw_spin_unlock(&desc->lock);
253 static int fsl_of_msi_remove(struct platform_device *ofdev)
255 struct fsl_msi *msi = ofdev->dev.platform_data;
257 struct fsl_msi_cascade_data *cascade_data;
259 if (msi->list.prev != NULL)
260 list_del(&msi->list);
261 for (i = 0; i < NR_MSI_REG; i++) {
262 virq = msi->msi_virqs[i];
263 if (virq != NO_IRQ) {
264 cascade_data = get_irq_data(virq);
266 irq_dispose_mapping(virq);
269 if (msi->bitmap.bitmap)
270 msi_bitmap_free(&msi->bitmap);
271 iounmap(msi->msi_regs);
277 static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
278 struct platform_device *dev,
279 int offset, int irq_index)
281 struct fsl_msi_cascade_data *cascade_data = NULL;
284 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
285 if (virt_msir == NO_IRQ) {
286 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
287 __func__, irq_index);
291 cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
293 dev_err(&dev->dev, "No memory for MSI cascade data\n");
297 msi->msi_virqs[irq_index] = virt_msir;
298 cascade_data->index = offset + irq_index;
299 cascade_data->msi_data = msi;
300 set_irq_data(virt_msir, cascade_data);
301 set_irq_chained_handler(virt_msir, fsl_msi_cascade);
306 static int __devinit fsl_of_msi_probe(struct platform_device *dev)
310 int err, i, j, irq_index, count;
313 struct fsl_msi_feature *features;
316 static const u32 all_avail[] = { 0, NR_MSI_IRQS };
318 if (!dev->dev.of_match)
320 features = dev->dev.of_match->data;
322 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
324 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
326 dev_err(&dev->dev, "No memory for MSI structure\n");
329 dev->dev.platform_data = msi;
331 msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
332 NR_MSI_IRQS, &fsl_msi_host_ops, 0);
334 if (msi->irqhost == NULL) {
335 dev_err(&dev->dev, "No memory for MSI irqhost\n");
340 /* Get the MSI reg base */
341 err = of_address_to_resource(dev->dev.of_node, 0, &res);
343 dev_err(&dev->dev, "%s resource error!\n",
344 dev->dev.of_node->full_name);
348 msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
349 if (!msi->msi_regs) {
350 dev_err(&dev->dev, "ioremap problem failed\n");
354 msi->feature = features->fsl_pic_ip;
356 msi->irqhost->host_data = msi;
358 msi->msi_addr_hi = 0x0;
359 msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
361 rc = fsl_msi_init_allocator(msi);
363 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
367 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
368 if (p && len % (2 * sizeof(u32)) != 0) {
369 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
378 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
379 if (p[i * 2] % IRQS_PER_MSI_REG ||
380 p[i * 2 + 1] % IRQS_PER_MSI_REG) {
381 printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
382 __func__, dev->dev.of_node->full_name,
383 p[i * 2 + 1], p[i * 2]);
388 offset = p[i * 2] / IRQS_PER_MSI_REG;
389 count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
391 for (j = 0; j < count; j++, irq_index++) {
392 err = fsl_msi_setup_hwirq(msi, dev, offset, irq_index);
398 list_add_tail(&msi->list, &msi_head);
400 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
401 if (!ppc_md.setup_msi_irqs) {
402 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
403 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
404 ppc_md.msi_check_device = fsl_msi_check_device;
405 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
406 dev_err(&dev->dev, "Different MSI driver already installed!\n");
412 fsl_of_msi_remove(dev);
416 static const struct fsl_msi_feature mpic_msi_feature = {
417 .fsl_pic_ip = FSL_PIC_IP_MPIC,
418 .msiir_offset = 0x140,
421 static const struct fsl_msi_feature ipic_msi_feature = {
422 .fsl_pic_ip = FSL_PIC_IP_IPIC,
423 .msiir_offset = 0x38,
426 static const struct of_device_id fsl_of_msi_ids[] = {
428 .compatible = "fsl,mpic-msi",
429 .data = (void *)&mpic_msi_feature,
432 .compatible = "fsl,ipic-msi",
433 .data = (void *)&ipic_msi_feature,
438 static struct platform_driver fsl_of_msi_driver = {
441 .owner = THIS_MODULE,
442 .of_match_table = fsl_of_msi_ids,
444 .probe = fsl_of_msi_probe,
445 .remove = fsl_of_msi_remove,
448 static __init int fsl_of_msi_init(void)
450 return platform_driver_register(&fsl_of_msi_driver);
453 subsys_initcall(fsl_of_msi_init);