2 * arch/powerpc/platforms/pseries/xics.c
4 * Copyright 2000 IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/irq.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/radix-tree.h>
20 #include <linux/cpu.h>
21 #include <linux/msi.h>
23 #include <linux/percpu.h>
25 #include <asm/firmware.h>
27 #include <asm/pgtable.h>
30 #include <asm/hvcall.h>
31 #include <asm/machdep.h>
34 #include "plpar_wrappers.h"
36 static struct irq_host *xics_host;
39 #define XICS_IRQ_SPURIOUS 0
41 /* Want a priority other than 0. Various HW issues require this. */
42 #define DEFAULT_PRIORITY 5
45 * Mark IPIs as higher priority so we can take them inside interrupts that
46 * arent marked IRQF_DISABLED
48 #define IPI_PRIORITY 4
50 /* The least favored priority */
51 #define LOWEST_PRIORITY 0xFF
53 /* The number of priorities defined above */
54 #define MAX_NUM_PRIORITIES 3
56 static unsigned int default_server = 0xFF;
57 static unsigned int default_distrib_server = 0;
58 static unsigned int interrupt_server_size = 8;
60 /* RTAS service tokens */
61 static int ibm_get_xive;
62 static int ibm_set_xive;
63 static int ibm_int_on;
64 static int ibm_int_off;
67 unsigned char stack[MAX_NUM_PRIORITIES];
71 static DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
73 /* Direct hardware low level accessors */
75 /* The part of the interrupt presentation layer that we care about */
92 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
94 static inline unsigned int direct_xirr_info_get(void)
96 int cpu = smp_processor_id();
98 return in_be32(&xics_per_cpu[cpu]->xirr.word);
101 static inline void direct_xirr_info_set(unsigned int value)
103 int cpu = smp_processor_id();
105 out_be32(&xics_per_cpu[cpu]->xirr.word, value);
108 static inline void direct_cppr_info(u8 value)
110 int cpu = smp_processor_id();
112 out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
115 static inline void direct_qirr_info(int n_cpu, u8 value)
117 out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
121 /* LPAR low level accessors */
123 static inline unsigned int lpar_xirr_info_get(unsigned char cppr)
125 unsigned long lpar_rc;
126 unsigned long return_value;
128 lpar_rc = plpar_xirr(&return_value, cppr);
129 if (lpar_rc != H_SUCCESS)
130 panic(" bad return code xirr - rc = %lx\n", lpar_rc);
131 return (unsigned int)return_value;
134 static inline void lpar_xirr_info_set(unsigned int value)
136 unsigned long lpar_rc;
138 lpar_rc = plpar_eoi(value);
139 if (lpar_rc != H_SUCCESS)
140 panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc,
144 static inline void lpar_cppr_info(u8 value)
146 unsigned long lpar_rc;
148 lpar_rc = plpar_cppr(value);
149 if (lpar_rc != H_SUCCESS)
150 panic("bad return code cppr - rc = %lx\n", lpar_rc);
153 static inline void lpar_qirr_info(int n_cpu , u8 value)
155 unsigned long lpar_rc;
157 lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
158 if (lpar_rc != H_SUCCESS)
159 panic("bad return code qirr - rc = %lx\n", lpar_rc);
163 /* Interface to generic irq subsystem */
167 * For the moment we only implement delivery to all cpus or one cpu.
169 * If the requested affinity is cpu_all_mask, we set global affinity.
170 * If not we set it to the first cpu in the mask, even if multiple cpus
171 * are set. This is so things like irqbalance (which set core and package
172 * wide affinities) do the right thing.
174 static int get_irq_server(unsigned int virq, const struct cpumask *cpumask,
175 unsigned int strict_check)
178 if (!distribute_irqs)
179 return default_server;
181 if (!cpumask_subset(cpu_possible_mask, cpumask)) {
182 int server = cpumask_first_and(cpu_online_mask, cpumask);
184 if (server < nr_cpu_ids)
185 return get_hard_smp_processor_id(server);
192 * Workaround issue with some versions of JS20 firmware that
193 * deliver interrupts to cpus which haven't been started. This
194 * happens when using the maxcpus= boot option.
196 if (cpumask_equal(cpu_online_mask, cpu_present_mask))
197 return default_distrib_server;
199 return default_server;
202 #define get_irq_server(virq, cpumask, strict_check) (default_server)
205 static void xics_unmask_irq(unsigned int virq)
211 pr_devel("xics: unmask virq %d\n", virq);
213 irq = (unsigned int)irq_map[virq].hwirq;
214 pr_devel(" -> map to hwirq 0x%x\n", irq);
215 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
218 server = get_irq_server(virq, irq_to_desc(virq)->affinity, 0);
220 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
222 if (call_status != 0) {
224 "%s: ibm_set_xive irq %u server %x returned %d\n",
225 __func__, irq, server, call_status);
229 /* Now unmask the interrupt (often a no-op) */
230 call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
231 if (call_status != 0) {
232 printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n",
233 __func__, irq, call_status);
238 static unsigned int xics_startup(unsigned int virq)
241 * The generic MSI code returns with the interrupt disabled on the
242 * card, using the MSI mask bits. Firmware doesn't appear to unmask
243 * at that level, so we do it here by hand.
245 if (irq_to_desc(virq)->msi_desc)
246 unmask_msi_irq(irq_get_irq_data(virq));
249 xics_unmask_irq(virq);
253 static void xics_mask_real_irq(unsigned int irq)
260 call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
261 if (call_status != 0) {
262 printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n",
263 __func__, irq, call_status);
267 /* Have to set XIVE to 0xff to be able to remove a slot */
268 call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
269 default_server, 0xff);
270 if (call_status != 0) {
271 printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n",
272 __func__, irq, call_status);
277 static void xics_mask_irq(unsigned int virq)
281 pr_devel("xics: mask virq %d\n", virq);
283 irq = (unsigned int)irq_map[virq].hwirq;
284 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
286 xics_mask_real_irq(irq);
289 static void xics_mask_unknown_vec(unsigned int vec)
291 printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
292 xics_mask_real_irq(vec);
295 static inline unsigned int xics_xirr_vector(unsigned int xirr)
298 * The top byte is the old cppr, to be restored on EOI.
299 * The remaining 24 bits are the vector.
301 return xirr & 0x00ffffff;
304 static void push_cppr(unsigned int vec)
306 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
308 if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
312 os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
314 os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
317 static unsigned int xics_get_irq_direct(void)
319 unsigned int xirr = direct_xirr_info_get();
320 unsigned int vec = xics_xirr_vector(xirr);
323 if (vec == XICS_IRQ_SPURIOUS)
326 irq = irq_radix_revmap_lookup(xics_host, vec);
327 if (likely(irq != NO_IRQ)) {
332 /* We don't have a linux mapping, so have rtas mask it. */
333 xics_mask_unknown_vec(vec);
335 /* We might learn about it later, so EOI it */
336 direct_xirr_info_set(xirr);
340 static unsigned int xics_get_irq_lpar(void)
342 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
343 unsigned int xirr = lpar_xirr_info_get(os_cppr->stack[os_cppr->index]);
344 unsigned int vec = xics_xirr_vector(xirr);
347 if (vec == XICS_IRQ_SPURIOUS)
350 irq = irq_radix_revmap_lookup(xics_host, vec);
351 if (likely(irq != NO_IRQ)) {
356 /* We don't have a linux mapping, so have RTAS mask it. */
357 xics_mask_unknown_vec(vec);
359 /* We might learn about it later, so EOI it */
360 lpar_xirr_info_set(xirr);
364 static unsigned char pop_cppr(void)
366 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
368 if (WARN_ON(os_cppr->index < 1))
369 return LOWEST_PRIORITY;
371 return os_cppr->stack[--os_cppr->index];
374 static void xics_eoi_direct(unsigned int virq)
376 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
379 direct_xirr_info_set((pop_cppr() << 24) | irq);
382 static void xics_eoi_lpar(unsigned int virq)
384 unsigned int irq = (unsigned int)irq_map[virq].hwirq;
387 lpar_xirr_info_set((pop_cppr() << 24) | irq);
390 static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
397 irq = (unsigned int)irq_map[virq].hwirq;
398 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
401 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
404 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
405 __func__, irq, status);
409 irq_server = get_irq_server(virq, cpumask, 1);
410 if (irq_server == -1) {
412 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
414 "%s: No online cpus in the mask %s for irq %d\n",
415 __func__, cpulist, virq);
419 status = rtas_call(ibm_set_xive, 3, 1, NULL,
420 irq, irq_server, xics_status[1]);
423 printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n",
424 __func__, irq, status);
431 static struct irq_chip xics_pic_direct = {
433 .startup = xics_startup,
434 .mask = xics_mask_irq,
435 .unmask = xics_unmask_irq,
436 .eoi = xics_eoi_direct,
437 .set_affinity = xics_set_affinity
440 static struct irq_chip xics_pic_lpar = {
442 .startup = xics_startup,
443 .mask = xics_mask_irq,
444 .unmask = xics_unmask_irq,
445 .eoi = xics_eoi_lpar,
446 .set_affinity = xics_set_affinity
450 /* Interface to arch irq controller subsystem layer */
452 /* Points to the irq_chip we're actually using */
453 static struct irq_chip *xics_irq_chip;
455 static int xics_host_match(struct irq_host *h, struct device_node *node)
457 /* IBM machines have interrupt parents of various funky types for things
458 * like vdevices, events, etc... The trick we use here is to match
459 * everything here except the legacy 8259 which is compatible "chrp,iic"
461 return !of_device_is_compatible(node, "chrp,iic");
464 static int xics_host_map(struct irq_host *h, unsigned int virq,
467 pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
469 /* Insert the interrupt mapping into the radix tree for fast lookup */
470 irq_radix_revmap_insert(xics_host, virq, hw);
472 irq_to_desc(virq)->status |= IRQ_LEVEL;
473 set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
477 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
478 const u32 *intspec, unsigned int intsize,
479 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
482 /* Current xics implementation translates everything
483 * to level. It is not technically right for MSIs but this
484 * is irrelevant at this point. We might get smarter in the future
486 *out_hwirq = intspec[0];
487 *out_flags = IRQ_TYPE_LEVEL_LOW;
492 static struct irq_host_ops xics_host_ops = {
493 .match = xics_host_match,
494 .map = xics_host_map,
495 .xlate = xics_host_xlate,
498 static void __init xics_init_host(void)
500 if (firmware_has_feature(FW_FEATURE_LPAR))
501 xics_irq_chip = &xics_pic_lpar;
503 xics_irq_chip = &xics_pic_direct;
505 xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
507 BUG_ON(xics_host == NULL);
508 irq_set_default_host(xics_host);
512 /* Inter-processor interrupt support */
516 * XICS only has a single IPI, so encode the messages per CPU
518 static DEFINE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
520 static inline void smp_xics_do_message(int cpu, int msg)
522 unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
526 if (firmware_has_feature(FW_FEATURE_LPAR))
527 lpar_qirr_info(cpu, IPI_PRIORITY);
529 direct_qirr_info(cpu, IPI_PRIORITY);
532 void smp_xics_message_pass(int target, int msg)
536 if (target < NR_CPUS) {
537 smp_xics_do_message(target, msg);
539 for_each_online_cpu(i) {
540 if (target == MSG_ALL_BUT_SELF
541 && i == smp_processor_id())
543 smp_xics_do_message(i, msg);
548 static irqreturn_t xics_ipi_dispatch(int cpu)
550 unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
552 mb(); /* order mmio clearing qirr */
554 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) {
555 smp_message_recv(PPC_MSG_CALL_FUNCTION);
557 if (test_and_clear_bit(PPC_MSG_RESCHEDULE, tgt)) {
558 smp_message_recv(PPC_MSG_RESCHEDULE);
560 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, tgt)) {
561 smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
563 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
564 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, tgt)) {
565 smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
572 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
574 int cpu = smp_processor_id();
576 direct_qirr_info(cpu, 0xff);
578 return xics_ipi_dispatch(cpu);
581 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
583 int cpu = smp_processor_id();
585 lpar_qirr_info(cpu, 0xff);
587 return xics_ipi_dispatch(cpu);
590 static void xics_request_ipi(void)
595 ipi = irq_create_mapping(xics_host, XICS_IPI);
596 BUG_ON(ipi == NO_IRQ);
599 * IPIs are marked IRQF_DISABLED as they must run with irqs
602 set_irq_handler(ipi, handle_percpu_irq);
603 if (firmware_has_feature(FW_FEATURE_LPAR))
604 rc = request_irq(ipi, xics_ipi_action_lpar,
605 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
607 rc = request_irq(ipi, xics_ipi_action_direct,
608 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
612 int __init smp_xics_probe(void)
616 return cpumask_weight(cpu_possible_mask);
619 #endif /* CONFIG_SMP */
624 static void xics_update_irq_servers(void)
627 struct device_node *np;
632 /* Find the server numbers for the boot cpu. */
633 np = of_get_cpu_node(boot_cpuid, NULL);
636 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
642 i = ilen / sizeof(int);
643 hcpuid = get_hard_smp_processor_id(boot_cpuid);
645 /* Global interrupt distribution server is specified in the last
646 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
647 * entry fom this property for current boot cpu id and use it as
648 * default distribution server
650 for (j = 0; j < i; j += 2) {
651 if (ireg[j] == hcpuid) {
652 default_server = hcpuid;
653 default_distrib_server = ireg[j+1];
660 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
665 /* This may look gross but it's good enough for now, we don't quite
666 * have a hard -> linux processor id matching.
668 for_each_possible_cpu(i) {
671 if (hw_id == get_hard_smp_processor_id(i)) {
672 xics_per_cpu[i] = ioremap(addr, size);
678 static void __init xics_init_one_node(struct device_node *np,
684 /* This code does the theorically broken assumption that the interrupt
685 * server numbers are the same as the hard CPU numbers.
686 * This happens to be the case so far but we are playing with fire...
687 * should be fixed one of these days. -BenH.
689 ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
691 /* Do that ever happen ? we'll know soon enough... but even good'old
692 * f80 does have that property ..
694 WARN_ON(ireg == NULL);
697 * set node starting index for this node
701 ireg = of_get_property(np, "reg", &ilen);
703 panic("xics_init_IRQ: can't find interrupt reg property");
705 while (ilen >= (4 * sizeof(u32))) {
706 unsigned long addr, size;
708 /* XXX Use proper OF parsing code here !!! */
709 addr = (unsigned long)*ireg++ << 32;
713 size = (unsigned long)*ireg++ << 32;
717 xics_map_one_cpu(*indx, addr, size);
722 void __init xics_init_IRQ(void)
724 struct device_node *np;
729 ppc64_boot_msg(0x20, "XICS Init");
731 ibm_get_xive = rtas_token("ibm,get-xive");
732 ibm_set_xive = rtas_token("ibm,set-xive");
733 ibm_int_on = rtas_token("ibm,int-on");
734 ibm_int_off = rtas_token("ibm,int-off");
736 for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
738 if (firmware_has_feature(FW_FEATURE_LPAR)) {
742 xics_init_one_node(np, &indx);
747 /* get the bit size of server numbers */
750 for_each_compatible_node(np, NULL, "ibm,ppc-xics") {
751 isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
757 interrupt_server_size = *isize;
759 } else if (*isize != interrupt_server_size) {
760 printk(KERN_WARNING "XICS: "
761 "mismatched ibm,interrupt-server#-size\n");
762 interrupt_server_size = max(*isize,
763 interrupt_server_size);
767 xics_update_irq_servers();
770 if (firmware_has_feature(FW_FEATURE_LPAR))
771 ppc_md.get_irq = xics_get_irq_lpar;
773 ppc_md.get_irq = xics_get_irq_direct;
777 ppc64_boot_msg(0x21, "XICS Done");
780 /* Cpu startup, shutdown, and hotplug */
782 static void xics_set_cpu_priority(unsigned char cppr)
784 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
787 * we only really want to set the priority when there's
788 * just one cppr value on the stack
790 WARN_ON(os_cppr->index != 0);
792 os_cppr->stack[0] = cppr;
794 if (firmware_has_feature(FW_FEATURE_LPAR))
795 lpar_cppr_info(cppr);
797 direct_cppr_info(cppr);
801 /* Have the calling processor join or leave the specified global queue */
802 static void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
807 if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
810 index = (1UL << interrupt_server_size) - 1 - gserver;
812 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
814 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
815 GLOBAL_INTERRUPT_QUEUE, index, join, status);
818 void xics_setup_cpu(void)
820 xics_set_cpu_priority(LOWEST_PRIORITY);
822 xics_set_cpu_giq(default_distrib_server, 1);
825 void xics_teardown_cpu(void)
827 struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
828 int cpu = smp_processor_id();
831 * we have to reset the cppr index to 0 because we're
832 * not going to return from the IPI
835 xics_set_cpu_priority(0);
837 /* Clear any pending IPI request */
838 if (firmware_has_feature(FW_FEATURE_LPAR))
839 lpar_qirr_info(cpu, 0xff);
841 direct_qirr_info(cpu, 0xff);
844 void xics_kexec_teardown_cpu(int secondary)
849 * we take the ipi irq but and never return so we
850 * need to EOI the IPI, but want to leave our priority 0
852 * should we check all the other interrupts too?
853 * should we be flagging idle loop instead?
854 * or creating some task to be scheduled?
857 if (firmware_has_feature(FW_FEATURE_LPAR))
858 lpar_xirr_info_set((0x00 << 24) | XICS_IPI);
860 direct_xirr_info_set((0x00 << 24) | XICS_IPI);
863 * Some machines need to have at least one cpu in the GIQ,
864 * so leave the master cpu in the group.
867 xics_set_cpu_giq(default_distrib_server, 0);
870 #ifdef CONFIG_HOTPLUG_CPU
872 /* Interrupts are disabled. */
873 void xics_migrate_irqs_away(void)
875 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
876 unsigned int irq, virq;
878 /* If we used to be the default server, move to the new "boot_cpuid" */
879 if (hw_cpu == default_server)
880 xics_update_irq_servers();
882 /* Reject any interrupt that was queued to us... */
883 xics_set_cpu_priority(0);
885 /* Remove ourselves from the global interrupt queue */
886 xics_set_cpu_giq(default_distrib_server, 0);
888 /* Allow IPIs again... */
889 xics_set_cpu_priority(DEFAULT_PRIORITY);
892 struct irq_desc *desc;
897 /* We cant set affinity on ISA interrupts */
898 if (virq < NUM_ISA_INTERRUPTS)
900 if (irq_map[virq].host != xics_host)
902 irq = (unsigned int)irq_map[virq].hwirq;
903 /* We need to get IPIs still. */
904 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
906 desc = irq_to_desc(virq);
908 /* We only need to migrate enabled IRQS */
909 if (desc == NULL || desc->chip == NULL
910 || desc->action == NULL
911 || desc->chip->set_affinity == NULL)
914 raw_spin_lock_irqsave(&desc->lock, flags);
916 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
918 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
919 __func__, irq, status);
924 * We only support delivery to all cpus or to one cpu.
925 * The irq has to be migrated only in the single cpu
928 if (xics_status[0] != hw_cpu)
931 /* This is expected during cpu offline. */
933 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
936 /* Reset affinity to all cpus */
937 cpumask_setall(irq_to_desc(virq)->affinity);
938 desc->chip->set_affinity(virq, cpu_all_mask);
940 raw_spin_unlock_irqrestore(&desc->lock, flags);