arch/powerpc/platforms/powernv/pci.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Currently supports only P5IOC2
   5  *
   6  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17 #include <linux/string.h>
  18 #include <linux/init.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/msi.h>
  23
  24 #include <asm/sections.h>
  25 #include <asm/io.h>
  26 #include <asm/prom.h>
  27 #include <asm/pci-bridge.h>
  28 #include <asm/machdep.h>
  29 #include <asm/msi_bitmap.h>
  30 #include <asm/ppc-pci.h>
  31 #include <asm/opal.h>
  32 #include <asm/iommu.h>
  33 #include <asm/tce.h>
  34 #include <asm/firmware.h>
  35
  36 #include "powernv.h"
  37 #include "pci.h"
  38
  39 /* Delay in usec */
  40 #define PCI_RESET_DELAY_US      3000000
  41
  42 #define cfg_dbg(fmt...) do { } while(0)
  43 //#define cfg_dbg(fmt...)       printk(fmt)
  44
  45 #ifdef CONFIG_PCI_MSI
  46 static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
  47 {
  48         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  49         struct pnv_phb *phb = hose->private_data;
  50
  51         return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
  52 }
  53
  54 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  55 {
  56         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  57         struct pnv_phb *phb = hose->private_data;
  58         struct msi_desc *entry;
  59         struct msi_msg msg;
  60         int hwirq;
  61         unsigned int virq;
  62         int rc;
  63
  64         if (WARN_ON(!phb))
  65                 return -ENODEV;
  66
  67         list_for_each_entry(entry, &pdev->msi_list, list) {
  68                 if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
  69                         pr_warn("%s: Supports only 64-bit MSIs\n",
  70                                 pci_name(pdev));
  71                         return -ENXIO;
  72                 }
  73                 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
  74                 if (hwirq < 0) {
  75                         pr_warn("%s: Failed to find a free MSI\n",
  76                                 pci_name(pdev));
  77                         return -ENOSPC;
  78                 }
  79                 virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
  80                 if (virq == NO_IRQ) {
  81                         pr_warn("%s: Failed to map MSI to linux irq\n",
  82                                 pci_name(pdev));
  83                         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
  84                         return -ENOMEM;
  85                 }
  86                 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
  87                                     virq, entry->msi_attrib.is_64, &msg);
  88                 if (rc) {
  89                         pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
  90                         irq_dispose_mapping(virq);
  91                         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
  92                         return rc;
  93                 }
  94                 irq_set_msi_desc(virq, entry);
  95                 write_msi_msg(virq, &msg);
  96         }
  97         return 0;
  98 }
  99
 100 static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
 101 {
 102         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 103         struct pnv_phb *phb = hose->private_data;
 104         struct msi_desc *entry;
 105
 106         if (WARN_ON(!phb))
 107                 return;
 108
 109         list_for_each_entry(entry, &pdev->msi_list, list) {
 110                 if (entry->irq == NO_IRQ)
 111                         continue;
 112                 irq_set_msi_desc(entry->irq, NULL);
 113                 msi_bitmap_free_hwirqs(&phb->msi_bmp,
 114                         virq_to_hw(entry->irq) - phb->msi_base, 1);
 115                 irq_dispose_mapping(entry->irq);
 116         }
 117 }
 118 #endif /* CONFIG_PCI_MSI */
 119
 120 static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
 121 {
 122         struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
 123         int i;
 124
 125         pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
 126
 127         pr_info("  brdgCtl              = 0x%08x\n", data->brdgCtl);
 128
 129         pr_info("  portStatusReg        = 0x%08x\n", data->portStatusReg);
 130         pr_info("  rootCmplxStatus      = 0x%08x\n", data->rootCmplxStatus);
 131         pr_info("  busAgentStatus       = 0x%08x\n", data->busAgentStatus);
 132
 133         pr_info("  deviceStatus         = 0x%08x\n", data->deviceStatus);
 134         pr_info("  slotStatus           = 0x%08x\n", data->slotStatus);
 135         pr_info("  linkStatus           = 0x%08x\n", data->linkStatus);
 136         pr_info("  devCmdStatus         = 0x%08x\n", data->devCmdStatus);
 137         pr_info("  devSecStatus         = 0x%08x\n", data->devSecStatus);
 138
 139         pr_info("  rootErrorStatus      = 0x%08x\n", data->rootErrorStatus);
 140         pr_info("  uncorrErrorStatus    = 0x%08x\n", data->uncorrErrorStatus);
 141         pr_info("  corrErrorStatus      = 0x%08x\n", data->corrErrorStatus);
 142         pr_info("  tlpHdr1              = 0x%08x\n", data->tlpHdr1);
 143         pr_info("  tlpHdr2              = 0x%08x\n", data->tlpHdr2);
 144         pr_info("  tlpHdr3              = 0x%08x\n", data->tlpHdr3);
 145         pr_info("  tlpHdr4              = 0x%08x\n", data->tlpHdr4);
 146         pr_info("  sourceId             = 0x%08x\n", data->sourceId);
 147
 148         pr_info("  errorClass           = 0x%016llx\n", data->errorClass);
 149         pr_info("  correlator           = 0x%016llx\n", data->correlator);
 150
 151         pr_info("  p7iocPlssr           = 0x%016llx\n", data->p7iocPlssr);
 152         pr_info("  p7iocCsr             = 0x%016llx\n", data->p7iocCsr);
 153         pr_info("  lemFir               = 0x%016llx\n", data->lemFir);
 154         pr_info("  lemErrorMask         = 0x%016llx\n", data->lemErrorMask);
 155         pr_info("  lemWOF               = 0x%016llx\n", data->lemWOF);
 156         pr_info("  phbErrorStatus       = 0x%016llx\n", data->phbErrorStatus);
 157         pr_info("  phbFirstErrorStatus  = 0x%016llx\n", data->phbFirstErrorStatus);
 158         pr_info("  phbErrorLog0         = 0x%016llx\n", data->phbErrorLog0);
 159         pr_info("  phbErrorLog1         = 0x%016llx\n", data->phbErrorLog1);
 160         pr_info("  mmioErrorStatus      = 0x%016llx\n", data->mmioErrorStatus);
 161         pr_info("  mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
 162         pr_info("  mmioErrorLog0        = 0x%016llx\n", data->mmioErrorLog0);
 163         pr_info("  mmioErrorLog1        = 0x%016llx\n", data->mmioErrorLog1);
 164         pr_info("  dma0ErrorStatus      = 0x%016llx\n", data->dma0ErrorStatus);
 165         pr_info("  dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
 166         pr_info("  dma0ErrorLog0        = 0x%016llx\n", data->dma0ErrorLog0);
 167         pr_info("  dma0ErrorLog1        = 0x%016llx\n", data->dma0ErrorLog1);
 168         pr_info("  dma1ErrorStatus      = 0x%016llx\n", data->dma1ErrorStatus);
 169         pr_info("  dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
 170         pr_info("  dma1ErrorLog0        = 0x%016llx\n", data->dma1ErrorLog0);
 171         pr_info("  dma1ErrorLog1        = 0x%016llx\n", data->dma1ErrorLog1);
 172
 173         for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
 174                 if ((data->pestA[i] >> 63) == 0 &&
 175                     (data->pestB[i] >> 63) == 0)
 176                         continue;
 177                 pr_info("  PE[%3d] PESTA        = 0x%016llx\n", i, data->pestA[i]);
 178                 pr_info("          PESTB        = 0x%016llx\n", data->pestB[i]);
 179         }
 180 }
 181
 182 static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
 183 {
 184         switch(phb->model) {
 185         case PNV_PHB_MODEL_P7IOC:
 186                 pnv_pci_dump_p7ioc_diag_data(phb);
 187                 break;
 188         default:
 189                 pr_warning("PCI %d: Can't decode this PHB diag data\n",
 190                            phb->hose->global_number);
 191         }
 192 }
 193
 194 static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
 195 {
 196         unsigned long flags, rc;
 197         int has_diag;
 198
 199         spin_lock_irqsave(&phb->lock, flags);
 200
 201         rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
 202         has_diag = (rc == OPAL_SUCCESS);
 203
 204         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 205                                        OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 206         if (rc) {
 207                 pr_warning("PCI %d: Failed to clear EEH freeze state"
 208                            " for PE#%d, err %ld\n",
 209                            phb->hose->global_number, pe_no, rc);
 210
 211                 /* For now, let's only display the diag buffer when we fail to clear
 212                  * the EEH status. We'll do more sensible things later when we have
 213                  * proper EEH support. We need to make sure we don't pollute ourselves
 214                  * with the normal errors generated when probing empty slots
 215                  */
 216                 if (has_diag)
 217                         pnv_pci_dump_phb_diag_data(phb);
 218                 else
 219                         pr_warning("PCI %d: No diag data available\n",
 220                                    phb->hose->global_number);
 221         }
 222
 223         spin_unlock_irqrestore(&phb->lock, flags);
 224 }
 225
 226 static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
 227                                      u32 bdfn)
 228 {
 229         s64     rc;
 230         u8      fstate;
 231         u16     pcierr;
 232         u32     pe_no;
 233
 234         /* Get PE# if we support IODA */
 235         pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;
 236
 237         /* Read freeze status */
 238         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
 239                                         NULL);
 240         if (rc) {
 241                 pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
 242                            " err %lld\n", phb->hose->global_number, pe_no, rc);
 243                 return;
 244         }
 245         cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
 246                 bdfn, pe_no, fstate);
 247         if (fstate != 0)
 248                 pnv_pci_handle_eeh_config(phb, pe_no);
 249 }
 250
 251 static int pnv_pci_read_config(struct pci_bus *bus,
 252                                unsigned int devfn,
 253                                int where, int size, u32 *val)
 254 {
 255         struct pci_controller *hose = pci_bus_to_host(bus);
 256         struct pnv_phb *phb = hose->private_data;
 257         u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
 258         s64 rc;
 259
 260         if (hose == NULL)
 261                 return PCIBIOS_DEVICE_NOT_FOUND;
 262
 263         switch (size) {
 264         case 1: {
 265                 u8 v8;
 266                 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
 267                 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
 268                 break;
 269         }
 270         case 2: {
 271                 u16 v16;
 272                 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
 273                                                    &v16);
 274                 *val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
 275                 break;
 276         }
 277         case 4: {
 278                 u32 v32;
 279                 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
 280                 *val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
 281                 break;
 282         }
 283         default:
 284                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 285         }
 286         cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
 287                 bus->number, devfn, where, size, *val);
 288
 289         /* Check if the PHB got frozen due to an error (no response) */
 290         pnv_pci_config_check_eeh(phb, bus, bdfn);
 291
 292         return PCIBIOS_SUCCESSFUL;
 293 }
 294
 295 static int pnv_pci_write_config(struct pci_bus *bus,
 296                                 unsigned int devfn,
 297                                 int where, int size, u32 val)
 298 {
 299         struct pci_controller *hose = pci_bus_to_host(bus);
 300         struct pnv_phb *phb = hose->private_data;
 301         u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
 302
 303         if (hose == NULL)
 304                 return PCIBIOS_DEVICE_NOT_FOUND;
 305
 306         cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
 307                 bus->number, devfn, where, size, val);
 308         switch (size) {
 309         case 1:
 310                 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
 311                 break;
 312         case 2:
 313                 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
 314                 break;
 315         case 4:
 316                 opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
 317                 break;
 318         default:
 319                 return PCIBIOS_FUNC_NOT_SUPPORTED;
 320         }
 321         /* Check if the PHB got frozen due to an error (no response) */
 322         pnv_pci_config_check_eeh(phb, bus, bdfn);
 323
 324         return PCIBIOS_SUCCESSFUL;
 325 }
 326
 327 struct pci_ops pnv_pci_ops = {
 328         .read = pnv_pci_read_config,
 329         .write = pnv_pci_write_config,
 330 };
 331
 332 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
 333                          unsigned long uaddr, enum dma_data_direction direction,
 334                          struct dma_attrs *attrs)
 335 {
 336         u64 proto_tce;
 337         u64 *tcep, *tces;
 338         u64 rpn;
 339
 340         proto_tce = TCE_PCI_READ; // Read allowed
 341
 342         if (direction != DMA_TO_DEVICE)
 343                 proto_tce |= TCE_PCI_WRITE;
 344
 345         tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
 346         rpn = __pa(uaddr) >> TCE_SHIFT;
 347
 348         while (npages--)
 349                 *(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
 350
 351         /* Some implementations won't cache invalid TCEs and thus may not
 352          * need that flush. We'll probably turn it_type into a bit mask
 353          * of flags if that becomes the case
 354          */
 355         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
 356                 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
 357
 358         return 0;
 359 }
 360
 361 static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
 362 {
 363         u64 *tcep, *tces;
 364
 365         tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
 366
 367         while (npages--)
 368                 *(tcep++) = 0;
 369
 370         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
 371                 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
 372 }
 373
 374 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
 375 {
 376         return ((u64 *)tbl->it_base)[index - tbl->it_offset];
 377 }
 378
 379 void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
 380                                void *tce_mem, u64 tce_size,
 381                                u64 dma_offset)
 382 {
 383         tbl->it_blocksize = 16;
 384         tbl->it_base = (unsigned long)tce_mem;
 385         tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
 386         tbl->it_index = 0;
 387         tbl->it_size = tce_size >> 3;
 388         tbl->it_busno = 0;
 389         tbl->it_type = TCE_PCI;
 390 }
 391
 392 static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
 393 {
 394         struct iommu_table *tbl;
 395         const __be64 *basep, *swinvp;
 396         const __be32 *sizep;
 397
 398         basep = of_get_property(hose->dn, "linux,tce-base", NULL);
 399         sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
 400         if (basep == NULL || sizep == NULL) {
 401                 pr_err("PCI: %s has missing tce entries !\n",
 402                        hose->dn->full_name);
 403                 return NULL;
 404         }
 405         tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
 406         if (WARN_ON(!tbl))
 407                 return NULL;
 408         pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
 409                                   be32_to_cpup(sizep), 0);
 410         iommu_init_table(tbl, hose->node);
 411
 412         /* Deal with SW invalidated TCEs when needed (BML way) */
 413         swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
 414                                  NULL);
 415         if (swinvp) {
 416                 tbl->it_busno = swinvp[1];
 417                 tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
 418                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 419         }
 420         return tbl;
 421 }
 422
 423 static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
 424                                        struct pci_dev *pdev)
 425 {
 426         struct device_node *np = pci_bus_to_OF_node(hose->bus);
 427         struct pci_dn *pdn;
 428
 429         if (np == NULL)
 430                 return;
 431         pdn = PCI_DN(np);
 432         if (!pdn->iommu_table)
 433                 pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
 434         if (!pdn->iommu_table)
 435                 return;
 436         set_iommu_table_base(&pdev->dev, pdn->iommu_table);
 437 }
 438
 439 static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
 440 {
 441         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 442         struct pnv_phb *phb = hose->private_data;
 443
 444         /* If we have no phb structure, try to setup a fallback based on
 445          * the device-tree (RTAS PCI for example)
 446          */
 447         if (phb && phb->dma_dev_setup)
 448                 phb->dma_dev_setup(phb, pdev);
 449         else
 450                 pnv_pci_dma_fallback_setup(hose, pdev);
 451 }
 452
 453 /* Fixup wrong class code in p7ioc and p8 root complex */
 454 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
 455 {
 456         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 457 }
 458 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
 459
 460 static int pnv_pci_probe_mode(struct pci_bus *bus)
 461 {
 462         struct pci_controller *hose = pci_bus_to_host(bus);
 463         const __be64 *tstamp;
 464         u64 now, target;
 465
 466
 467         /* We hijack this as a way to ensure we have waited long
 468          * enough since the reset was lifted on the PCI bus
 469          */
 470         if (bus != hose->bus)
 471                 return PCI_PROBE_NORMAL;
 472         tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
 473         if (!tstamp || !*tstamp)
 474                 return PCI_PROBE_NORMAL;
 475
 476         now = mftb() / tb_ticks_per_usec;
 477         target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
 478                 + PCI_RESET_DELAY_US;
 479
 480         pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
 481                  hose->global_number, target, now);
 482
 483         if (now < target)
 484                 msleep((target - now + 999) / 1000);
 485
 486         return PCI_PROBE_NORMAL;
 487 }
 488
 489 void __init pnv_pci_init(void)
 490 {
 491         struct device_node *np;
 492
 493         pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
 494
 495         /* OPAL absent, try POPAL first then RTAS detection of PHBs */
 496         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
 497 #ifdef CONFIG_PPC_POWERNV_RTAS
 498                 init_pci_config_tokens();
 499                 find_and_init_phbs();
 500 #endif /* CONFIG_PPC_POWERNV_RTAS */
 501         }
 502         /* OPAL is here, do our normal stuff */
 503         else {
 504                 int found_ioda = 0;
 505
 506                 /* Look for IODA IO-Hubs. We don't support mixing IODA
 507                  * and p5ioc2 due to the need to change some global
 508                  * probing flags
 509                  */
 510                 for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
 511                         pnv_pci_init_ioda_hub(np);
 512                         found_ioda = 1;
 513                 }
 514
 515                 /* Look for p5ioc2 IO-Hubs */
 516                 if (!found_ioda)
 517                         for_each_compatible_node(np, NULL, "ibm,p5ioc2")
 518                                 pnv_pci_init_p5ioc2_hub(np);
 519
 520                 /* Look for ioda2 built-in PHB3's */
 521                 for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
 522                         pnv_pci_init_ioda2_phb(np);
 523         }
 524
 525         /* Setup the linkage between OF nodes and PHBs */
 526         pci_devs_phb_init();
 527
 528         /* Configure IOMMU DMA hooks */
 529         ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
 530         ppc_md.tce_build = pnv_tce_build;
 531         ppc_md.tce_free = pnv_tce_free;
 532         ppc_md.tce_get = pnv_tce_get;
 533         ppc_md.pci_probe_mode = pnv_pci_probe_mode;
 534         set_pci_dma_ops(&dma_iommu_ops);
 535
 536         /* Configure MSIs */
 537 #ifdef CONFIG_PCI_MSI
 538         ppc_md.msi_check_device = pnv_msi_check_device;
 539         ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
 540         ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
 541 #endif
 542 }