1 // SPDX-License-Identifier: GPL-2.0-or-later
3 #include <linux/kernel.h>
4 #include <linux/ioport.h>
5 #include <linux/bitmap.h>
13 * The majority of the complexity in supporting SR-IOV on PowerNV comes from
14 * the need to put the MMIO space for each VF into a separate PE. Internally
15 * the PHB maps MMIO addresses to a specific PE using the "Memory BAR Table".
16 * The MBT historically only applied to the 64bit MMIO window of the PHB
17 * so it's common to see it referred to as the "M64BT".
19 * An MBT entry stores the mapped range as an <base>,<mask> pair. This forces
20 * the address range that we want to map to be power-of-two sized and aligned.
21 * For conventional PCI devices this isn't really an issue since PCI device BARs
22 * have the same requirement.
24 * For a SR-IOV BAR things are a little more awkward since size and alignment
25 * are not coupled. The alignment is set based on the the per-VF BAR size, but
26 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs
27 * isn't necessarily a power of two, so neither is the total size. To fix that
28 * we need to finesse (read: hack) the Linux BAR allocator so that it will
29 * allocate the SR-IOV BARs in a way that lets us map them using the MBT.
31 * The changes to size and alignment that we need to do depend on the "mode"
32 * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above,
33 * so as a baseline we can assume that we have the following BAR modes
36 * NB: $PE_COUNT is the number of PEs that the PHB supports.
38 * a) A segmented BAR that splits the mapped range into $PE_COUNT equally sized
39 * segments. The n'th segment is mapped to the n'th PE.
40 * b) An un-segmented BAR that maps the whole address range to a specific PE.
43 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR
44 * For comparison b) requires one entry per-VF per-BAR, or:
45 * (num-vfs * num-sriov-bars) in total. To use a) we need the size of each segment
46 * to equal the size of the per-VF BAR area. So:
48 * new_size = per-vf-size * number-of-PEs
50 * The alignment for the SR-IOV BAR also needs to be changed from per-vf-size
51 * to "new_size", calculated above. Implementing this is a convoluted process
52 * which requires several hooks in the PCI core:
54 * 1. In pcibios_device_add() we call pnv_pci_ioda_fixup_iov().
56 * At this point the device has been probed and the device's BARs are sized,
57 * but no resource allocations have been done. The SR-IOV BARs are sized
58 * based on the maximum number of VFs supported by the device and we need
59 * to increase that to new_size.
61 * 2. Later, when Linux actually assigns resources it tries to make the resource
62 * allocations for each PCI bus as compact as possible. As a part of that it
63 * sorts the BARs on a bus by their required alignment, which is calculated
64 * using pci_resource_alignment().
66 * For IOV resources this goes:
67 * pci_resource_alignment()
68 * pci_sriov_resource_alignment()
69 * pcibios_sriov_resource_alignment()
70 * pnv_pci_iov_resource_alignment()
72 * Our hook overrides the default alignment, equal to the per-vf-size, with
73 * new_size computed above.
75 * 3. When userspace enables VFs for a device:
78 * pcibios_sriov_enable()
79 * pnv_pcibios_sriov_enable()
81 * This is where we actually allocate PE numbers for each VF and setup the
82 * MBT mapping for each SR-IOV BAR. In steps 1) and 2) we setup an "arena"
83 * where each MBT segment is equal in size to the VF BAR so we can shift
84 * around the actual SR-IOV BAR location within this arena. We need this
85 * ability because the PE space is shared by all devices on the same PHB.
86 * When using mode a) described above segment 0 in maps to PE#0 which might
87 * be already being used by another device on the PHB.
89 * As a result we need allocate a contigious range of PE numbers, then shift
90 * the address programmed into the SR-IOV BAR of the PF so that the address
91 * of VF0 matches up with the segment corresponding to the first allocated
92 * PE number. This is handled in pnv_pci_vf_resource_shift().
94 * Once all that is done we return to the PCI core which then enables VFs,
95 * scans them and creates pci_devs for each. The init process for a VF is
96 * largely the same as a normal device, but the VF is inserted into the IODA
97 * PE that we allocated for it rather than the PE associated with the bus.
99 * 4. When userspace disables VFs we unwind the above in
100 * pnv_pcibios_sriov_disable(). Fortunately this is relatively simple since
101 * we don't need to validate anything, just tear down the mappings and
102 * move SR-IOV resource back to its "proper" location.
104 * That's how mode a) works. In theory mode b) (single PE mapping) is less work
105 * since we can map each individual VF with a separate BAR. However, there's a
108 * 1) For IODA2 mode b) has a minimum alignment requirement of 32MB. This makes
109 * it only usable for devices with very large per-VF BARs. Such devices are
110 * similar to Big Foot. They definitely exist, but I've never seen one.
112 * 2) The number of MBT entries that we have is limited. PHB3 and PHB4 only
113 * 16 total and some are needed for. Most SR-IOV capable network cards can support
114 * more than 16 VFs on each port.
116 * We use b) when using a) would use more than 1/4 of the entire 64 bit MMIO
121 * PHB4 (IODA3) added a few new features that would be useful for SR-IOV. It
122 * allowed the MBT to map 32bit MMIO space in addition to 64bit which allows
123 * us to support SR-IOV BARs in the 32bit MMIO window. This is useful since
124 * the Linux BAR allocation will place any BAR marked as non-prefetchable into
125 * the non-prefetchable bridge window, which is 32bit only. It also added two
128 * c) A segmented BAR similar to a), but each segment can be individually
129 * mapped to any PE. This is matches how the 32bit MMIO window worked on
132 * d) A segmented BAR with 8, 64, or 128 segments. This works similarly to a),
133 * but with fewer segments and configurable base PE.
135 * i.e. The n'th segment maps to the (n + base)'th PE.
137 * The base PE is also required to be a multiple of the window size.
139 * Unfortunately, the OPAL API doesn't currently (as of skiboot v6.6) allow us
140 * to exploit any of the IODA3 features.
143 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
145 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
146 struct resource *res;
148 resource_size_t vf_bar_sz;
149 struct pnv_iov_data *iov;
152 iov = kzalloc(sizeof(*iov), GFP_KERNEL);
155 pdev->dev.archdata.iov_data = iov;
156 mul = phb->ioda.total_pe_num;
158 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
159 res = &pdev->resource[i + PCI_IOV_RESOURCES];
160 if (!res->flags || res->parent)
162 if (!pnv_pci_is_m64_flags(res->flags)) {
163 dev_warn(&pdev->dev, "Don't support SR-IOV with non M64 VF BAR%d: %pR. \n",
168 vf_bar_sz = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
171 * Generally, one segmented M64 BAR maps one IOV BAR. However,
172 * if a VF BAR is too large we end up wasting a lot of space.
173 * If each VF needs more than 1/4 of the default m64 segment
174 * then each VF BAR should be mapped in single-PE mode to reduce
175 * the amount of space required. This does however limit the
176 * number of VFs we can support.
178 * The 1/4 limit is arbitrary and can be tweaked.
180 if (vf_bar_sz > (phb->ioda.m64_segsize >> 2)) {
182 * On PHB3, the minimum size alignment of M64 BAR in
183 * single mode is 32MB. If this VF BAR is smaller than
184 * 32MB, but still too large for a segmented window
185 * then we can't map it and need to disable SR-IOV for
188 if (vf_bar_sz < SZ_32M) {
189 pci_err(pdev, "VF BAR%d: %pR can't be mapped in single PE mode\n",
194 iov->m64_single_mode[i] = true;
199 * This BAR can be mapped with one segmented window, so adjust
200 * te resource size to accommodate.
202 pci_dbg(pdev, " Fixing VF BAR%d: %pR to\n", i, res);
203 res->end = res->start + vf_bar_sz * mul - 1;
204 pci_dbg(pdev, " %pR\n", res);
206 pci_info(pdev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
209 iov->need_shift = true;
215 /* Save ourselves some MMIO space by disabling the unusable BARs */
216 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
217 res = &pdev->resource[i + PCI_IOV_RESOURCES];
219 res->end = res->start - 1;
222 pdev->dev.archdata.iov_data = NULL;
226 void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
228 if (pdev->is_virtfn) {
229 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
232 * VF PEs are single-device PEs so their pdev pointer needs to
233 * be set. The pdev doesn't exist when the PE is allocated (in
234 * (pcibios_sriov_enable()) so we fix it up here.
237 WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
238 } else if (pdev->is_physfn) {
240 * For PFs adjust their allocated IOV resources to match what
241 * the PHB can support using it's M64 BAR table.
243 pnv_pci_ioda_fixup_iov_resources(pdev);
247 resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
250 resource_size_t align = pci_iov_resource_size(pdev, resno);
251 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
252 struct pnv_iov_data *iov = pnv_iov_get(pdev);
255 * iov can be null if we have an SR-IOV device with IOV BAR that can't
256 * be placed in the m64 space (i.e. The BAR is 32bit or non-prefetch).
257 * In that case we don't allow VFs to be enabled since one of their
258 * BARs would not be placed in the correct PE.
264 * If we're using single mode then we can just use the native VF BAR
265 * alignment. We validated that it's possible to use a single PE
266 * window above when we did the fixup.
268 if (iov->m64_single_mode[resno - PCI_IOV_RESOURCES])
272 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
273 * SR-IOV. While from hardware perspective, the range mapped by M64
274 * BAR should be size aligned.
276 * This function returns the total IOV BAR size if M64 BAR is in
277 * Shared PE mode or just VF BAR size if not.
278 * If the M64 BAR is in Single PE mode, return the VF BAR size or
279 * M64 segment size if IOV BAR size is less.
281 return phb->ioda.total_pe_num * align;
284 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
286 struct pnv_iov_data *iov;
290 phb = pci_bus_to_pnvhb(pdev->bus);
291 iov = pnv_iov_get(pdev);
293 for_each_set_bit(window_id, iov->used_m64_bar_mask, MAX_M64_BARS) {
294 opal_pci_phb_mmio_enable(phb->opal_id,
295 OPAL_M64_WINDOW_TYPE,
299 clear_bit(window_id, &phb->ioda.m64_bar_alloc);
307 * PHB3 and beyond support segmented windows. The window's address range
308 * is subdivided into phb->ioda.total_pe_num segments and there's a 1-1
309 * mapping between PEs and segments.
311 static int64_t pnv_ioda_map_m64_segmented(struct pnv_phb *phb,
313 resource_size_t start,
314 resource_size_t size)
318 rc = opal_pci_set_phb_mem_window(phb->opal_id,
319 OPAL_M64_WINDOW_TYPE,
327 rc = opal_pci_phb_mmio_enable(phb->opal_id,
328 OPAL_M64_WINDOW_TYPE,
330 OPAL_ENABLE_M64_SPLIT);
333 pr_err("Failed to map M64 window #%d: %lld\n", window_id, rc);
338 static int64_t pnv_ioda_map_m64_single(struct pnv_phb *phb,
341 resource_size_t start,
342 resource_size_t size)
347 * The API for setting up m64 mmio windows seems to have been designed
348 * with P7-IOC in mind. For that chip each M64 BAR (window) had a fixed
349 * split of 8 equally sized segments each of which could individually
352 * The problem with this is that the API doesn't have any way to
353 * communicate the number of segments we want on a BAR. This wasn't
354 * a problem for p7-ioc since you didn't have a choice, but the
355 * single PE windows added in PHB3 don't map cleanly to this API.
357 * As a result we've got this slightly awkward process where we
358 * call opal_pci_map_pe_mmio_window() to put the single in single
359 * PE mode, and set the PE for the window before setting the address
360 * bounds. We need to do it this way because the single PE windows
361 * for PHB3 have different alignment requirements on PHB3.
363 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
365 OPAL_M64_WINDOW_TYPE,
372 * NB: In single PE mode the window needs to be aligned to 32MB
374 rc = opal_pci_set_phb_mem_window(phb->opal_id,
375 OPAL_M64_WINDOW_TYPE,
378 0, /* ignored by FW, m64 is 1-1 */
384 * Now actually enable it. We specified the BAR should be in "non-split"
385 * mode so FW will validate that the BAR is in single PE mode.
387 rc = opal_pci_phb_mmio_enable(phb->opal_id,
388 OPAL_M64_WINDOW_TYPE,
390 OPAL_ENABLE_M64_NON_SPLIT);
393 pr_err("Error mapping single PE BAR\n");
398 static int pnv_pci_alloc_m64_bar(struct pnv_phb *phb, struct pnv_iov_data *iov)
403 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
404 phb->ioda.m64_bar_idx + 1, 0);
406 if (win >= phb->ioda.m64_bar_idx + 1)
408 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
410 set_bit(win, iov->used_m64_bar_mask);
415 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
417 struct pnv_iov_data *iov;
420 struct resource *res;
423 resource_size_t size, start;
426 phb = pci_bus_to_pnvhb(pdev->bus);
427 iov = pnv_iov_get(pdev);
429 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
430 res = &pdev->resource[i + PCI_IOV_RESOURCES];
431 if (!res->flags || !res->parent)
434 /* don't need single mode? map everything in one go! */
435 if (!iov->m64_single_mode[i]) {
436 win = pnv_pci_alloc_m64_bar(phb, iov);
440 size = resource_size(res);
443 rc = pnv_ioda_map_m64_segmented(phb, win, start, size);
450 /* otherwise map each VF with single PE BARs */
451 size = pci_iov_resource_size(pdev, PCI_IOV_RESOURCES + i);
452 base_pe_num = iov->vf_pe_arr[0].pe_number;
454 for (j = 0; j < num_vfs; j++) {
455 win = pnv_pci_alloc_m64_bar(phb, iov);
459 start = res->start + size * j;
460 rc = pnv_ioda_map_m64_single(phb, win,
471 pnv_pci_vf_release_m64(pdev, num_vfs);
475 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
478 struct pnv_ioda_pe *pe, *pe_n;
480 phb = pci_bus_to_pnvhb(pdev->bus);
482 if (!pdev->is_physfn)
485 /* FIXME: Use pnv_ioda_release_pe()? */
486 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
487 if (pe->parent_dev != pdev)
490 pnv_pci_ioda2_release_pe_dma(pe);
492 /* Remove from list */
493 mutex_lock(&phb->ioda.pe_list_mutex);
495 mutex_unlock(&phb->ioda.pe_list_mutex);
497 pnv_ioda_deconfigure_pe(phb, pe);
499 pnv_ioda_free_pe(pe);
503 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
505 struct resource *res, res2;
506 struct pnv_iov_data *iov;
507 resource_size_t size;
513 iov = pnv_iov_get(dev);
516 * "offset" is in VFs. The M64 windows are sized so that when they
517 * are segmented, each segment is the same size as the IOV BAR.
518 * Each segment is in a separate PE, and the high order bits of the
519 * address are the PE number. Therefore, each VF's BAR is in a
520 * separate PE, and changing the IOV BAR start address changes the
521 * range of PEs the VFs are in.
523 num_vfs = iov->num_vfs;
524 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
525 res = &dev->resource[i + PCI_IOV_RESOURCES];
526 if (!res->flags || !res->parent)
528 if (iov->m64_single_mode[i])
532 * The actual IOV BAR range is determined by the start address
533 * and the actual size for num_vfs VFs BAR. This check is to
534 * make sure that after shifting, the range will not overlap
535 * with another device.
537 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
538 res2.flags = res->flags;
539 res2.start = res->start + (size * offset);
540 res2.end = res2.start + (size * num_vfs) - 1;
542 if (res2.end > res->end) {
543 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
544 i, &res2, res, num_vfs, offset);
550 * Since M64 BAR shares segments among all possible 256 PEs,
551 * we have to shift the beginning of PF IOV BAR to make it start from
552 * the segment which belongs to the PE number assigned to the first VF.
553 * This creates a "hole" in the /proc/iomem which could be used for
554 * allocating other resources so we reserve this area below and
555 * release when IOV is released.
557 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
558 res = &dev->resource[i + PCI_IOV_RESOURCES];
559 if (!res->flags || !res->parent)
561 if (iov->m64_single_mode[i])
564 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
566 res->start += size * offset;
568 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
569 i, &res2, res, (offset > 0) ? "En" : "Dis",
573 devm_release_resource(&dev->dev, &iov->holes[i]);
574 memset(&iov->holes[i], 0, sizeof(iov->holes[i]));
577 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
580 iov->holes[i].start = res2.start;
581 iov->holes[i].end = res2.start + size * offset - 1;
582 iov->holes[i].flags = IORESOURCE_BUS;
583 iov->holes[i].name = "pnv_iov_reserved";
584 devm_request_resource(&dev->dev, res->parent,
591 static void pnv_pci_sriov_disable(struct pci_dev *pdev)
593 u16 num_vfs, base_pe;
594 struct pnv_iov_data *iov;
596 iov = pnv_iov_get(pdev);
597 num_vfs = iov->num_vfs;
598 base_pe = iov->vf_pe_arr[0].pe_number;
604 pnv_ioda_release_vf_PE(pdev);
606 /* Un-shift the IOV BARs if we need to */
608 pnv_pci_vf_resource_shift(pdev, -base_pe);
610 /* Release M64 windows */
611 pnv_pci_vf_release_m64(pdev, num_vfs);
614 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
617 struct pnv_ioda_pe *pe;
620 struct pnv_iov_data *iov;
623 if (!pdev->is_physfn)
626 phb = pci_bus_to_pnvhb(pdev->bus);
627 pdn = pci_get_pdn(pdev);
628 iov = pnv_iov_get(pdev);
630 /* Reserve PE for each VF */
631 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
632 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
633 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
634 struct pci_dn *vf_pdn;
636 pe = &iov->vf_pe_arr[vf_index];
638 pe->flags = PNV_IODA_PE_VF;
640 pe->parent_dev = pdev;
642 pe->rid = (vf_bus << 8) | vf_devfn;
644 pe_num = pe->pe_number;
645 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
646 pci_domain_nr(pdev->bus), pdev->bus->number,
647 PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
649 if (pnv_ioda_configure_pe(phb, pe)) {
650 /* XXX What do we do here ? */
651 pnv_ioda_free_pe(pe);
656 /* Put PE to the list */
657 mutex_lock(&phb->ioda.pe_list_mutex);
658 list_add_tail(&pe->list, &phb->ioda.pe_list);
659 mutex_unlock(&phb->ioda.pe_list_mutex);
661 /* associate this pe to it's pdn */
662 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
663 if (vf_pdn->busno == vf_bus &&
664 vf_pdn->devfn == vf_devfn) {
665 vf_pdn->pe_number = pe_num;
670 pnv_pci_ioda2_setup_dma_pe(phb, pe);
674 static int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
676 struct pnv_ioda_pe *base_pe;
677 struct pnv_iov_data *iov;
682 phb = pci_bus_to_pnvhb(pdev->bus);
683 iov = pnv_iov_get(pdev);
686 * There's a calls to IODA2 PE setup code littered throughout. We could
687 * probably fix that, but we'd still have problems due to the
688 * restriction inherent on IODA1 PHBs.
690 * NB: We class IODA3 as IODA2 since they're very similar.
692 if (phb->type != PNV_PHB_IODA2) {
693 pci_err(pdev, "SR-IOV is not supported on this PHB\n");
698 dev_info(&pdev->dev, "don't support this SRIOV device with non 64bit-prefetchable IOV BAR\n");
702 /* allocate a contigious block of PEs for our VFs */
703 base_pe = pnv_ioda_alloc_pe(phb, num_vfs);
705 pci_err(pdev, "Unable to allocate PEs for %d VFs\n", num_vfs);
709 iov->vf_pe_arr = base_pe;
710 iov->num_vfs = num_vfs;
712 /* Assign M64 window accordingly */
713 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
715 dev_info(&pdev->dev, "Not enough M64 window resources\n");
720 * When using one M64 BAR to map one IOV BAR, we need to shift
721 * the IOV BAR according to the PE# allocated to the VFs.
722 * Otherwise, the PE# for the VF will conflict with others.
724 if (iov->need_shift) {
725 ret = pnv_pci_vf_resource_shift(pdev, base_pe->pe_number);
731 pnv_ioda_setup_vf_PE(pdev, num_vfs);
736 pnv_pci_vf_release_m64(pdev, num_vfs);
739 for (i = 0; i < num_vfs; i++)
740 pnv_ioda_free_pe(&iov->vf_pe_arr[i]);
745 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
747 pnv_pci_sriov_disable(pdev);
749 /* Release PCI data */
750 remove_sriov_vf_pdns(pdev);
754 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
756 /* Allocate PCI data */
757 add_sriov_vf_pdns(pdev);
759 return pnv_pci_sriov_enable(pdev, num_vfs);