arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <linux/msi.h>
  24
  25 #include <asm/sections.h>
  26 #include <asm/io.h>
  27 #include <asm/prom.h>
  28 #include <asm/pci-bridge.h>
  29 #include <asm/machdep.h>
  30 #include <asm/msi_bitmap.h>
  31 #include <asm/ppc-pci.h>
  32 #include <asm/opal.h>
  33 #include <asm/iommu.h>
  34 #include <asm/tce.h>
  35 #include <asm/xics.h>
  36 #include <asm/debug.h>
  37
  38 #include "powernv.h"
  39 #include "pci.h"
  40
  41 #define define_pe_printk_level(func, kern_level)                \
  42 static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...)     \
  43 {                                                               \
  44         struct va_format vaf;                                   \
  45         va_list args;                                           \
  46         char pfix[32];                                          \
  47         int r;                                                  \
  48                                                                 \
  49         va_start(args, fmt);                                    \
  50                                                                 \
  51         vaf.fmt = fmt;                                          \
  52         vaf.va = &args;                                         \
  53                                                                 \
  54         if (pe->pdev)                                           \
  55                 strlcpy(pfix, dev_name(&pe->pdev->dev),         \
  56                         sizeof(pfix));                          \
  57         else                                                    \
  58                 sprintf(pfix, "%04x:%02x     ",                 \
  59                         pci_domain_nr(pe->pbus),                \
  60                         pe->pbus->number);                      \
  61         r = printk(kern_level "pci %s: [PE# %.3d] %pV",         \
  62                    pfix, pe->pe_number, &vaf);                  \
  63                                                                 \
  64         va_end(args);                                           \
  65                                                                 \
  66         return r;                                               \
  67 }                                                               \
  68
  69 define_pe_printk_level(pe_err, KERN_ERR);
  70 define_pe_printk_level(pe_warn, KERN_WARNING);
  71 define_pe_printk_level(pe_info, KERN_INFO);
  72
  73 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
  74 {
  75         unsigned long pe;
  76
  77         do {
  78                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
  79                                         phb->ioda.total_pe, 0);
  80                 if (pe >= phb->ioda.total_pe)
  81                         return IODA_INVALID_PE;
  82         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
  83
  84         phb->ioda.pe_array[pe].phb = phb;
  85         phb->ioda.pe_array[pe].pe_number = pe;
  86         return pe;
  87 }
  88
  89 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
  90 {
  91         WARN_ON(phb->ioda.pe_array[pe].pdev);
  92
  93         memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
  94         clear_bit(pe, phb->ioda.pe_alloc);
  95 }
  96
  97 /* Currently those 2 are only used when MSIs are enabled, this will change
  98  * but in the meantime, we need to protect them to avoid warnings
  99  */
 100 #ifdef CONFIG_PCI_MSI
 101 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 102 {
 103         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 104         struct pnv_phb *phb = hose->private_data;
 105         struct pci_dn *pdn = pci_get_pdn(dev);
 106
 107         if (!pdn)
 108                 return NULL;
 109         if (pdn->pe_number == IODA_INVALID_PE)
 110                 return NULL;
 111         return &phb->ioda.pe_array[pdn->pe_number];
 112 }
 113 #endif /* CONFIG_PCI_MSI */
 114
 115 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 116 {
 117         struct pci_dev *parent;
 118         uint8_t bcomp, dcomp, fcomp;
 119         long rc, rid_end, rid;
 120
 121         /* Bus validation ? */
 122         if (pe->pbus) {
 123                 int count;
 124
 125                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 126                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 127                 parent = pe->pbus->self;
 128                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 129                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 130                 else
 131                         count = 1;
 132
 133                 switch(count) {
 134                 case  1: bcomp = OpalPciBusAll;         break;
 135                 case  2: bcomp = OpalPciBus7Bits;       break;
 136                 case  4: bcomp = OpalPciBus6Bits;       break;
 137                 case  8: bcomp = OpalPciBus5Bits;       break;
 138                 case 16: bcomp = OpalPciBus4Bits;       break;
 139                 case 32: bcomp = OpalPciBus3Bits;       break;
 140                 default:
 141                         pr_err("%s: Number of subordinate busses %d"
 142                                " unsupported\n",
 143                                pci_name(pe->pbus->self), count);
 144                         /* Do an exact match only */
 145                         bcomp = OpalPciBusAll;
 146                 }
 147                 rid_end = pe->rid + (count << 8);
 148         } else {
 149                 parent = pe->pdev->bus->self;
 150                 bcomp = OpalPciBusAll;
 151                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 152                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 153                 rid_end = pe->rid + 1;
 154         }
 155
 156         /* Associate PE in PELT */
 157         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 158                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 159         if (rc) {
 160                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 161                 return -ENXIO;
 162         }
 163         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 164                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 165
 166         /* Add to all parents PELT-V */
 167         while (parent) {
 168                 struct pci_dn *pdn = pci_get_pdn(parent);
 169                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 170                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 171                                                 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
 172                         /* XXX What to do in case of error ? */
 173                 }
 174                 parent = parent->bus->self;
 175         }
 176         /* Setup reverse map */
 177         for (rid = pe->rid; rid < rid_end; rid++)
 178                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 179
 180         /* Setup one MVTs on IODA1 */
 181         if (phb->type == PNV_PHB_IODA1) {
 182                 pe->mve_number = pe->pe_number;
 183                 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number,
 184                                       pe->pe_number);
 185                 if (rc) {
 186                         pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 187                                rc, pe->mve_number);
 188                         pe->mve_number = -1;
 189                 } else {
 190                         rc = opal_pci_set_mve_enable(phb->opal_id,
 191                                                      pe->mve_number, OPAL_ENABLE_MVE);
 192                         if (rc) {
 193                                 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 194                                        rc, pe->mve_number);
 195                                 pe->mve_number = -1;
 196                         }
 197                 }
 198         } else if (phb->type == PNV_PHB_IODA2)
 199                 pe->mve_number = 0;
 200
 201         return 0;
 202 }
 203
 204 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 205                                        struct pnv_ioda_pe *pe)
 206 {
 207         struct pnv_ioda_pe *lpe;
 208
 209         list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
 210                 if (lpe->dma_weight < pe->dma_weight) {
 211                         list_add_tail(&pe->dma_link, &lpe->dma_link);
 212                         return;
 213                 }
 214         }
 215         list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 216 }
 217
 218 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
 219 {
 220         /* This is quite simplistic. The "base" weight of a device
 221          * is 10. 0 means no DMA is to be accounted for it.
 222          */
 223
 224         /* If it's a bridge, no DMA */
 225         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
 226                 return 0;
 227
 228         /* Reduce the weight of slow USB controllers */
 229         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
 230             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
 231             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
 232                 return 3;
 233
 234         /* Increase the weight of RAID (includes Obsidian) */
 235         if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
 236                 return 15;
 237
 238         /* Default */
 239         return 10;
 240 }
 241
 242 #if 0
 243 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 244 {
 245         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 246         struct pnv_phb *phb = hose->private_data;
 247         struct pci_dn *pdn = pci_get_pdn(dev);
 248         struct pnv_ioda_pe *pe;
 249         int pe_num;
 250
 251         if (!pdn) {
 252                 pr_err("%s: Device tree node not associated properly\n",
 253                            pci_name(dev));
 254                 return NULL;
 255         }
 256         if (pdn->pe_number != IODA_INVALID_PE)
 257                 return NULL;
 258
 259         /* PE#0 has been pre-set */
 260         if (dev->bus->number == 0)
 261                 pe_num = 0;
 262         else
 263                 pe_num = pnv_ioda_alloc_pe(phb);
 264         if (pe_num == IODA_INVALID_PE) {
 265                 pr_warning("%s: Not enough PE# available, disabling device\n",
 266                            pci_name(dev));
 267                 return NULL;
 268         }
 269
 270         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 271          * pointer in the PE data structure, both should be destroyed at the
 272          * same time. However, this needs to be looked at more closely again
 273          * once we actually start removing things (Hotplug, SR-IOV, ...)
 274          *
 275          * At some point we want to remove the PDN completely anyways
 276          */
 277         pe = &phb->ioda.pe_array[pe_num];
 278         pci_dev_get(dev);
 279         pdn->pcidev = dev;
 280         pdn->pe_number = pe_num;
 281         pe->pdev = dev;
 282         pe->pbus = NULL;
 283         pe->tce32_seg = -1;
 284         pe->mve_number = -1;
 285         pe->rid = dev->bus->number << 8 | pdn->devfn;
 286
 287         pe_info(pe, "Associated device to PE\n");
 288
 289         if (pnv_ioda_configure_pe(phb, pe)) {
 290                 /* XXX What do we do here ? */
 291                 if (pe_num)
 292                         pnv_ioda_free_pe(phb, pe_num);
 293                 pdn->pe_number = IODA_INVALID_PE;
 294                 pe->pdev = NULL;
 295                 pci_dev_put(dev);
 296                 return NULL;
 297         }
 298
 299         /* Assign a DMA weight to the device */
 300         pe->dma_weight = pnv_ioda_dma_weight(dev);
 301         if (pe->dma_weight != 0) {
 302                 phb->ioda.dma_weight += pe->dma_weight;
 303                 phb->ioda.dma_pe_count++;
 304         }
 305
 306         /* Link the PE */
 307         pnv_ioda_link_pe_by_weight(phb, pe);
 308
 309         return pe;
 310 }
 311 #endif /* Useful for SRIOV case */
 312
 313 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
 314 {
 315         struct pci_dev *dev;
 316
 317         list_for_each_entry(dev, &bus->devices, bus_list) {
 318                 struct pci_dn *pdn = pci_get_pdn(dev);
 319
 320                 if (pdn == NULL) {
 321                         pr_warn("%s: No device node associated with device !\n",
 322                                 pci_name(dev));
 323                         continue;
 324                 }
 325                 pci_dev_get(dev);
 326                 pdn->pcidev = dev;
 327                 pdn->pe_number = pe->pe_number;
 328                 pe->dma_weight += pnv_ioda_dma_weight(dev);
 329                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
 330                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
 331         }
 332 }
 333
 334 /*
 335  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
 336  * single PCI bus. Another one that contains the primary PCI bus and its
 337  * subordinate PCI devices and buses. The second type of PE is normally
 338  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
 339  */
 340 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
 341 {
 342         struct pci_controller *hose = pci_bus_to_host(bus);
 343         struct pnv_phb *phb = hose->private_data;
 344         struct pnv_ioda_pe *pe;
 345         int pe_num;
 346
 347         pe_num = pnv_ioda_alloc_pe(phb);
 348         if (pe_num == IODA_INVALID_PE) {
 349                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
 350                         __func__, pci_domain_nr(bus), bus->number);
 351                 return;
 352         }
 353
 354         pe = &phb->ioda.pe_array[pe_num];
 355         pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
 356         pe->pbus = bus;
 357         pe->pdev = NULL;
 358         pe->tce32_seg = -1;
 359         pe->mve_number = -1;
 360         pe->rid = bus->busn_res.start << 8;
 361         pe->dma_weight = 0;
 362
 363         if (all)
 364                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
 365                         bus->busn_res.start, bus->busn_res.end, pe_num);
 366         else
 367                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
 368                         bus->busn_res.start, pe_num);
 369
 370         if (pnv_ioda_configure_pe(phb, pe)) {
 371                 /* XXX What do we do here ? */
 372                 if (pe_num)
 373                         pnv_ioda_free_pe(phb, pe_num);
 374                 pe->pbus = NULL;
 375                 return;
 376         }
 377
 378         /* Associate it with all child devices */
 379         pnv_ioda_setup_same_PE(bus, pe);
 380
 381         /* Put PE to the list */
 382         list_add_tail(&pe->list, &phb->ioda.pe_list);
 383
 384         /* Account for one DMA PE if at least one DMA capable device exist
 385          * below the bridge
 386          */
 387         if (pe->dma_weight != 0) {
 388                 phb->ioda.dma_weight += pe->dma_weight;
 389                 phb->ioda.dma_pe_count++;
 390         }
 391
 392         /* Link the PE */
 393         pnv_ioda_link_pe_by_weight(phb, pe);
 394 }
 395
 396 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
 397 {
 398         struct pci_dev *dev;
 399
 400         pnv_ioda_setup_bus_PE(bus, 0);
 401
 402         list_for_each_entry(dev, &bus->devices, bus_list) {
 403                 if (dev->subordinate) {
 404                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
 405                                 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
 406                         else
 407                                 pnv_ioda_setup_PEs(dev->subordinate);
 408                 }
 409         }
 410 }
 411
 412 /*
 413  * Configure PEs so that the downstream PCI buses and devices
 414  * could have their associated PE#. Unfortunately, we didn't
 415  * figure out the way to identify the PLX bridge yet. So we
 416  * simply put the PCI bus and the subordinate behind the root
 417  * port to PE# here. The game rule here is expected to be changed
 418  * as soon as we can detected PLX bridge correctly.
 419  */
 420 static void pnv_pci_ioda_setup_PEs(void)
 421 {
 422         struct pci_controller *hose, *tmp;
 423
 424         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 425                 pnv_ioda_setup_PEs(hose->bus);
 426         }
 427 }
 428
 429 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
 430 {
 431         struct pci_dn *pdn = pci_get_pdn(pdev);
 432         struct pnv_ioda_pe *pe;
 433
 434         /*
 435          * The function can be called while the PE#
 436          * hasn't been assigned. Do nothing for the
 437          * case.
 438          */
 439         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
 440                 return;
 441
 442         pe = &phb->ioda.pe_array[pdn->pe_number];
 443         set_iommu_table_base(&pdev->dev, &pe->tce32_table);
 444 }
 445
 446 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
 447                                          u64 *startp, u64 *endp)
 448 {
 449         u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
 450         unsigned long start, end, inc;
 451
 452         start = __pa(startp);
 453         end = __pa(endp);
 454
 455         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
 456         if (tbl->it_busno) {
 457                 start <<= 12;
 458                 end <<= 12;
 459                 inc = 128 << 12;
 460                 start |= tbl->it_busno;
 461                 end |= tbl->it_busno;
 462         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
 463                 /* p7ioc-style invalidation, 2 TCEs per write */
 464                 start |= (1ull << 63);
 465                 end |= (1ull << 63);
 466                 inc = 16;
 467         } else {
 468                 /* Default (older HW) */
 469                 inc = 128;
 470         }
 471
 472         end |= inc - 1; /* round up end to be different than start */
 473
 474         mb(); /* Ensure above stores are visible */
 475         while (start <= end) {
 476                 __raw_writeq(start, invalidate);
 477                 start += inc;
 478         }
 479
 480         /*
 481          * The iommu layer will do another mb() for us on build()
 482          * and we don't care on free()
 483          */
 484 }
 485
 486 static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
 487                                          struct iommu_table *tbl,
 488                                          u64 *startp, u64 *endp)
 489 {
 490         unsigned long start, end, inc;
 491         u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
 492
 493         /* We'll invalidate DMA address in PE scope */
 494         start = 0x2ul << 60;
 495         start |= (pe->pe_number & 0xFF);
 496         end = start;
 497
 498         /* Figure out the start, end and step */
 499         inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64));
 500         start |= (inc << 12);
 501         inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64));
 502         end |= (inc << 12);
 503         inc = (0x1ul << 12);
 504         mb();
 505
 506         while (start <= end) {
 507                 __raw_writeq(start, invalidate);
 508                 start += inc;
 509         }
 510 }
 511
 512 void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
 513                                  u64 *startp, u64 *endp)
 514 {
 515         struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
 516                                               tce32_table);
 517         struct pnv_phb *phb = pe->phb;
 518
 519         if (phb->type == PNV_PHB_IODA1)
 520                 pnv_pci_ioda1_tce_invalidate(tbl, startp, endp);
 521         else
 522                 pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp);
 523 }
 524
 525 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
 526                                       struct pnv_ioda_pe *pe, unsigned int base,
 527                                       unsigned int segs)
 528 {
 529
 530         struct page *tce_mem = NULL;
 531         const __be64 *swinvp;
 532         struct iommu_table *tbl;
 533         unsigned int i;
 534         int64_t rc;
 535         void *addr;
 536
 537         /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
 538 #define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
 539
 540         /* XXX FIXME: Handle 64-bit only DMA devices */
 541         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
 542         /* XXX FIXME: Allocate multi-level tables on PHB3 */
 543
 544         /* We shouldn't already have a 32-bit DMA associated */
 545         if (WARN_ON(pe->tce32_seg >= 0))
 546                 return;
 547
 548         /* Grab a 32-bit TCE table */
 549         pe->tce32_seg = base;
 550         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
 551                 (base << 28), ((base + segs) << 28) - 1);
 552
 553         /* XXX Currently, we allocate one big contiguous table for the
 554          * TCEs. We only really need one chunk per 256M of TCE space
 555          * (ie per segment) but that's an optimization for later, it
 556          * requires some added smarts with our get/put_tce implementation
 557          */
 558         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
 559                                    get_order(TCE32_TABLE_SIZE * segs));
 560         if (!tce_mem) {
 561                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
 562                 goto fail;
 563         }
 564         addr = page_address(tce_mem);
 565         memset(addr, 0, TCE32_TABLE_SIZE * segs);
 566
 567         /* Configure HW */
 568         for (i = 0; i < segs; i++) {
 569                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
 570                                               pe->pe_number,
 571                                               base + i, 1,
 572                                               __pa(addr) + TCE32_TABLE_SIZE * i,
 573                                               TCE32_TABLE_SIZE, 0x1000);
 574                 if (rc) {
 575                         pe_err(pe, " Failed to configure 32-bit TCE table,"
 576                                " err %ld\n", rc);
 577                         goto fail;
 578                 }
 579         }
 580
 581         /* Setup linux iommu table */
 582         tbl = &pe->tce32_table;
 583         pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
 584                                   base << 28);
 585
 586         /* OPAL variant of P7IOC SW invalidated TCEs */
 587         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
 588         if (swinvp) {
 589                 /* We need a couple more fields -- an address and a data
 590                  * to or.  Since the bus is only printed out on table free
 591                  * errors, and on the first pass the data will be a relative
 592                  * bus number, print that out instead.
 593                  */
 594                 tbl->it_busno = 0;
 595                 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
 596                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE |
 597                                TCE_PCI_SWINV_PAIR;
 598         }
 599         iommu_init_table(tbl, phb->hose->node);
 600         iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number);
 601
 602         return;
 603  fail:
 604         /* XXX Failure: Try to fallback to 64-bit only ? */
 605         if (pe->tce32_seg >= 0)
 606                 pe->tce32_seg = -1;
 607         if (tce_mem)
 608                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
 609 }
 610
 611 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
 612                                        struct pnv_ioda_pe *pe)
 613 {
 614         struct page *tce_mem = NULL;
 615         void *addr;
 616         const __be64 *swinvp;
 617         struct iommu_table *tbl;
 618         unsigned int tce_table_size, end;
 619         int64_t rc;
 620
 621         /* We shouldn't already have a 32-bit DMA associated */
 622         if (WARN_ON(pe->tce32_seg >= 0))
 623                 return;
 624
 625         /* The PE will reserve all possible 32-bits space */
 626         pe->tce32_seg = 0;
 627         end = (1 << ilog2(phb->ioda.m32_pci_base));
 628         tce_table_size = (end / 0x1000) * 8;
 629         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
 630                 end);
 631
 632         /* Allocate TCE table */
 633         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
 634                                    get_order(tce_table_size));
 635         if (!tce_mem) {
 636                 pe_err(pe, "Failed to allocate a 32-bit TCE memory\n");
 637                 goto fail;
 638         }
 639         addr = page_address(tce_mem);
 640         memset(addr, 0, tce_table_size);
 641
 642         /*
 643          * Map TCE table through TVT. The TVE index is the PE number
 644          * shifted by 1 bit for 32-bits DMA space.
 645          */
 646         rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
 647                                         pe->pe_number << 1, 1, __pa(addr),
 648                                         tce_table_size, 0x1000);
 649         if (rc) {
 650                 pe_err(pe, "Failed to configure 32-bit TCE table,"
 651                        " err %ld\n", rc);
 652                 goto fail;
 653         }
 654
 655         /* Setup linux iommu table */
 656         tbl = &pe->tce32_table;
 657         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0);
 658
 659         /* OPAL variant of PHB3 invalidated TCEs */
 660         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
 661         if (swinvp) {
 662                 /* We need a couple more fields -- an address and a data
 663                  * to or.  Since the bus is only printed out on table free
 664                  * errors, and on the first pass the data will be a relative
 665                  * bus number, print that out instead.
 666                  */
 667                 tbl->it_busno = 0;
 668                 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
 669                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 670         }
 671         iommu_init_table(tbl, phb->hose->node);
 672
 673         return;
 674 fail:
 675         if (pe->tce32_seg >= 0)
 676                 pe->tce32_seg = -1;
 677         if (tce_mem)
 678                 __free_pages(tce_mem, get_order(tce_table_size));
 679 }
 680
 681 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
 682 {
 683         struct pci_controller *hose = phb->hose;
 684         unsigned int residual, remaining, segs, tw, base;
 685         struct pnv_ioda_pe *pe;
 686
 687         /* If we have more PE# than segments available, hand out one
 688          * per PE until we run out and let the rest fail. If not,
 689          * then we assign at least one segment per PE, plus more based
 690          * on the amount of devices under that PE
 691          */
 692         if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
 693                 residual = 0;
 694         else
 695                 residual = phb->ioda.tce32_count -
 696                         phb->ioda.dma_pe_count;
 697
 698         pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
 699                 hose->global_number, phb->ioda.tce32_count);
 700         pr_info("PCI: %d PE# for a total weight of %d\n",
 701                 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
 702
 703         /* Walk our PE list and configure their DMA segments, hand them
 704          * out one base segment plus any residual segments based on
 705          * weight
 706          */
 707         remaining = phb->ioda.tce32_count;
 708         tw = phb->ioda.dma_weight;
 709         base = 0;
 710         list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
 711                 if (!pe->dma_weight)
 712                         continue;
 713                 if (!remaining) {
 714                         pe_warn(pe, "No DMA32 resources available\n");
 715                         continue;
 716                 }
 717                 segs = 1;
 718                 if (residual) {
 719                         segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
 720                         if (segs > remaining)
 721                                 segs = remaining;
 722                 }
 723
 724                 /*
 725                  * For IODA2 compliant PHB3, we needn't care about the weight.
 726                  * The all available 32-bits DMA space will be assigned to
 727                  * the specific PE.
 728                  */
 729                 if (phb->type == PNV_PHB_IODA1) {
 730                         pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
 731                                 pe->dma_weight, segs);
 732                         pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
 733                 } else {
 734                         pe_info(pe, "Assign DMA32 space\n");
 735                         segs = 0;
 736                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
 737                 }
 738
 739                 remaining -= segs;
 740                 base += segs;
 741         }
 742 }
 743
 744 #ifdef CONFIG_PCI_MSI
 745 static void pnv_ioda2_msi_eoi(struct irq_data *d)
 746 {
 747         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 748         struct irq_chip *chip = irq_data_get_irq_chip(d);
 749         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
 750                                            ioda.irq_chip);
 751         int64_t rc;
 752
 753         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
 754         WARN_ON_ONCE(rc);
 755
 756         icp_native_eoi(d);
 757 }
 758
 759 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
 760                                   unsigned int hwirq, unsigned int virq,
 761                                   unsigned int is_64, struct msi_msg *msg)
 762 {
 763         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
 764         struct pci_dn *pdn = pci_get_pdn(dev);
 765         struct irq_data *idata;
 766         struct irq_chip *ichip;
 767         unsigned int xive_num = hwirq - phb->msi_base;
 768         uint64_t addr64;
 769         uint32_t addr32, data;
 770         int rc;
 771
 772         /* No PE assigned ? bail out ... no MSI for you ! */
 773         if (pe == NULL)
 774                 return -ENXIO;
 775
 776         /* Check if we have an MVE */
 777         if (pe->mve_number < 0)
 778                 return -ENXIO;
 779
 780         /* Force 32-bit MSI on some broken devices */
 781         if (pdn && pdn->force_32bit_msi)
 782                 is_64 = 0;
 783
 784         /* Assign XIVE to PE */
 785         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
 786         if (rc) {
 787                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
 788                         pci_name(dev), rc, xive_num);
 789                 return -EIO;
 790         }
 791
 792         if (is_64) {
 793                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
 794                                      &addr64, &data);
 795                 if (rc) {
 796                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
 797                                 pci_name(dev), rc);
 798                         return -EIO;
 799                 }
 800                 msg->address_hi = addr64 >> 32;
 801                 msg->address_lo = addr64 & 0xfffffffful;
 802         } else {
 803                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
 804                                      &addr32, &data);
 805                 if (rc) {
 806                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
 807                                 pci_name(dev), rc);
 808                         return -EIO;
 809                 }
 810                 msg->address_hi = 0;
 811                 msg->address_lo = addr32;
 812         }
 813         msg->data = data;
 814
 815         /*
 816          * Change the IRQ chip for the MSI interrupts on PHB3.
 817          * The corresponding IRQ chip should be populated for
 818          * the first time.
 819          */
 820         if (phb->type == PNV_PHB_IODA2) {
 821                 if (!phb->ioda.irq_chip_init) {
 822                         idata = irq_get_irq_data(virq);
 823                         ichip = irq_data_get_irq_chip(idata);
 824                         phb->ioda.irq_chip_init = 1;
 825                         phb->ioda.irq_chip = *ichip;
 826                         phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
 827                 }
 828
 829                 irq_set_chip(virq, &phb->ioda.irq_chip);
 830         }
 831
 832         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
 833                  " address=%x_%08x data=%x PE# %d\n",
 834                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
 835                  msg->address_hi, msg->address_lo, data, pe->pe_number);
 836
 837         return 0;
 838 }
 839
 840 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
 841 {
 842         unsigned int count;
 843         const __be32 *prop = of_get_property(phb->hose->dn,
 844                                              "ibm,opal-msi-ranges", NULL);
 845         if (!prop) {
 846                 /* BML Fallback */
 847                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
 848         }
 849         if (!prop)
 850                 return;
 851
 852         phb->msi_base = be32_to_cpup(prop);
 853         count = be32_to_cpup(prop + 1);
 854         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
 855                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
 856                        phb->hose->global_number);
 857                 return;
 858         }
 859
 860         phb->msi_setup = pnv_pci_ioda_msi_setup;
 861         phb->msi32_support = 1;
 862         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
 863                 count, phb->msi_base);
 864 }
 865 #else
 866 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
 867 #endif /* CONFIG_PCI_MSI */
 868
 869 /*
 870  * This function is supposed to be called on basis of PE from top
 871  * to bottom style. So the the I/O or MMIO segment assigned to
 872  * parent PE could be overrided by its child PEs if necessary.
 873  */
 874 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
 875                                   struct pnv_ioda_pe *pe)
 876 {
 877         struct pnv_phb *phb = hose->private_data;
 878         struct pci_bus_region region;
 879         struct resource *res;
 880         int i, index;
 881         int rc;
 882
 883         /*
 884          * NOTE: We only care PCI bus based PE for now. For PCI
 885          * device based PE, for example SRIOV sensitive VF should
 886          * be figured out later.
 887          */
 888         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
 889
 890         pci_bus_for_each_resource(pe->pbus, res, i) {
 891                 if (!res || !res->flags ||
 892                     res->start > res->end)
 893                         continue;
 894
 895                 if (res->flags & IORESOURCE_IO) {
 896                         region.start = res->start - phb->ioda.io_pci_base;
 897                         region.end   = res->end - phb->ioda.io_pci_base;
 898                         index = region.start / phb->ioda.io_segsize;
 899
 900                         while (index < phb->ioda.total_pe &&
 901                                region.start <= region.end) {
 902                                 phb->ioda.io_segmap[index] = pe->pe_number;
 903                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 904                                         pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
 905                                 if (rc != OPAL_SUCCESS) {
 906                                         pr_err("%s: OPAL error %d when mapping IO "
 907                                                "segment #%d to PE#%d\n",
 908                                                __func__, rc, index, pe->pe_number);
 909                                         break;
 910                                 }
 911
 912                                 region.start += phb->ioda.io_segsize;
 913                                 index++;
 914                         }
 915                 } else if (res->flags & IORESOURCE_MEM) {
 916                         /* WARNING: Assumes M32 is mem region 0 in PHB. We need to
 917                          * harden that algorithm when we start supporting M64
 918                          */
 919                         region.start = res->start -
 920                                        hose->mem_offset[0] -
 921                                        phb->ioda.m32_pci_base;
 922                         region.end   = res->end -
 923                                        hose->mem_offset[0] -
 924                                        phb->ioda.m32_pci_base;
 925                         index = region.start / phb->ioda.m32_segsize;
 926
 927                         while (index < phb->ioda.total_pe &&
 928                                region.start <= region.end) {
 929                                 phb->ioda.m32_segmap[index] = pe->pe_number;
 930                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 931                                         pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
 932                                 if (rc != OPAL_SUCCESS) {
 933                                         pr_err("%s: OPAL error %d when mapping M32 "
 934                                                "segment#%d to PE#%d",
 935                                                __func__, rc, index, pe->pe_number);
 936                                         break;
 937                                 }
 938
 939                                 region.start += phb->ioda.m32_segsize;
 940                                 index++;
 941                         }
 942                 }
 943         }
 944 }
 945
 946 static void pnv_pci_ioda_setup_seg(void)
 947 {
 948         struct pci_controller *tmp, *hose;
 949         struct pnv_phb *phb;
 950         struct pnv_ioda_pe *pe;
 951
 952         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 953                 phb = hose->private_data;
 954                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
 955                         pnv_ioda_setup_pe_seg(hose, pe);
 956                 }
 957         }
 958 }
 959
 960 static void pnv_pci_ioda_setup_DMA(void)
 961 {
 962         struct pci_controller *hose, *tmp;
 963         struct pnv_phb *phb;
 964
 965         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 966                 pnv_ioda_setup_dma(hose->private_data);
 967
 968                 /* Mark the PHB initialization done */
 969                 phb = hose->private_data;
 970                 phb->initialized = 1;
 971         }
 972 }
 973
 974 static void pnv_pci_ioda_create_dbgfs(void)
 975 {
 976 #ifdef CONFIG_DEBUG_FS
 977         struct pci_controller *hose, *tmp;
 978         struct pnv_phb *phb;
 979         char name[16];
 980
 981         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 982                 phb = hose->private_data;
 983
 984                 sprintf(name, "PCI%04x", hose->global_number);
 985                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
 986                 if (!phb->dbgfs)
 987                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
 988                                 __func__, hose->global_number);
 989         }
 990 #endif /* CONFIG_DEBUG_FS */
 991 }
 992
 993 static void pnv_pci_ioda_fixup(void)
 994 {
 995         pnv_pci_ioda_setup_PEs();
 996         pnv_pci_ioda_setup_seg();
 997         pnv_pci_ioda_setup_DMA();
 998
 999         pnv_pci_ioda_create_dbgfs();
1000
1001 #ifdef CONFIG_EEH
1002         eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
1003         eeh_addr_cache_build();
1004         eeh_init();
1005 #endif
1006 }
1007
1008 /*
1009  * Returns the alignment for I/O or memory windows for P2P
1010  * bridges. That actually depends on how PEs are segmented.
1011  * For now, we return I/O or M32 segment size for PE sensitive
1012  * P2P bridges. Otherwise, the default values (4KiB for I/O,
1013  * 1MiB for memory) will be returned.
1014  *
1015  * The current PCI bus might be put into one PE, which was
1016  * create against the parent PCI bridge. For that case, we
1017  * needn't enlarge the alignment so that we can save some
1018  * resources.
1019  */
1020 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
1021                                                 unsigned long type)
1022 {
1023         struct pci_dev *bridge;
1024         struct pci_controller *hose = pci_bus_to_host(bus);
1025         struct pnv_phb *phb = hose->private_data;
1026         int num_pci_bridges = 0;
1027
1028         bridge = bus->self;
1029         while (bridge) {
1030                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
1031                         num_pci_bridges++;
1032                         if (num_pci_bridges >= 2)
1033                                 return 1;
1034                 }
1035
1036                 bridge = bridge->bus->self;
1037         }
1038
1039         /* We need support prefetchable memory window later */
1040         if (type & IORESOURCE_MEM)
1041                 return phb->ioda.m32_segsize;
1042
1043         return phb->ioda.io_segsize;
1044 }
1045
1046 /* Prevent enabling devices for which we couldn't properly
1047  * assign a PE
1048  */
1049 static int pnv_pci_enable_device_hook(struct pci_dev *dev)
1050 {
1051         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1052         struct pnv_phb *phb = hose->private_data;
1053         struct pci_dn *pdn;
1054
1055         /* The function is probably called while the PEs have
1056          * not be created yet. For example, resource reassignment
1057          * during PCI probe period. We just skip the check if
1058          * PEs isn't ready.
1059          */
1060         if (!phb->initialized)
1061                 return 0;
1062
1063         pdn = pci_get_pdn(dev);
1064         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1065                 return -EINVAL;
1066
1067         return 0;
1068 }
1069
1070 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
1071                                u32 devfn)
1072 {
1073         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
1074 }
1075
1076 static void pnv_pci_ioda_shutdown(struct pnv_phb *phb)
1077 {
1078         opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET,
1079                        OPAL_ASSERT_RESET);
1080 }
1081
1082 void __init pnv_pci_init_ioda_phb(struct device_node *np,
1083                                   u64 hub_id, int ioda_type)
1084 {
1085         struct pci_controller *hose;
1086         static int primary = 1;
1087         struct pnv_phb *phb;
1088         unsigned long size, m32map_off, iomap_off, pemap_off;
1089         const u64 *prop64;
1090         const u32 *prop32;
1091         u64 phb_id;
1092         void *aux;
1093         long rc;
1094
1095         pr_info(" Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
1096
1097         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
1098         if (!prop64) {
1099                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
1100                 return;
1101         }
1102         phb_id = be64_to_cpup(prop64);
1103         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
1104
1105         phb = alloc_bootmem(sizeof(struct pnv_phb));
1106         if (phb) {
1107                 memset(phb, 0, sizeof(struct pnv_phb));
1108                 phb->hose = hose = pcibios_alloc_controller(np);
1109         }
1110         if (!phb || !phb->hose) {
1111                 pr_err("PCI: Failed to allocate PCI controller for %s\n",
1112                        np->full_name);
1113                 return;
1114         }
1115
1116         spin_lock_init(&phb->lock);
1117         /* XXX Use device-tree */
1118         hose->first_busno = 0;
1119         hose->last_busno = 0xff;
1120         hose->private_data = phb;
1121         phb->hub_id = hub_id;
1122         phb->opal_id = phb_id;
1123         phb->type = ioda_type;
1124
1125         /* Detect specific models for error handling */
1126         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
1127                 phb->model = PNV_PHB_MODEL_P7IOC;
1128         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
1129                 phb->model = PNV_PHB_MODEL_PHB3;
1130         else
1131                 phb->model = PNV_PHB_MODEL_UNKNOWN;
1132
1133         /* Parse 32-bit and IO ranges (if any) */
1134         pci_process_bridge_OF_ranges(phb->hose, np, primary);
1135         primary = 0;
1136
1137         /* Get registers */
1138         phb->regs = of_iomap(np, 0);
1139         if (phb->regs == NULL)
1140                 pr_err("  Failed to map registers !\n");
1141
1142         /* Initialize more IODA stuff */
1143         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
1144         if (!prop32)
1145                 phb->ioda.total_pe = 1;
1146         else
1147                 phb->ioda.total_pe = *prop32;
1148
1149         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
1150         /* FW Has already off top 64k of M32 space (MSI space) */
1151         phb->ioda.m32_size += 0x10000;
1152
1153         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
1154         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
1155         phb->ioda.io_size = hose->pci_io_size;
1156         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
1157         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
1158
1159         /* Allocate aux data & arrays
1160          *
1161          * XXX TODO: Don't allocate io segmap on PHB3
1162          */
1163         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
1164         m32map_off = size;
1165         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
1166         iomap_off = size;
1167         size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
1168         pemap_off = size;
1169         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
1170         aux = alloc_bootmem(size);
1171         memset(aux, 0, size);
1172         phb->ioda.pe_alloc = aux;
1173         phb->ioda.m32_segmap = aux + m32map_off;
1174         phb->ioda.io_segmap = aux + iomap_off;
1175         phb->ioda.pe_array = aux + pemap_off;
1176         set_bit(0, phb->ioda.pe_alloc);
1177
1178         INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
1179         INIT_LIST_HEAD(&phb->ioda.pe_list);
1180
1181         /* Calculate how many 32-bit TCE segments we have */
1182         phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
1183
1184         /* Clear unusable m64 */
1185         hose->mem_resources[1].flags = 0;
1186         hose->mem_resources[1].start = 0;
1187         hose->mem_resources[1].end = 0;
1188         hose->mem_resources[2].flags = 0;
1189         hose->mem_resources[2].start = 0;
1190         hose->mem_resources[2].end = 0;
1191
1192 #if 0 /* We should really do that ... */
1193         rc = opal_pci_set_phb_mem_window(opal->phb_id,
1194                                          window_type,
1195                                          window_num,
1196                                          starting_real_address,
1197                                          starting_pci_address,
1198                                          segment_size);
1199 #endif
1200
1201         pr_info("  %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n",
1202                 phb->ioda.total_pe,
1203                 phb->ioda.m32_size, phb->ioda.m32_segsize,
1204                 phb->ioda.io_size, phb->ioda.io_segsize);
1205
1206         phb->hose->ops = &pnv_pci_ops;
1207 #ifdef CONFIG_EEH
1208         phb->eeh_ops = &ioda_eeh_ops;
1209 #endif
1210
1211         /* Setup RID -> PE mapping function */
1212         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
1213
1214         /* Setup TCEs */
1215         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
1216
1217         /* Setup shutdown function for kexec */
1218         phb->shutdown = pnv_pci_ioda_shutdown;
1219
1220         /* Setup MSI support */
1221         pnv_pci_init_ioda_msis(phb);
1222
1223         /*
1224          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
1225          * to let the PCI core do resource assignment. It's supposed
1226          * that the PCI core will do correct I/O and MMIO alignment
1227          * for the P2P bridge bars so that each PCI bus (excluding
1228          * the child P2P bridges) can form individual PE.
1229          */
1230         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
1231         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
1232         ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
1233         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1234
1235         /* Reset IODA tables to a clean state */
1236         rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
1237         if (rc)
1238                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
1239
1240         /*
1241          * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset
1242          * has cleared the RTT which has the same effect
1243          */
1244         if (ioda_type == PNV_PHB_IODA1)
1245                 opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
1246 }
1247
1248 void pnv_pci_init_ioda2_phb(struct device_node *np)
1249 {
1250         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
1251 }
1252
1253 void __init pnv_pci_init_ioda_hub(struct device_node *np)
1254 {
1255         struct device_node *phbn;
1256         const u64 *prop64;
1257         u64 hub_id;
1258
1259         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
1260
1261         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
1262         if (!prop64) {
1263                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
1264                 return;
1265         }
1266         hub_id = be64_to_cpup(prop64);
1267         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
1268
1269         /* Count child PHBs */
1270         for_each_child_of_node(np, phbn) {
1271                 /* Look for IODA1 PHBs */
1272                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
1273                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
1274         }
1275 }