arch/powerpc/platforms/powernv/eeh-ioda.c

   1 /*
   2  * The file intends to implement the functions needed by EEH, which is
   3  * built on IODA compliant chip. Actually, lots of functions related
   4  * to EEH would be built based on the OPAL APIs.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/bootmem.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/kernel.h>
  21 #include <linux/msi.h>
  22 #include <linux/notifier.h>
  23 #include <linux/pci.h>
  24 #include <linux/string.h>
  25
  26 #include <asm/eeh.h>
  27 #include <asm/eeh_event.h>
  28 #include <asm/io.h>
  29 #include <asm/iommu.h>
  30 #include <asm/msi_bitmap.h>
  31 #include <asm/opal.h>
  32 #include <asm/pci-bridge.h>
  33 #include <asm/ppc-pci.h>
  34 #include <asm/tce.h>
  35
  36 #include "powernv.h"
  37 #include "pci.h"
  38
  39 static int ioda_eeh_nb_init = 0;
  40
  41 static int ioda_eeh_event(struct notifier_block *nb,
  42                           unsigned long events, void *change)
  43 {
  44         uint64_t changed_evts = (uint64_t)change;
  45
  46         /* We simply send special EEH event */
  47         if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
  48             (events & OPAL_EVENT_PCI_ERROR))
  49                 eeh_send_failure_event(NULL);
  50
  51         return 0;
  52 }
  53
  54 static struct notifier_block ioda_eeh_nb = {
  55         .notifier_call  = ioda_eeh_event,
  56         .next           = NULL,
  57         .priority       = 0
  58 };
  59
  60 #ifdef CONFIG_DEBUG_FS
  61 static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val)
  62 {
  63         struct pci_controller *hose = data;
  64         struct pnv_phb *phb = hose->private_data;
  65
  66         out_be64(phb->regs + offset, val);
  67         return 0;
  68 }
  69
  70 static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val)
  71 {
  72         struct pci_controller *hose = data;
  73         struct pnv_phb *phb = hose->private_data;
  74
  75         *val = in_be64(phb->regs + offset);
  76         return 0;
  77 }
  78
  79 static int ioda_eeh_outb_dbgfs_set(void *data, u64 val)
  80 {
  81         return ioda_eeh_dbgfs_set(data, 0xD10, val);
  82 }
  83
  84 static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val)
  85 {
  86         return ioda_eeh_dbgfs_get(data, 0xD10, val);
  87 }
  88
  89 static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val)
  90 {
  91         return ioda_eeh_dbgfs_set(data, 0xD90, val);
  92 }
  93
  94 static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val)
  95 {
  96         return ioda_eeh_dbgfs_get(data, 0xD90, val);
  97 }
  98
  99 static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val)
 100 {
 101         return ioda_eeh_dbgfs_set(data, 0xE10, val);
 102 }
 103
 104 static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val)
 105 {
 106         return ioda_eeh_dbgfs_get(data, 0xE10, val);
 107 }
 108
 109 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get,
 110                         ioda_eeh_outb_dbgfs_set, "0x%llx\n");
 111 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get,
 112                         ioda_eeh_inbA_dbgfs_set, "0x%llx\n");
 113 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get,
 114                         ioda_eeh_inbB_dbgfs_set, "0x%llx\n");
 115 #endif /* CONFIG_DEBUG_FS */
 116
 117 /**
 118  * ioda_eeh_post_init - Chip dependent post initialization
 119  * @hose: PCI controller
 120  *
 121  * The function will be called after eeh PEs and devices
 122  * have been built. That means the EEH is ready to supply
 123  * service with I/O cache.
 124  */
 125 static int ioda_eeh_post_init(struct pci_controller *hose)
 126 {
 127         struct pnv_phb *phb = hose->private_data;
 128         int ret;
 129
 130         /* Register OPAL event notifier */
 131         if (!ioda_eeh_nb_init) {
 132                 ret = opal_notifier_register(&ioda_eeh_nb);
 133                 if (ret) {
 134                         pr_err("%s: Can't register OPAL event notifier (%d)\n",
 135                                __func__, ret);
 136                         return ret;
 137                 }
 138
 139                 ioda_eeh_nb_init = 1;
 140         }
 141
 142 #ifdef CONFIG_DEBUG_FS
 143         if (phb->dbgfs) {
 144                 debugfs_create_file("err_injct_outbound", 0600,
 145                                     phb->dbgfs, hose,
 146                                     &ioda_eeh_outb_dbgfs_ops);
 147                 debugfs_create_file("err_injct_inboundA", 0600,
 148                                     phb->dbgfs, hose,
 149                                     &ioda_eeh_inbA_dbgfs_ops);
 150                 debugfs_create_file("err_injct_inboundB", 0600,
 151                                     phb->dbgfs, hose,
 152                                     &ioda_eeh_inbB_dbgfs_ops);
 153         }
 154 #endif
 155
 156         phb->eeh_state |= PNV_EEH_STATE_ENABLED;
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * ioda_eeh_set_option - Set EEH operation or I/O setting
 163  * @pe: EEH PE
 164  * @option: options
 165  *
 166  * Enable or disable EEH option for the indicated PE. The
 167  * function also can be used to enable I/O or DMA for the
 168  * PE.
 169  */
 170 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
 171 {
 172         s64 ret;
 173         u32 pe_no;
 174         struct pci_controller *hose = pe->phb;
 175         struct pnv_phb *phb = hose->private_data;
 176
 177         /* Check on PE number */
 178         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 179                 pr_err("%s: PE address %x out of range [0, %x] "
 180                        "on PHB#%x\n",
 181                         __func__, pe->addr, phb->ioda.total_pe,
 182                         hose->global_number);
 183                 return -EINVAL;
 184         }
 185
 186         pe_no = pe->addr;
 187         switch (option) {
 188         case EEH_OPT_DISABLE:
 189                 ret = -EEXIST;
 190                 break;
 191         case EEH_OPT_ENABLE:
 192                 ret = 0;
 193                 break;
 194         case EEH_OPT_THAW_MMIO:
 195                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 196                                 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
 197                 if (ret) {
 198                         pr_warning("%s: Failed to enable MMIO for "
 199                                    "PHB#%x-PE#%x, err=%lld\n",
 200                                 __func__, hose->global_number, pe_no, ret);
 201                         return -EIO;
 202                 }
 203
 204                 break;
 205         case EEH_OPT_THAW_DMA:
 206                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 207                                 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
 208                 if (ret) {
 209                         pr_warning("%s: Failed to enable DMA for "
 210                                    "PHB#%x-PE#%x, err=%lld\n",
 211                                 __func__, hose->global_number, pe_no, ret);
 212                         return -EIO;
 213                 }
 214
 215                 break;
 216         default:
 217                 pr_warning("%s: Invalid option %d\n", __func__, option);
 218                 return -EINVAL;
 219         }
 220
 221         return ret;
 222 }
 223
 224 /**
 225  * ioda_eeh_get_state - Retrieve the state of PE
 226  * @pe: EEH PE
 227  *
 228  * The PE's state should be retrieved from the PEEV, PEST
 229  * IODA tables. Since the OPAL has exported the function
 230  * to do it, it'd better to use that.
 231  */
 232 static int ioda_eeh_get_state(struct eeh_pe *pe)
 233 {
 234         s64 ret = 0;
 235         u8 fstate;
 236         u16 pcierr;
 237         u32 pe_no;
 238         int result;
 239         struct pci_controller *hose = pe->phb;
 240         struct pnv_phb *phb = hose->private_data;
 241
 242         /*
 243          * Sanity check on PE address. The PHB PE address should
 244          * be zero.
 245          */
 246         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 247                 pr_err("%s: PE address %x out of range [0, %x] "
 248                        "on PHB#%x\n",
 249                        __func__, pe->addr, phb->ioda.total_pe,
 250                        hose->global_number);
 251                 return EEH_STATE_NOT_SUPPORT;
 252         }
 253
 254         /* Retrieve PE status through OPAL */
 255         pe_no = pe->addr;
 256         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 257                         &fstate, &pcierr, NULL);
 258         if (ret) {
 259                 pr_err("%s: Failed to get EEH status on "
 260                        "PHB#%x-PE#%x\n, err=%lld\n",
 261                        __func__, hose->global_number, pe_no, ret);
 262                 return EEH_STATE_NOT_SUPPORT;
 263         }
 264
 265         /* Check PHB status */
 266         if (pe->type & EEH_PE_PHB) {
 267                 result = 0;
 268                 result &= ~EEH_STATE_RESET_ACTIVE;
 269
 270                 if (pcierr != OPAL_EEH_PHB_ERROR) {
 271                         result |= EEH_STATE_MMIO_ACTIVE;
 272                         result |= EEH_STATE_DMA_ACTIVE;
 273                         result |= EEH_STATE_MMIO_ENABLED;
 274                         result |= EEH_STATE_DMA_ENABLED;
 275                 }
 276
 277                 return result;
 278         }
 279
 280         /* Parse result out */
 281         result = 0;
 282         switch (fstate) {
 283         case OPAL_EEH_STOPPED_NOT_FROZEN:
 284                 result &= ~EEH_STATE_RESET_ACTIVE;
 285                 result |= EEH_STATE_MMIO_ACTIVE;
 286                 result |= EEH_STATE_DMA_ACTIVE;
 287                 result |= EEH_STATE_MMIO_ENABLED;
 288                 result |= EEH_STATE_DMA_ENABLED;
 289                 break;
 290         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 291                 result &= ~EEH_STATE_RESET_ACTIVE;
 292                 result |= EEH_STATE_DMA_ACTIVE;
 293                 result |= EEH_STATE_DMA_ENABLED;
 294                 break;
 295         case OPAL_EEH_STOPPED_DMA_FREEZE:
 296                 result &= ~EEH_STATE_RESET_ACTIVE;
 297                 result |= EEH_STATE_MMIO_ACTIVE;
 298                 result |= EEH_STATE_MMIO_ENABLED;
 299                 break;
 300         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 301                 result &= ~EEH_STATE_RESET_ACTIVE;
 302                 break;
 303         case OPAL_EEH_STOPPED_RESET:
 304                 result |= EEH_STATE_RESET_ACTIVE;
 305                 break;
 306         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 307                 result |= EEH_STATE_UNAVAILABLE;
 308                 break;
 309         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 310                 result |= EEH_STATE_NOT_SUPPORT;
 311                 break;
 312         default:
 313                 pr_warning("%s: Unexpected EEH status 0x%x "
 314                            "on PHB#%x-PE#%x\n",
 315                            __func__, fstate, hose->global_number, pe_no);
 316         }
 317
 318         return result;
 319 }
 320
 321 static int ioda_eeh_pe_clear(struct eeh_pe *pe)
 322 {
 323         struct pci_controller *hose;
 324         struct pnv_phb *phb;
 325         u32 pe_no;
 326         u8 fstate;
 327         u16 pcierr;
 328         s64 ret;
 329
 330         pe_no = pe->addr;
 331         hose = pe->phb;
 332         phb = pe->phb->private_data;
 333
 334         /* Clear the EEH error on the PE */
 335         ret = opal_pci_eeh_freeze_clear(phb->opal_id,
 336                         pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 337         if (ret) {
 338                 pr_err("%s: Failed to clear EEH error for "
 339                        "PHB#%x-PE#%x, err=%lld\n",
 340                        __func__, hose->global_number, pe_no, ret);
 341                 return -EIO;
 342         }
 343
 344         /*
 345          * Read the PE state back and verify that the frozen
 346          * state has been removed.
 347          */
 348         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 349                         &fstate, &pcierr, NULL);
 350         if (ret) {
 351                 pr_err("%s: Failed to get EEH status on "
 352                        "PHB#%x-PE#%x\n, err=%lld\n",
 353                        __func__, hose->global_number, pe_no, ret);
 354                 return -EIO;
 355         }
 356
 357         if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
 358                 pr_err("%s: Frozen state not cleared on "
 359                        "PHB#%x-PE#%x, sts=%x\n",
 360                        __func__, hose->global_number, pe_no, fstate);
 361                 return -EIO;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
 368 {
 369         s64 rc = OPAL_HARDWARE;
 370
 371         while (1) {
 372                 rc = opal_pci_poll(phb->opal_id);
 373                 if (rc <= 0)
 374                         break;
 375
 376                 msleep(rc);
 377         }
 378
 379         return rc;
 380 }
 381
 382 static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 383 {
 384         struct pnv_phb *phb = hose->private_data;
 385         s64 rc = OPAL_HARDWARE;
 386
 387         pr_debug("%s: Reset PHB#%x, option=%d\n",
 388                  __func__, hose->global_number, option);
 389
 390         /* Issue PHB complete reset request */
 391         if (option == EEH_RESET_FUNDAMENTAL ||
 392             option == EEH_RESET_HOT)
 393                 rc = opal_pci_reset(phb->opal_id,
 394                                 OPAL_PHB_COMPLETE,
 395                                 OPAL_ASSERT_RESET);
 396         else if (option == EEH_RESET_DEACTIVATE)
 397                 rc = opal_pci_reset(phb->opal_id,
 398                                 OPAL_PHB_COMPLETE,
 399                                 OPAL_DEASSERT_RESET);
 400         if (rc < 0)
 401                 goto out;
 402
 403         /*
 404          * Poll state of the PHB until the request is done
 405          * successfully.
 406          */
 407         rc = ioda_eeh_phb_poll(phb);
 408 out:
 409         if (rc != OPAL_SUCCESS)
 410                 return -EIO;
 411
 412         return 0;
 413 }
 414
 415 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
 416 {
 417         struct pnv_phb *phb = hose->private_data;
 418         s64 rc = OPAL_SUCCESS;
 419
 420         pr_debug("%s: Reset PHB#%x, option=%d\n",
 421                  __func__, hose->global_number, option);
 422
 423         /*
 424          * During the reset deassert time, we needn't care
 425          * the reset scope because the firmware does nothing
 426          * for fundamental or hot reset during deassert phase.
 427          */
 428         if (option == EEH_RESET_FUNDAMENTAL)
 429                 rc = opal_pci_reset(phb->opal_id,
 430                                 OPAL_PCI_FUNDAMENTAL_RESET,
 431                                 OPAL_ASSERT_RESET);
 432         else if (option == EEH_RESET_HOT)
 433                 rc = opal_pci_reset(phb->opal_id,
 434                                 OPAL_PCI_HOT_RESET,
 435                                 OPAL_ASSERT_RESET);
 436         else if (option == EEH_RESET_DEACTIVATE)
 437                 rc = opal_pci_reset(phb->opal_id,
 438                                 OPAL_PCI_HOT_RESET,
 439                                 OPAL_DEASSERT_RESET);
 440         if (rc < 0)
 441                 goto out;
 442
 443         /* Poll state of the PHB until the request is done */
 444         rc = ioda_eeh_phb_poll(phb);
 445 out:
 446         if (rc != OPAL_SUCCESS)
 447                 return -EIO;
 448
 449         return 0;
 450 }
 451
 452 static int ioda_eeh_bridge_reset(struct pci_controller *hose,
 453                 struct pci_dev *dev, int option)
 454 {
 455         u16 ctrl;
 456
 457         pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
 458                  __func__, hose->global_number, dev->bus->number,
 459                  PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
 460
 461         switch (option) {
 462         case EEH_RESET_FUNDAMENTAL:
 463         case EEH_RESET_HOT:
 464                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 465                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
 466                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 467                 break;
 468         case EEH_RESET_DEACTIVATE:
 469                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 470                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 471                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 472                 break;
 473         }
 474
 475         return 0;
 476 }
 477
 478 /**
 479  * ioda_eeh_reset - Reset the indicated PE
 480  * @pe: EEH PE
 481  * @option: reset option
 482  *
 483  * Do reset on the indicated PE. For PCI bus sensitive PE,
 484  * we need to reset the parent p2p bridge. The PHB has to
 485  * be reinitialized if the p2p bridge is root bridge. For
 486  * PCI device sensitive PE, we will try to reset the device
 487  * through FLR. For now, we don't have OPAL APIs to do HARD
 488  * reset yet, so all reset would be SOFT (HOT) reset.
 489  */
 490 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
 491 {
 492         struct pci_controller *hose = pe->phb;
 493         struct eeh_dev *edev;
 494         struct pci_dev *dev;
 495         int ret;
 496
 497         /*
 498          * Anyway, we have to clear the problematic state for the
 499          * corresponding PE. However, we needn't do it if the PE
 500          * is PHB associated. That means the PHB is having fatal
 501          * errors and it needs reset. Further more, the AIB interface
 502          * isn't reliable any more.
 503          */
 504         if (!(pe->type & EEH_PE_PHB) &&
 505             (option == EEH_RESET_HOT ||
 506             option == EEH_RESET_FUNDAMENTAL)) {
 507                 ret = ioda_eeh_pe_clear(pe);
 508                 if (ret)
 509                         return -EIO;
 510         }
 511
 512         /*
 513          * The rules applied to reset, either fundamental or hot reset:
 514          *
 515          * We always reset the direct upstream bridge of the PE. If the
 516          * direct upstream bridge isn't root bridge, we always take hot
 517          * reset no matter what option (fundamental or hot) is. Otherwise,
 518          * we should do the reset according to the required option.
 519          */
 520         if (pe->type & EEH_PE_PHB) {
 521                 ret = ioda_eeh_phb_reset(hose, option);
 522         } else {
 523                 if (pe->type & EEH_PE_DEVICE) {
 524                         /*
 525                          * If it's device PE, we didn't refer to the parent
 526                          * PCI bus yet. So we have to figure it out indirectly.
 527                          */
 528                         edev = list_first_entry(&pe->edevs,
 529                                         struct eeh_dev, list);
 530                         dev = eeh_dev_to_pci_dev(edev);
 531                         dev = dev->bus->self;
 532                 } else {
 533                         /*
 534                          * If it's bus PE, the parent PCI bus is already there
 535                          * and just pick it up.
 536                          */
 537                         dev = pe->bus->self;
 538                 }
 539
 540                 /*
 541                  * Do reset based on the fact that the direct upstream bridge
 542                  * is root bridge (port) or not.
 543                  */
 544                 if (dev->bus->number == 0)
 545                         ret = ioda_eeh_root_reset(hose, option);
 546                 else
 547                         ret = ioda_eeh_bridge_reset(hose, dev, option);
 548         }
 549
 550         return ret;
 551 }
 552
 553 /**
 554  * ioda_eeh_get_log - Retrieve error log
 555  * @pe: EEH PE
 556  * @severity: Severity level of the log
 557  * @drv_log: buffer to store the log
 558  * @len: space of the log buffer
 559  *
 560  * The function is used to retrieve error log from P7IOC.
 561  */
 562 static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
 563                             char *drv_log, unsigned long len)
 564 {
 565         s64 ret;
 566         unsigned long flags;
 567         struct pci_controller *hose = pe->phb;
 568         struct pnv_phb *phb = hose->private_data;
 569
 570         spin_lock_irqsave(&phb->lock, flags);
 571
 572         ret = opal_pci_get_phb_diag_data2(phb->opal_id,
 573                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
 574         if (ret) {
 575                 spin_unlock_irqrestore(&phb->lock, flags);
 576                 pr_warning("%s: Can't get log for PHB#%x-PE#%x (%lld)\n",
 577                            __func__, hose->global_number, pe->addr, ret);
 578                 return -EIO;
 579         }
 580
 581         /* The PHB diag-data is always indicative */
 582         pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
 583
 584         spin_unlock_irqrestore(&phb->lock, flags);
 585
 586         return 0;
 587 }
 588
 589 /**
 590  * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
 591  * @pe: EEH PE
 592  *
 593  * For particular PE, it might have included PCI bridges. In order
 594  * to make the PE work properly, those PCI bridges should be configured
 595  * correctly. However, we need do nothing on P7IOC since the reset
 596  * function will do everything that should be covered by the function.
 597  */
 598 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
 599 {
 600         return 0;
 601 }
 602
 603 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
 604 {
 605         /* GEM */
 606         pr_info("  GEM XFIR:        %016llx\n", data->gemXfir);
 607         pr_info("  GEM RFIR:        %016llx\n", data->gemRfir);
 608         pr_info("  GEM RIRQFIR:     %016llx\n", data->gemRirqfir);
 609         pr_info("  GEM Mask:        %016llx\n", data->gemMask);
 610         pr_info("  GEM RWOF:        %016llx\n", data->gemRwof);
 611
 612         /* LEM */
 613         pr_info("  LEM FIR:         %016llx\n", data->lemFir);
 614         pr_info("  LEM Error Mask:  %016llx\n", data->lemErrMask);
 615         pr_info("  LEM Action 0:    %016llx\n", data->lemAction0);
 616         pr_info("  LEM Action 1:    %016llx\n", data->lemAction1);
 617         pr_info("  LEM WOF:         %016llx\n", data->lemWof);
 618 }
 619
 620 static void ioda_eeh_hub_diag(struct pci_controller *hose)
 621 {
 622         struct pnv_phb *phb = hose->private_data;
 623         struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
 624         long rc;
 625
 626         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
 627         if (rc != OPAL_SUCCESS) {
 628                 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
 629                            __func__, phb->hub_id, rc);
 630                 return;
 631         }
 632
 633         switch (data->type) {
 634         case OPAL_P7IOC_DIAG_TYPE_RGC:
 635                 pr_info("P7IOC diag-data for RGC\n\n");
 636                 ioda_eeh_hub_diag_common(data);
 637                 pr_info("  RGC Status:      %016llx\n", data->rgc.rgcStatus);
 638                 pr_info("  RGC LDCP:        %016llx\n", data->rgc.rgcLdcp);
 639                 break;
 640         case OPAL_P7IOC_DIAG_TYPE_BI:
 641                 pr_info("P7IOC diag-data for BI %s\n\n",
 642                         data->bi.biDownbound ? "Downbound" : "Upbound");
 643                 ioda_eeh_hub_diag_common(data);
 644                 pr_info("  BI LDCP 0:       %016llx\n", data->bi.biLdcp0);
 645                 pr_info("  BI LDCP 1:       %016llx\n", data->bi.biLdcp1);
 646                 pr_info("  BI LDCP 2:       %016llx\n", data->bi.biLdcp2);
 647                 pr_info("  BI Fence Status: %016llx\n", data->bi.biFenceStatus);
 648                 break;
 649         case OPAL_P7IOC_DIAG_TYPE_CI:
 650                 pr_info("P7IOC diag-data for CI Port %d\\nn",
 651                         data->ci.ciPort);
 652                 ioda_eeh_hub_diag_common(data);
 653                 pr_info("  CI Port Status:  %016llx\n", data->ci.ciPortStatus);
 654                 pr_info("  CI Port LDCP:    %016llx\n", data->ci.ciPortLdcp);
 655                 break;
 656         case OPAL_P7IOC_DIAG_TYPE_MISC:
 657                 pr_info("P7IOC diag-data for MISC\n\n");
 658                 ioda_eeh_hub_diag_common(data);
 659                 break;
 660         case OPAL_P7IOC_DIAG_TYPE_I2C:
 661                 pr_info("P7IOC diag-data for I2C\n\n");
 662                 ioda_eeh_hub_diag_common(data);
 663                 break;
 664         default:
 665                 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
 666                            __func__, phb->hub_id, data->type);
 667         }
 668 }
 669
 670 static void ioda_eeh_phb_diag(struct pci_controller *hose)
 671 {
 672         struct pnv_phb *phb = hose->private_data;
 673         long rc;
 674
 675         rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
 676                                          PNV_PCI_DIAG_BUF_SIZE);
 677         if (rc != OPAL_SUCCESS) {
 678                 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
 679                             __func__, hose->global_number, rc);
 680                 return;
 681         }
 682
 683         pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
 684 }
 685
 686 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
 687                                struct eeh_pe **pe)
 688 {
 689         struct eeh_pe *phb_pe;
 690
 691         phb_pe = eeh_phb_pe_get(hose);
 692         if (!phb_pe) {
 693                 pr_warning("%s Can't find PE for PHB#%d\n",
 694                            __func__, hose->global_number);
 695                 return -EEXIST;
 696         }
 697
 698         *pe = phb_pe;
 699         return 0;
 700 }
 701
 702 static int ioda_eeh_get_pe(struct pci_controller *hose,
 703                            u16 pe_no, struct eeh_pe **pe)
 704 {
 705         struct eeh_pe *phb_pe, *dev_pe;
 706         struct eeh_dev dev;
 707
 708         /* Find the PHB PE */
 709         if (ioda_eeh_get_phb_pe(hose, &phb_pe))
 710                 return -EEXIST;
 711
 712         /* Find the PE according to PE# */
 713         memset(&dev, 0, sizeof(struct eeh_dev));
 714         dev.phb = hose;
 715         dev.pe_config_addr = pe_no;
 716         dev_pe = eeh_pe_get(&dev);
 717         if (!dev_pe) {
 718                 pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
 719                            __func__, hose->global_number, pe_no);
 720                 return -EEXIST;
 721         }
 722
 723         *pe = dev_pe;
 724         return 0;
 725 }
 726
 727 /**
 728  * ioda_eeh_next_error - Retrieve next error for EEH core to handle
 729  * @pe: The affected PE
 730  *
 731  * The function is expected to be called by EEH core while it gets
 732  * special EEH event (without binding PE). The function calls to
 733  * OPAL APIs for next error to handle. The informational error is
 734  * handled internally by platform. However, the dead IOC, dead PHB,
 735  * fenced PHB and frozen PE should be handled by EEH core eventually.
 736  */
 737 static int ioda_eeh_next_error(struct eeh_pe **pe)
 738 {
 739         struct pci_controller *hose, *tmp;
 740         struct pnv_phb *phb;
 741         u64 frozen_pe_no;
 742         u16 err_type, severity;
 743         long rc;
 744         int ret = 1;
 745
 746         /*
 747          * While running here, it's safe to purge the event queue.
 748          * And we should keep the cached OPAL notifier event sychronized
 749          * between the kernel and firmware.
 750          */
 751         eeh_remove_event(NULL);
 752         opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
 753
 754         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 755                 /*
 756                  * If the subordinate PCI buses of the PHB has been
 757                  * removed, we needn't take care of it any more.
 758                  */
 759                 phb = hose->private_data;
 760                 if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
 761                         continue;
 762
 763                 rc = opal_pci_next_error(phb->opal_id,
 764                                 &frozen_pe_no, &err_type, &severity);
 765
 766                 /* If OPAL API returns error, we needn't proceed */
 767                 if (rc != OPAL_SUCCESS) {
 768                         pr_devel("%s: Invalid return value on "
 769                                  "PHB#%x (0x%lx) from opal_pci_next_error",
 770                                  __func__, hose->global_number, rc);
 771                         continue;
 772                 }
 773
 774                 /* If the PHB doesn't have error, stop processing */
 775                 if (err_type == OPAL_EEH_NO_ERROR ||
 776                     severity == OPAL_EEH_SEV_NO_ERROR) {
 777                         pr_devel("%s: No error found on PHB#%x\n",
 778                                  __func__, hose->global_number);
 779                         continue;
 780                 }
 781
 782                 /*
 783                  * Processing the error. We're expecting the error with
 784                  * highest priority reported upon multiple errors on the
 785                  * specific PHB.
 786                  */
 787                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
 788                          __func__, err_type, severity,
 789                          frozen_pe_no, hose->global_number);
 790                 switch (err_type) {
 791                 case OPAL_EEH_IOC_ERROR:
 792                         if (severity == OPAL_EEH_SEV_IOC_DEAD) {
 793                                 list_for_each_entry_safe(hose, tmp,
 794                                                 &hose_list, list_node) {
 795                                         phb = hose->private_data;
 796                                         phb->eeh_state |= PNV_EEH_STATE_REMOVED;
 797                                 }
 798
 799                                 pr_err("EEH: dead IOC detected\n");
 800                                 ret = 4;
 801                                 goto out;
 802                         } else if (severity == OPAL_EEH_SEV_INF) {
 803                                 pr_info("EEH: IOC informative error "
 804                                         "detected\n");
 805                                 ioda_eeh_hub_diag(hose);
 806                         }
 807
 808                         break;
 809                 case OPAL_EEH_PHB_ERROR:
 810                         if (severity == OPAL_EEH_SEV_PHB_DEAD) {
 811                                 if (ioda_eeh_get_phb_pe(hose, pe))
 812                                         break;
 813
 814                                 pr_err("EEH: dead PHB#%x detected\n",
 815                                         hose->global_number);
 816                                 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
 817                                 ret = 3;
 818                                 goto out;
 819                         } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
 820                                 if (ioda_eeh_get_phb_pe(hose, pe))
 821                                         break;
 822
 823                                 pr_err("EEH: fenced PHB#%x detected\n",
 824                                         hose->global_number);
 825                                 ret = 2;
 826                                 goto out;
 827                         } else if (severity == OPAL_EEH_SEV_INF) {
 828                                 pr_info("EEH: PHB#%x informative error "
 829                                         "detected\n",
 830                                         hose->global_number);
 831                                 ioda_eeh_phb_diag(hose);
 832                         }
 833
 834                         break;
 835                 case OPAL_EEH_PE_ERROR:
 836                         if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
 837                                 break;
 838
 839                         pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
 840                                 (*pe)->addr, (*pe)->phb->global_number);
 841                         ret = 1;
 842                         goto out;
 843                 }
 844         }
 845
 846         ret = 0;
 847 out:
 848         return ret;
 849 }
 850
 851 struct pnv_eeh_ops ioda_eeh_ops = {
 852         .post_init              = ioda_eeh_post_init,
 853         .set_option             = ioda_eeh_set_option,
 854         .get_state              = ioda_eeh_get_state,
 855         .reset                  = ioda_eeh_reset,
 856         .get_log                = ioda_eeh_get_log,
 857         .configure_bridge       = ioda_eeh_configure_bridge,
 858         .next_error             = ioda_eeh_next_error
 859 };