arch/powerpc/platforms/powernv/eeh-ioda.c

   1 /*
   2  * The file intends to implement the functions needed by EEH, which is
   3  * built on IODA compliant chip. Actually, lots of functions related
   4  * to EEH would be built based on the OPAL APIs.
   5  *
   6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/bootmem.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/kernel.h>
  21 #include <linux/msi.h>
  22 #include <linux/notifier.h>
  23 #include <linux/pci.h>
  24 #include <linux/string.h>
  25
  26 #include <asm/eeh.h>
  27 #include <asm/eeh_event.h>
  28 #include <asm/io.h>
  29 #include <asm/iommu.h>
  30 #include <asm/msi_bitmap.h>
  31 #include <asm/opal.h>
  32 #include <asm/pci-bridge.h>
  33 #include <asm/ppc-pci.h>
  34 #include <asm/tce.h>
  35
  36 #include "powernv.h"
  37 #include "pci.h"
  38
  39 static char *hub_diag = NULL;
  40 static int ioda_eeh_nb_init = 0;
  41
  42 static int ioda_eeh_event(struct notifier_block *nb,
  43                           unsigned long events, void *change)
  44 {
  45         uint64_t changed_evts = (uint64_t)change;
  46
  47         /* We simply send special EEH event */
  48         if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
  49             (events & OPAL_EVENT_PCI_ERROR))
  50                 eeh_send_failure_event(NULL);
  51
  52         return 0;
  53 }
  54
  55 static struct notifier_block ioda_eeh_nb = {
  56         .notifier_call  = ioda_eeh_event,
  57         .next           = NULL,
  58         .priority       = 0
  59 };
  60
  61 #ifdef CONFIG_DEBUG_FS
  62 static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val)
  63 {
  64         struct pci_controller *hose = data;
  65         struct pnv_phb *phb = hose->private_data;
  66
  67         out_be64(phb->regs + offset, val);
  68         return 0;
  69 }
  70
  71 static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val)
  72 {
  73         struct pci_controller *hose = data;
  74         struct pnv_phb *phb = hose->private_data;
  75
  76         *val = in_be64(phb->regs + offset);
  77         return 0;
  78 }
  79
  80 static int ioda_eeh_outb_dbgfs_set(void *data, u64 val)
  81 {
  82         return ioda_eeh_dbgfs_set(data, 0xD10, val);
  83 }
  84
  85 static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val)
  86 {
  87         return ioda_eeh_dbgfs_get(data, 0xD10, val);
  88 }
  89
  90 static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val)
  91 {
  92         return ioda_eeh_dbgfs_set(data, 0xD90, val);
  93 }
  94
  95 static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val)
  96 {
  97         return ioda_eeh_dbgfs_get(data, 0xD90, val);
  98 }
  99
 100 static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val)
 101 {
 102         return ioda_eeh_dbgfs_set(data, 0xE10, val);
 103 }
 104
 105 static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val)
 106 {
 107         return ioda_eeh_dbgfs_get(data, 0xE10, val);
 108 }
 109
 110 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get,
 111                         ioda_eeh_outb_dbgfs_set, "0x%llx\n");
 112 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get,
 113                         ioda_eeh_inbA_dbgfs_set, "0x%llx\n");
 114 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get,
 115                         ioda_eeh_inbB_dbgfs_set, "0x%llx\n");
 116 #endif /* CONFIG_DEBUG_FS */
 117
 118 /**
 119  * ioda_eeh_post_init - Chip dependent post initialization
 120  * @hose: PCI controller
 121  *
 122  * The function will be called after eeh PEs and devices
 123  * have been built. That means the EEH is ready to supply
 124  * service with I/O cache.
 125  */
 126 static int ioda_eeh_post_init(struct pci_controller *hose)
 127 {
 128         struct pnv_phb *phb = hose->private_data;
 129         int ret;
 130
 131         /* Register OPAL event notifier */
 132         if (!ioda_eeh_nb_init) {
 133                 ret = opal_notifier_register(&ioda_eeh_nb);
 134                 if (ret) {
 135                         pr_err("%s: Can't register OPAL event notifier (%d)\n",
 136                                __func__, ret);
 137                         return ret;
 138                 }
 139
 140                 ioda_eeh_nb_init = 1;
 141         }
 142
 143         /* We needn't HUB diag-data on PHB3 */
 144         if (phb->type == PNV_PHB_IODA1 && !hub_diag) {
 145                 hub_diag = (char *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
 146                 if (!hub_diag) {
 147                         pr_err("%s: Out of memory !\n", __func__);
 148                         return -ENOMEM;
 149                 }
 150         }
 151
 152 #ifdef CONFIG_DEBUG_FS
 153         if (phb->dbgfs) {
 154                 debugfs_create_file("err_injct_outbound", 0600,
 155                                     phb->dbgfs, hose,
 156                                     &ioda_eeh_outb_dbgfs_ops);
 157                 debugfs_create_file("err_injct_inboundA", 0600,
 158                                     phb->dbgfs, hose,
 159                                     &ioda_eeh_inbA_dbgfs_ops);
 160                 debugfs_create_file("err_injct_inboundB", 0600,
 161                                     phb->dbgfs, hose,
 162                                     &ioda_eeh_inbB_dbgfs_ops);
 163         }
 164 #endif
 165
 166         phb->eeh_state |= PNV_EEH_STATE_ENABLED;
 167
 168         return 0;
 169 }
 170
 171 /**
 172  * ioda_eeh_set_option - Set EEH operation or I/O setting
 173  * @pe: EEH PE
 174  * @option: options
 175  *
 176  * Enable or disable EEH option for the indicated PE. The
 177  * function also can be used to enable I/O or DMA for the
 178  * PE.
 179  */
 180 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
 181 {
 182         s64 ret;
 183         u32 pe_no;
 184         struct pci_controller *hose = pe->phb;
 185         struct pnv_phb *phb = hose->private_data;
 186
 187         /* Check on PE number */
 188         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 189                 pr_err("%s: PE address %x out of range [0, %x] "
 190                        "on PHB#%x\n",
 191                         __func__, pe->addr, phb->ioda.total_pe,
 192                         hose->global_number);
 193                 return -EINVAL;
 194         }
 195
 196         pe_no = pe->addr;
 197         switch (option) {
 198         case EEH_OPT_DISABLE:
 199                 ret = -EEXIST;
 200                 break;
 201         case EEH_OPT_ENABLE:
 202                 ret = 0;
 203                 break;
 204         case EEH_OPT_THAW_MMIO:
 205                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 206                                 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
 207                 if (ret) {
 208                         pr_warning("%s: Failed to enable MMIO for "
 209                                    "PHB#%x-PE#%x, err=%lld\n",
 210                                 __func__, hose->global_number, pe_no, ret);
 211                         return -EIO;
 212                 }
 213
 214                 break;
 215         case EEH_OPT_THAW_DMA:
 216                 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
 217                                 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
 218                 if (ret) {
 219                         pr_warning("%s: Failed to enable DMA for "
 220                                    "PHB#%x-PE#%x, err=%lld\n",
 221                                 __func__, hose->global_number, pe_no, ret);
 222                         return -EIO;
 223                 }
 224
 225                 break;
 226         default:
 227                 pr_warning("%s: Invalid option %d\n", __func__, option);
 228                 return -EINVAL;
 229         }
 230
 231         return ret;
 232 }
 233
 234 /**
 235  * ioda_eeh_get_state - Retrieve the state of PE
 236  * @pe: EEH PE
 237  *
 238  * The PE's state should be retrieved from the PEEV, PEST
 239  * IODA tables. Since the OPAL has exported the function
 240  * to do it, it'd better to use that.
 241  */
 242 static int ioda_eeh_get_state(struct eeh_pe *pe)
 243 {
 244         s64 ret = 0;
 245         u8 fstate;
 246         u16 pcierr;
 247         u32 pe_no;
 248         int result;
 249         struct pci_controller *hose = pe->phb;
 250         struct pnv_phb *phb = hose->private_data;
 251
 252         /*
 253          * Sanity check on PE address. The PHB PE address should
 254          * be zero.
 255          */
 256         if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
 257                 pr_err("%s: PE address %x out of range [0, %x] "
 258                        "on PHB#%x\n",
 259                        __func__, pe->addr, phb->ioda.total_pe,
 260                        hose->global_number);
 261                 return EEH_STATE_NOT_SUPPORT;
 262         }
 263
 264         /* Retrieve PE status through OPAL */
 265         pe_no = pe->addr;
 266         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 267                         &fstate, &pcierr, NULL);
 268         if (ret) {
 269                 pr_err("%s: Failed to get EEH status on "
 270                        "PHB#%x-PE#%x\n, err=%lld\n",
 271                        __func__, hose->global_number, pe_no, ret);
 272                 return EEH_STATE_NOT_SUPPORT;
 273         }
 274
 275         /* Check PHB status */
 276         if (pe->type & EEH_PE_PHB) {
 277                 result = 0;
 278                 result &= ~EEH_STATE_RESET_ACTIVE;
 279
 280                 if (pcierr != OPAL_EEH_PHB_ERROR) {
 281                         result |= EEH_STATE_MMIO_ACTIVE;
 282                         result |= EEH_STATE_DMA_ACTIVE;
 283                         result |= EEH_STATE_MMIO_ENABLED;
 284                         result |= EEH_STATE_DMA_ENABLED;
 285                 }
 286
 287                 return result;
 288         }
 289
 290         /* Parse result out */
 291         result = 0;
 292         switch (fstate) {
 293         case OPAL_EEH_STOPPED_NOT_FROZEN:
 294                 result &= ~EEH_STATE_RESET_ACTIVE;
 295                 result |= EEH_STATE_MMIO_ACTIVE;
 296                 result |= EEH_STATE_DMA_ACTIVE;
 297                 result |= EEH_STATE_MMIO_ENABLED;
 298                 result |= EEH_STATE_DMA_ENABLED;
 299                 break;
 300         case OPAL_EEH_STOPPED_MMIO_FREEZE:
 301                 result &= ~EEH_STATE_RESET_ACTIVE;
 302                 result |= EEH_STATE_DMA_ACTIVE;
 303                 result |= EEH_STATE_DMA_ENABLED;
 304                 break;
 305         case OPAL_EEH_STOPPED_DMA_FREEZE:
 306                 result &= ~EEH_STATE_RESET_ACTIVE;
 307                 result |= EEH_STATE_MMIO_ACTIVE;
 308                 result |= EEH_STATE_MMIO_ENABLED;
 309                 break;
 310         case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
 311                 result &= ~EEH_STATE_RESET_ACTIVE;
 312                 break;
 313         case OPAL_EEH_STOPPED_RESET:
 314                 result |= EEH_STATE_RESET_ACTIVE;
 315                 break;
 316         case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
 317                 result |= EEH_STATE_UNAVAILABLE;
 318                 break;
 319         case OPAL_EEH_STOPPED_PERM_UNAVAIL:
 320                 result |= EEH_STATE_NOT_SUPPORT;
 321                 break;
 322         default:
 323                 pr_warning("%s: Unexpected EEH status 0x%x "
 324                            "on PHB#%x-PE#%x\n",
 325                            __func__, fstate, hose->global_number, pe_no);
 326         }
 327
 328         return result;
 329 }
 330
 331 static int ioda_eeh_pe_clear(struct eeh_pe *pe)
 332 {
 333         struct pci_controller *hose;
 334         struct pnv_phb *phb;
 335         u32 pe_no;
 336         u8 fstate;
 337         u16 pcierr;
 338         s64 ret;
 339
 340         pe_no = pe->addr;
 341         hose = pe->phb;
 342         phb = pe->phb->private_data;
 343
 344         /* Clear the EEH error on the PE */
 345         ret = opal_pci_eeh_freeze_clear(phb->opal_id,
 346                         pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 347         if (ret) {
 348                 pr_err("%s: Failed to clear EEH error for "
 349                        "PHB#%x-PE#%x, err=%lld\n",
 350                        __func__, hose->global_number, pe_no, ret);
 351                 return -EIO;
 352         }
 353
 354         /*
 355          * Read the PE state back and verify that the frozen
 356          * state has been removed.
 357          */
 358         ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 359                         &fstate, &pcierr, NULL);
 360         if (ret) {
 361                 pr_err("%s: Failed to get EEH status on "
 362                        "PHB#%x-PE#%x\n, err=%lld\n",
 363                        __func__, hose->global_number, pe_no, ret);
 364                 return -EIO;
 365         }
 366
 367         if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
 368                 pr_err("%s: Frozen state not cleared on "
 369                        "PHB#%x-PE#%x, sts=%x\n",
 370                        __func__, hose->global_number, pe_no, fstate);
 371                 return -EIO;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
 378 {
 379         s64 rc = OPAL_HARDWARE;
 380
 381         while (1) {
 382                 rc = opal_pci_poll(phb->opal_id);
 383                 if (rc <= 0)
 384                         break;
 385
 386                 msleep(rc);
 387         }
 388
 389         return rc;
 390 }
 391
 392 static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
 393 {
 394         struct pnv_phb *phb = hose->private_data;
 395         s64 rc = OPAL_HARDWARE;
 396
 397         pr_debug("%s: Reset PHB#%x, option=%d\n",
 398                  __func__, hose->global_number, option);
 399
 400         /* Issue PHB complete reset request */
 401         if (option == EEH_RESET_FUNDAMENTAL ||
 402             option == EEH_RESET_HOT)
 403                 rc = opal_pci_reset(phb->opal_id,
 404                                 OPAL_PHB_COMPLETE,
 405                                 OPAL_ASSERT_RESET);
 406         else if (option == EEH_RESET_DEACTIVATE)
 407                 rc = opal_pci_reset(phb->opal_id,
 408                                 OPAL_PHB_COMPLETE,
 409                                 OPAL_DEASSERT_RESET);
 410         if (rc < 0)
 411                 goto out;
 412
 413         /*
 414          * Poll state of the PHB until the request is done
 415          * successfully.
 416          */
 417         rc = ioda_eeh_phb_poll(phb);
 418 out:
 419         if (rc != OPAL_SUCCESS)
 420                 return -EIO;
 421
 422         return 0;
 423 }
 424
 425 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
 426 {
 427         struct pnv_phb *phb = hose->private_data;
 428         s64 rc = OPAL_SUCCESS;
 429
 430         pr_debug("%s: Reset PHB#%x, option=%d\n",
 431                  __func__, hose->global_number, option);
 432
 433         /*
 434          * During the reset deassert time, we needn't care
 435          * the reset scope because the firmware does nothing
 436          * for fundamental or hot reset during deassert phase.
 437          */
 438         if (option == EEH_RESET_FUNDAMENTAL)
 439                 rc = opal_pci_reset(phb->opal_id,
 440                                 OPAL_PCI_FUNDAMENTAL_RESET,
 441                                 OPAL_ASSERT_RESET);
 442         else if (option == EEH_RESET_HOT)
 443                 rc = opal_pci_reset(phb->opal_id,
 444                                 OPAL_PCI_HOT_RESET,
 445                                 OPAL_ASSERT_RESET);
 446         else if (option == EEH_RESET_DEACTIVATE)
 447                 rc = opal_pci_reset(phb->opal_id,
 448                                 OPAL_PCI_HOT_RESET,
 449                                 OPAL_DEASSERT_RESET);
 450         if (rc < 0)
 451                 goto out;
 452
 453         /* Poll state of the PHB until the request is done */
 454         rc = ioda_eeh_phb_poll(phb);
 455 out:
 456         if (rc != OPAL_SUCCESS)
 457                 return -EIO;
 458
 459         return 0;
 460 }
 461
 462 static int ioda_eeh_bridge_reset(struct pci_controller *hose,
 463                 struct pci_dev *dev, int option)
 464 {
 465         u16 ctrl;
 466
 467         pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
 468                  __func__, hose->global_number, dev->bus->number,
 469                  PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
 470
 471         switch (option) {
 472         case EEH_RESET_FUNDAMENTAL:
 473         case EEH_RESET_HOT:
 474                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 475                 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
 476                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 477                 break;
 478         case EEH_RESET_DEACTIVATE:
 479                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
 480                 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 481                 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
 482                 break;
 483         }
 484
 485         return 0;
 486 }
 487
 488 /**
 489  * ioda_eeh_reset - Reset the indicated PE
 490  * @pe: EEH PE
 491  * @option: reset option
 492  *
 493  * Do reset on the indicated PE. For PCI bus sensitive PE,
 494  * we need to reset the parent p2p bridge. The PHB has to
 495  * be reinitialized if the p2p bridge is root bridge. For
 496  * PCI device sensitive PE, we will try to reset the device
 497  * through FLR. For now, we don't have OPAL APIs to do HARD
 498  * reset yet, so all reset would be SOFT (HOT) reset.
 499  */
 500 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
 501 {
 502         struct pci_controller *hose = pe->phb;
 503         struct eeh_dev *edev;
 504         struct pci_dev *dev;
 505         int ret;
 506
 507         /*
 508          * Anyway, we have to clear the problematic state for the
 509          * corresponding PE. However, we needn't do it if the PE
 510          * is PHB associated. That means the PHB is having fatal
 511          * errors and it needs reset. Further more, the AIB interface
 512          * isn't reliable any more.
 513          */
 514         if (!(pe->type & EEH_PE_PHB) &&
 515             (option == EEH_RESET_HOT ||
 516             option == EEH_RESET_FUNDAMENTAL)) {
 517                 ret = ioda_eeh_pe_clear(pe);
 518                 if (ret)
 519                         return -EIO;
 520         }
 521
 522         /*
 523          * The rules applied to reset, either fundamental or hot reset:
 524          *
 525          * We always reset the direct upstream bridge of the PE. If the
 526          * direct upstream bridge isn't root bridge, we always take hot
 527          * reset no matter what option (fundamental or hot) is. Otherwise,
 528          * we should do the reset according to the required option.
 529          */
 530         if (pe->type & EEH_PE_PHB) {
 531                 ret = ioda_eeh_phb_reset(hose, option);
 532         } else {
 533                 if (pe->type & EEH_PE_DEVICE) {
 534                         /*
 535                          * If it's device PE, we didn't refer to the parent
 536                          * PCI bus yet. So we have to figure it out indirectly.
 537                          */
 538                         edev = list_first_entry(&pe->edevs,
 539                                         struct eeh_dev, list);
 540                         dev = eeh_dev_to_pci_dev(edev);
 541                         dev = dev->bus->self;
 542                 } else {
 543                         /*
 544                          * If it's bus PE, the parent PCI bus is already there
 545                          * and just pick it up.
 546                          */
 547                         dev = pe->bus->self;
 548                 }
 549
 550                 /*
 551                  * Do reset based on the fact that the direct upstream bridge
 552                  * is root bridge (port) or not.
 553                  */
 554                 if (dev->bus->number == 0)
 555                         ret = ioda_eeh_root_reset(hose, option);
 556                 else
 557                         ret = ioda_eeh_bridge_reset(hose, dev, option);
 558         }
 559
 560         return ret;
 561 }
 562
 563 /**
 564  * ioda_eeh_get_log - Retrieve error log
 565  * @pe: EEH PE
 566  * @severity: Severity level of the log
 567  * @drv_log: buffer to store the log
 568  * @len: space of the log buffer
 569  *
 570  * The function is used to retrieve error log from P7IOC.
 571  */
 572 static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
 573                             char *drv_log, unsigned long len)
 574 {
 575         s64 ret;
 576         unsigned long flags;
 577         struct pci_controller *hose = pe->phb;
 578         struct pnv_phb *phb = hose->private_data;
 579
 580         spin_lock_irqsave(&phb->lock, flags);
 581
 582         ret = opal_pci_get_phb_diag_data2(phb->opal_id,
 583                         phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
 584         if (ret) {
 585                 spin_unlock_irqrestore(&phb->lock, flags);
 586                 pr_warning("%s: Can't get log for PHB#%x-PE#%x (%lld)\n",
 587                            __func__, hose->global_number, pe->addr, ret);
 588                 return -EIO;
 589         }
 590
 591         /*
 592          * FIXME: We probably need log the error in somewhere.
 593          * Lets make it up in future.
 594          */
 595         /* pr_info("%s", phb->diag.blob); */
 596
 597         spin_unlock_irqrestore(&phb->lock, flags);
 598
 599         return 0;
 600 }
 601
 602 /**
 603  * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
 604  * @pe: EEH PE
 605  *
 606  * For particular PE, it might have included PCI bridges. In order
 607  * to make the PE work properly, those PCI bridges should be configured
 608  * correctly. However, we need do nothing on P7IOC since the reset
 609  * function will do everything that should be covered by the function.
 610  */
 611 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
 612 {
 613         return 0;
 614 }
 615
 616 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
 617 {
 618         /* GEM */
 619         pr_info("  GEM XFIR:        %016llx\n", data->gemXfir);
 620         pr_info("  GEM RFIR:        %016llx\n", data->gemRfir);
 621         pr_info("  GEM RIRQFIR:     %016llx\n", data->gemRirqfir);
 622         pr_info("  GEM Mask:        %016llx\n", data->gemMask);
 623         pr_info("  GEM RWOF:        %016llx\n", data->gemRwof);
 624
 625         /* LEM */
 626         pr_info("  LEM FIR:         %016llx\n", data->lemFir);
 627         pr_info("  LEM Error Mask:  %016llx\n", data->lemErrMask);
 628         pr_info("  LEM Action 0:    %016llx\n", data->lemAction0);
 629         pr_info("  LEM Action 1:    %016llx\n", data->lemAction1);
 630         pr_info("  LEM WOF:         %016llx\n", data->lemWof);
 631 }
 632
 633 static void ioda_eeh_hub_diag(struct pci_controller *hose)
 634 {
 635         struct pnv_phb *phb = hose->private_data;
 636         struct OpalIoP7IOCErrorData *data;
 637         long rc;
 638
 639         data = (struct OpalIoP7IOCErrorData *)ioda_eeh_hub_diag;
 640         rc = opal_pci_get_hub_diag_data(phb->hub_id, data, PAGE_SIZE);
 641         if (rc != OPAL_SUCCESS) {
 642                 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
 643                            __func__, phb->hub_id, rc);
 644                 return;
 645         }
 646
 647         switch (data->type) {
 648         case OPAL_P7IOC_DIAG_TYPE_RGC:
 649                 pr_info("P7IOC diag-data for RGC\n\n");
 650                 ioda_eeh_hub_diag_common(data);
 651                 pr_info("  RGC Status:      %016llx\n", data->rgc.rgcStatus);
 652                 pr_info("  RGC LDCP:        %016llx\n", data->rgc.rgcLdcp);
 653                 break;
 654         case OPAL_P7IOC_DIAG_TYPE_BI:
 655                 pr_info("P7IOC diag-data for BI %s\n\n",
 656                         data->bi.biDownbound ? "Downbound" : "Upbound");
 657                 ioda_eeh_hub_diag_common(data);
 658                 pr_info("  BI LDCP 0:       %016llx\n", data->bi.biLdcp0);
 659                 pr_info("  BI LDCP 1:       %016llx\n", data->bi.biLdcp1);
 660                 pr_info("  BI LDCP 2:       %016llx\n", data->bi.biLdcp2);
 661                 pr_info("  BI Fence Status: %016llx\n", data->bi.biFenceStatus);
 662                 break;
 663         case OPAL_P7IOC_DIAG_TYPE_CI:
 664                 pr_info("P7IOC diag-data for CI Port %d\\nn",
 665                         data->ci.ciPort);
 666                 ioda_eeh_hub_diag_common(data);
 667                 pr_info("  CI Port Status:  %016llx\n", data->ci.ciPortStatus);
 668                 pr_info("  CI Port LDCP:    %016llx\n", data->ci.ciPortLdcp);
 669                 break;
 670         case OPAL_P7IOC_DIAG_TYPE_MISC:
 671                 pr_info("P7IOC diag-data for MISC\n\n");
 672                 ioda_eeh_hub_diag_common(data);
 673                 break;
 674         case OPAL_P7IOC_DIAG_TYPE_I2C:
 675                 pr_info("P7IOC diag-data for I2C\n\n");
 676                 ioda_eeh_hub_diag_common(data);
 677                 break;
 678         default:
 679                 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
 680                            __func__, phb->hub_id, data->type);
 681         }
 682 }
 683
 684 static void ioda_eeh_phb_diag(struct pci_controller *hose)
 685 {
 686         struct pnv_phb *phb = hose->private_data;
 687         long rc;
 688
 689         rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
 690                                          PNV_PCI_DIAG_BUF_SIZE);
 691         if (rc != OPAL_SUCCESS) {
 692                 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
 693                             __func__, hose->global_number, rc);
 694                 return;
 695         }
 696
 697         pnv_pci_dump_phb_diag_data(hose, phb->diag.blob);
 698 }
 699
 700 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
 701                                struct eeh_pe **pe)
 702 {
 703         struct eeh_pe *phb_pe;
 704
 705         phb_pe = eeh_phb_pe_get(hose);
 706         if (!phb_pe) {
 707                 pr_warning("%s Can't find PE for PHB#%d\n",
 708                            __func__, hose->global_number);
 709                 return -EEXIST;
 710         }
 711
 712         *pe = phb_pe;
 713         return 0;
 714 }
 715
 716 static int ioda_eeh_get_pe(struct pci_controller *hose,
 717                            u16 pe_no, struct eeh_pe **pe)
 718 {
 719         struct eeh_pe *phb_pe, *dev_pe;
 720         struct eeh_dev dev;
 721
 722         /* Find the PHB PE */
 723         if (ioda_eeh_get_phb_pe(hose, &phb_pe))
 724                 return -EEXIST;
 725
 726         /* Find the PE according to PE# */
 727         memset(&dev, 0, sizeof(struct eeh_dev));
 728         dev.phb = hose;
 729         dev.pe_config_addr = pe_no;
 730         dev_pe = eeh_pe_get(&dev);
 731         if (!dev_pe) {
 732                 pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
 733                            __func__, hose->global_number, pe_no);
 734                 return -EEXIST;
 735         }
 736
 737         *pe = dev_pe;
 738         return 0;
 739 }
 740
 741 /**
 742  * ioda_eeh_next_error - Retrieve next error for EEH core to handle
 743  * @pe: The affected PE
 744  *
 745  * The function is expected to be called by EEH core while it gets
 746  * special EEH event (without binding PE). The function calls to
 747  * OPAL APIs for next error to handle. The informational error is
 748  * handled internally by platform. However, the dead IOC, dead PHB,
 749  * fenced PHB and frozen PE should be handled by EEH core eventually.
 750  */
 751 static int ioda_eeh_next_error(struct eeh_pe **pe)
 752 {
 753         struct pci_controller *hose, *tmp;
 754         struct pnv_phb *phb;
 755         u64 frozen_pe_no;
 756         u16 err_type, severity;
 757         long rc;
 758         int ret = 1;
 759
 760         /*
 761          * While running here, it's safe to purge the event queue.
 762          * And we should keep the cached OPAL notifier event sychronized
 763          * between the kernel and firmware.
 764          */
 765         eeh_remove_event(NULL);
 766         opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
 767
 768         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 769                 /*
 770                  * If the subordinate PCI buses of the PHB has been
 771                  * removed, we needn't take care of it any more.
 772                  */
 773                 phb = hose->private_data;
 774                 if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
 775                         continue;
 776
 777                 rc = opal_pci_next_error(phb->opal_id,
 778                                 &frozen_pe_no, &err_type, &severity);
 779
 780                 /* If OPAL API returns error, we needn't proceed */
 781                 if (rc != OPAL_SUCCESS) {
 782                         pr_devel("%s: Invalid return value on "
 783                                  "PHB#%x (0x%lx) from opal_pci_next_error",
 784                                  __func__, hose->global_number, rc);
 785                         continue;
 786                 }
 787
 788                 /* If the PHB doesn't have error, stop processing */
 789                 if (err_type == OPAL_EEH_NO_ERROR ||
 790                     severity == OPAL_EEH_SEV_NO_ERROR) {
 791                         pr_devel("%s: No error found on PHB#%x\n",
 792                                  __func__, hose->global_number);
 793                         continue;
 794                 }
 795
 796                 /*
 797                  * Processing the error. We're expecting the error with
 798                  * highest priority reported upon multiple errors on the
 799                  * specific PHB.
 800                  */
 801                 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
 802                          __func__, err_type, severity,
 803                          frozen_pe_no, hose->global_number);
 804                 switch (err_type) {
 805                 case OPAL_EEH_IOC_ERROR:
 806                         if (severity == OPAL_EEH_SEV_IOC_DEAD) {
 807                                 list_for_each_entry_safe(hose, tmp,
 808                                                 &hose_list, list_node) {
 809                                         phb = hose->private_data;
 810                                         phb->eeh_state |= PNV_EEH_STATE_REMOVED;
 811                                 }
 812
 813                                 pr_err("EEH: dead IOC detected\n");
 814                                 ret = 4;
 815                                 goto out;
 816                         } else if (severity == OPAL_EEH_SEV_INF) {
 817                                 pr_info("EEH: IOC informative error "
 818                                         "detected\n");
 819                                 ioda_eeh_hub_diag(hose);
 820                         }
 821
 822                         break;
 823                 case OPAL_EEH_PHB_ERROR:
 824                         if (severity == OPAL_EEH_SEV_PHB_DEAD) {
 825                                 if (ioda_eeh_get_phb_pe(hose, pe))
 826                                         break;
 827
 828                                 pr_err("EEH: dead PHB#%x detected\n",
 829                                         hose->global_number);
 830                                 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
 831                                 ret = 3;
 832                                 goto out;
 833                         } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
 834                                 if (ioda_eeh_get_phb_pe(hose, pe))
 835                                         break;
 836
 837                                 pr_err("EEH: fenced PHB#%x detected\n",
 838                                         hose->global_number);
 839                                 ret = 2;
 840                                 goto out;
 841                         } else if (severity == OPAL_EEH_SEV_INF) {
 842                                 pr_info("EEH: PHB#%x informative error "
 843                                         "detected\n",
 844                                         hose->global_number);
 845                                 ioda_eeh_phb_diag(hose);
 846                         }
 847
 848                         break;
 849                 case OPAL_EEH_PE_ERROR:
 850                         if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
 851                                 break;
 852
 853                         pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
 854                                 (*pe)->addr, (*pe)->phb->global_number);
 855                         ret = 1;
 856                         goto out;
 857                 }
 858         }
 859
 860         ret = 0;
 861 out:
 862         return ret;
 863 }
 864
 865 struct pnv_eeh_ops ioda_eeh_ops = {
 866         .post_init              = ioda_eeh_post_init,
 867         .set_option             = ioda_eeh_set_option,
 868         .get_state              = ioda_eeh_get_state,
 869         .reset                  = ioda_eeh_reset,
 870         .get_log                = ioda_eeh_get_log,
 871         .configure_bridge       = ioda_eeh_configure_bridge,
 872         .next_error             = ioda_eeh_next_error
 873 };