2 * The file intends to implement the functions needed by EEH, which is
3 * built on IODA compliant chip. Actually, lots of functions related
4 * to EEH would be built based on the OPAL APIs.
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/bootmem.h>
15 #include <linux/debugfs.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/kernel.h>
21 #include <linux/msi.h>
22 #include <linux/notifier.h>
23 #include <linux/pci.h>
24 #include <linux/string.h>
27 #include <asm/eeh_event.h>
29 #include <asm/iommu.h>
30 #include <asm/msi_bitmap.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/ppc-pci.h>
39 static char *hub_diag = NULL;
40 static int ioda_eeh_nb_init = 0;
42 static int ioda_eeh_event(struct notifier_block *nb,
43 unsigned long events, void *change)
45 uint64_t changed_evts = (uint64_t)change;
47 /* We simply send special EEH event */
48 if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
49 (events & OPAL_EVENT_PCI_ERROR))
50 eeh_send_failure_event(NULL);
55 static struct notifier_block ioda_eeh_nb = {
56 .notifier_call = ioda_eeh_event,
61 #ifdef CONFIG_DEBUG_FS
62 static int ioda_eeh_dbgfs_set(void *data, u64 val)
64 struct pci_controller *hose = data;
65 struct pnv_phb *phb = hose->private_data;
67 out_be64(phb->regs + 0xD10, val);
71 static int ioda_eeh_dbgfs_get(void *data, u64 *val)
73 struct pci_controller *hose = data;
74 struct pnv_phb *phb = hose->private_data;
76 *val = in_be64(phb->regs + 0xD10);
80 DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_dbgfs_ops, ioda_eeh_dbgfs_get,
81 ioda_eeh_dbgfs_set, "0x%llx\n");
82 #endif /* CONFIG_DEBUG_FS */
85 * ioda_eeh_post_init - Chip dependent post initialization
86 * @hose: PCI controller
88 * The function will be called after eeh PEs and devices
89 * have been built. That means the EEH is ready to supply
90 * service with I/O cache.
92 static int ioda_eeh_post_init(struct pci_controller *hose)
94 struct pnv_phb *phb = hose->private_data;
97 /* Register OPAL event notifier */
98 if (!ioda_eeh_nb_init) {
99 ret = opal_notifier_register(&ioda_eeh_nb);
101 pr_err("%s: Can't register OPAL event notifier (%d)\n",
106 ioda_eeh_nb_init = 1;
109 /* FIXME: Enable it for PHB3 later */
110 if (phb->type == PNV_PHB_IODA1) {
112 hub_diag = (char *)__get_free_page(GFP_KERNEL |
115 pr_err("%s: Out of memory !\n",
121 #ifdef CONFIG_DEBUG_FS
123 debugfs_create_file("err_injct", 0600,
125 &ioda_eeh_dbgfs_ops);
128 phb->eeh_state |= PNV_EEH_STATE_ENABLED;
135 * ioda_eeh_set_option - Set EEH operation or I/O setting
139 * Enable or disable EEH option for the indicated PE. The
140 * function also can be used to enable I/O or DMA for the
143 static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
147 struct pci_controller *hose = pe->phb;
148 struct pnv_phb *phb = hose->private_data;
150 /* Check on PE number */
151 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
152 pr_err("%s: PE address %x out of range [0, %x] "
154 __func__, pe->addr, phb->ioda.total_pe,
155 hose->global_number);
161 case EEH_OPT_DISABLE:
167 case EEH_OPT_THAW_MMIO:
168 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
169 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
171 pr_warning("%s: Failed to enable MMIO for "
172 "PHB#%x-PE#%x, err=%lld\n",
173 __func__, hose->global_number, pe_no, ret);
178 case EEH_OPT_THAW_DMA:
179 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
180 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
182 pr_warning("%s: Failed to enable DMA for "
183 "PHB#%x-PE#%x, err=%lld\n",
184 __func__, hose->global_number, pe_no, ret);
190 pr_warning("%s: Invalid option %d\n", __func__, option);
198 * ioda_eeh_get_state - Retrieve the state of PE
201 * The PE's state should be retrieved from the PEEV, PEST
202 * IODA tables. Since the OPAL has exported the function
203 * to do it, it'd better to use that.
205 static int ioda_eeh_get_state(struct eeh_pe *pe)
212 struct pci_controller *hose = pe->phb;
213 struct pnv_phb *phb = hose->private_data;
216 * Sanity check on PE address. The PHB PE address should
219 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
220 pr_err("%s: PE address %x out of range [0, %x] "
222 __func__, pe->addr, phb->ioda.total_pe,
223 hose->global_number);
224 return EEH_STATE_NOT_SUPPORT;
227 /* Retrieve PE status through OPAL */
229 ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
230 &fstate, &pcierr, NULL);
232 pr_err("%s: Failed to get EEH status on "
233 "PHB#%x-PE#%x\n, err=%lld\n",
234 __func__, hose->global_number, pe_no, ret);
235 return EEH_STATE_NOT_SUPPORT;
238 /* Check PHB status */
239 if (pe->type & EEH_PE_PHB) {
241 result &= ~EEH_STATE_RESET_ACTIVE;
243 if (pcierr != OPAL_EEH_PHB_ERROR) {
244 result |= EEH_STATE_MMIO_ACTIVE;
245 result |= EEH_STATE_DMA_ACTIVE;
246 result |= EEH_STATE_MMIO_ENABLED;
247 result |= EEH_STATE_DMA_ENABLED;
253 /* Parse result out */
256 case OPAL_EEH_STOPPED_NOT_FROZEN:
257 result &= ~EEH_STATE_RESET_ACTIVE;
258 result |= EEH_STATE_MMIO_ACTIVE;
259 result |= EEH_STATE_DMA_ACTIVE;
260 result |= EEH_STATE_MMIO_ENABLED;
261 result |= EEH_STATE_DMA_ENABLED;
263 case OPAL_EEH_STOPPED_MMIO_FREEZE:
264 result &= ~EEH_STATE_RESET_ACTIVE;
265 result |= EEH_STATE_DMA_ACTIVE;
266 result |= EEH_STATE_DMA_ENABLED;
268 case OPAL_EEH_STOPPED_DMA_FREEZE:
269 result &= ~EEH_STATE_RESET_ACTIVE;
270 result |= EEH_STATE_MMIO_ACTIVE;
271 result |= EEH_STATE_MMIO_ENABLED;
273 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
274 result &= ~EEH_STATE_RESET_ACTIVE;
276 case OPAL_EEH_STOPPED_RESET:
277 result |= EEH_STATE_RESET_ACTIVE;
279 case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
280 result |= EEH_STATE_UNAVAILABLE;
282 case OPAL_EEH_STOPPED_PERM_UNAVAIL:
283 result |= EEH_STATE_NOT_SUPPORT;
286 pr_warning("%s: Unexpected EEH status 0x%x "
288 __func__, fstate, hose->global_number, pe_no);
294 static int ioda_eeh_pe_clear(struct eeh_pe *pe)
296 struct pci_controller *hose;
305 phb = pe->phb->private_data;
307 /* Clear the EEH error on the PE */
308 ret = opal_pci_eeh_freeze_clear(phb->opal_id,
309 pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
311 pr_err("%s: Failed to clear EEH error for "
312 "PHB#%x-PE#%x, err=%lld\n",
313 __func__, hose->global_number, pe_no, ret);
318 * Read the PE state back and verify that the frozen
319 * state has been removed.
321 ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
322 &fstate, &pcierr, NULL);
324 pr_err("%s: Failed to get EEH status on "
325 "PHB#%x-PE#%x\n, err=%lld\n",
326 __func__, hose->global_number, pe_no, ret);
330 if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
331 pr_err("%s: Frozen state not cleared on "
332 "PHB#%x-PE#%x, sts=%x\n",
333 __func__, hose->global_number, pe_no, fstate);
340 static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
342 s64 rc = OPAL_HARDWARE;
345 rc = opal_pci_poll(phb->opal_id);
355 static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
357 struct pnv_phb *phb = hose->private_data;
358 s64 rc = OPAL_HARDWARE;
360 pr_debug("%s: Reset PHB#%x, option=%d\n",
361 __func__, hose->global_number, option);
363 /* Issue PHB complete reset request */
364 if (option == EEH_RESET_FUNDAMENTAL ||
365 option == EEH_RESET_HOT)
366 rc = opal_pci_reset(phb->opal_id,
369 else if (option == EEH_RESET_DEACTIVATE)
370 rc = opal_pci_reset(phb->opal_id,
372 OPAL_DEASSERT_RESET);
377 * Poll state of the PHB until the request is done
380 rc = ioda_eeh_phb_poll(phb);
382 if (rc != OPAL_SUCCESS)
388 static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
390 struct pnv_phb *phb = hose->private_data;
391 s64 rc = OPAL_SUCCESS;
393 pr_debug("%s: Reset PHB#%x, option=%d\n",
394 __func__, hose->global_number, option);
397 * During the reset deassert time, we needn't care
398 * the reset scope because the firmware does nothing
399 * for fundamental or hot reset during deassert phase.
401 if (option == EEH_RESET_FUNDAMENTAL)
402 rc = opal_pci_reset(phb->opal_id,
403 OPAL_PCI_FUNDAMENTAL_RESET,
405 else if (option == EEH_RESET_HOT)
406 rc = opal_pci_reset(phb->opal_id,
409 else if (option == EEH_RESET_DEACTIVATE)
410 rc = opal_pci_reset(phb->opal_id,
412 OPAL_DEASSERT_RESET);
416 /* Poll state of the PHB until the request is done */
417 rc = ioda_eeh_phb_poll(phb);
419 if (rc != OPAL_SUCCESS)
425 static int ioda_eeh_bridge_reset(struct pci_controller *hose,
426 struct pci_dev *dev, int option)
430 pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
431 __func__, hose->global_number, dev->bus->number,
432 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
435 case EEH_RESET_FUNDAMENTAL:
437 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
438 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
439 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
441 case EEH_RESET_DEACTIVATE:
442 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
443 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
444 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
452 * ioda_eeh_reset - Reset the indicated PE
454 * @option: reset option
456 * Do reset on the indicated PE. For PCI bus sensitive PE,
457 * we need to reset the parent p2p bridge. The PHB has to
458 * be reinitialized if the p2p bridge is root bridge. For
459 * PCI device sensitive PE, we will try to reset the device
460 * through FLR. For now, we don't have OPAL APIs to do HARD
461 * reset yet, so all reset would be SOFT (HOT) reset.
463 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
465 struct pci_controller *hose = pe->phb;
466 struct eeh_dev *edev;
471 * Anyway, we have to clear the problematic state for the
472 * corresponding PE. However, we needn't do it if the PE
473 * is PHB associated. That means the PHB is having fatal
474 * errors and it needs reset. Further more, the AIB interface
475 * isn't reliable any more.
477 if (!(pe->type & EEH_PE_PHB) &&
478 (option == EEH_RESET_HOT ||
479 option == EEH_RESET_FUNDAMENTAL)) {
480 ret = ioda_eeh_pe_clear(pe);
486 * The rules applied to reset, either fundamental or hot reset:
488 * We always reset the direct upstream bridge of the PE. If the
489 * direct upstream bridge isn't root bridge, we always take hot
490 * reset no matter what option (fundamental or hot) is. Otherwise,
491 * we should do the reset according to the required option.
493 if (pe->type & EEH_PE_PHB) {
494 ret = ioda_eeh_phb_reset(hose, option);
496 if (pe->type & EEH_PE_DEVICE) {
498 * If it's device PE, we didn't refer to the parent
499 * PCI bus yet. So we have to figure it out indirectly.
501 edev = list_first_entry(&pe->edevs,
502 struct eeh_dev, list);
503 dev = eeh_dev_to_pci_dev(edev);
504 dev = dev->bus->self;
507 * If it's bus PE, the parent PCI bus is already there
508 * and just pick it up.
514 * Do reset based on the fact that the direct upstream bridge
515 * is root bridge (port) or not.
517 if (dev->bus->number == 0)
518 ret = ioda_eeh_root_reset(hose, option);
520 ret = ioda_eeh_bridge_reset(hose, dev, option);
527 * ioda_eeh_get_log - Retrieve error log
529 * @severity: Severity level of the log
530 * @drv_log: buffer to store the log
531 * @len: space of the log buffer
533 * The function is used to retrieve error log from P7IOC.
535 static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
536 char *drv_log, unsigned long len)
540 struct pci_controller *hose = pe->phb;
541 struct pnv_phb *phb = hose->private_data;
543 spin_lock_irqsave(&phb->lock, flags);
545 ret = opal_pci_get_phb_diag_data2(phb->opal_id,
546 phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
548 spin_unlock_irqrestore(&phb->lock, flags);
549 pr_warning("%s: Failed to get log for PHB#%x-PE#%x\n",
550 __func__, hose->global_number, pe->addr);
555 * FIXME: We probably need log the error in somewhere.
556 * Lets make it up in future.
558 /* pr_info("%s", phb->diag.blob); */
560 spin_unlock_irqrestore(&phb->lock, flags);
566 * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
569 * For particular PE, it might have included PCI bridges. In order
570 * to make the PE work properly, those PCI bridges should be configured
571 * correctly. However, we need do nothing on P7IOC since the reset
572 * function will do everything that should be covered by the function.
574 static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
579 static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
582 pr_info(" GEM XFIR: %016llx\n", data->gemXfir);
583 pr_info(" GEM RFIR: %016llx\n", data->gemRfir);
584 pr_info(" GEM RIRQFIR: %016llx\n", data->gemRirqfir);
585 pr_info(" GEM Mask: %016llx\n", data->gemMask);
586 pr_info(" GEM RWOF: %016llx\n", data->gemRwof);
589 pr_info(" LEM FIR: %016llx\n", data->lemFir);
590 pr_info(" LEM Error Mask: %016llx\n", data->lemErrMask);
591 pr_info(" LEM Action 0: %016llx\n", data->lemAction0);
592 pr_info(" LEM Action 1: %016llx\n", data->lemAction1);
593 pr_info(" LEM WOF: %016llx\n", data->lemWof);
596 static void ioda_eeh_hub_diag(struct pci_controller *hose)
598 struct pnv_phb *phb = hose->private_data;
599 struct OpalIoP7IOCErrorData *data;
602 data = (struct OpalIoP7IOCErrorData *)ioda_eeh_hub_diag;
603 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, PAGE_SIZE);
604 if (rc != OPAL_SUCCESS) {
605 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
606 __func__, phb->hub_id, rc);
610 switch (data->type) {
611 case OPAL_P7IOC_DIAG_TYPE_RGC:
612 pr_info("P7IOC diag-data for RGC\n\n");
613 ioda_eeh_hub_diag_common(data);
614 pr_info(" RGC Status: %016llx\n", data->rgc.rgcStatus);
615 pr_info(" RGC LDCP: %016llx\n", data->rgc.rgcLdcp);
617 case OPAL_P7IOC_DIAG_TYPE_BI:
618 pr_info("P7IOC diag-data for BI %s\n\n",
619 data->bi.biDownbound ? "Downbound" : "Upbound");
620 ioda_eeh_hub_diag_common(data);
621 pr_info(" BI LDCP 0: %016llx\n", data->bi.biLdcp0);
622 pr_info(" BI LDCP 1: %016llx\n", data->bi.biLdcp1);
623 pr_info(" BI LDCP 2: %016llx\n", data->bi.biLdcp2);
624 pr_info(" BI Fence Status: %016llx\n", data->bi.biFenceStatus);
626 case OPAL_P7IOC_DIAG_TYPE_CI:
627 pr_info("P7IOC diag-data for CI Port %d\\nn",
629 ioda_eeh_hub_diag_common(data);
630 pr_info(" CI Port Status: %016llx\n", data->ci.ciPortStatus);
631 pr_info(" CI Port LDCP: %016llx\n", data->ci.ciPortLdcp);
633 case OPAL_P7IOC_DIAG_TYPE_MISC:
634 pr_info("P7IOC diag-data for MISC\n\n");
635 ioda_eeh_hub_diag_common(data);
637 case OPAL_P7IOC_DIAG_TYPE_I2C:
638 pr_info("P7IOC diag-data for I2C\n\n");
639 ioda_eeh_hub_diag_common(data);
642 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
643 __func__, phb->hub_id, data->type);
647 static void ioda_eeh_p7ioc_phb_diag(struct pci_controller *hose,
648 struct OpalIoPhbErrorCommon *common)
650 struct OpalIoP7IOCPhbErrorData *data;
653 data = (struct OpalIoP7IOCPhbErrorData *)common;
655 pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n\n",
656 hose->global_number, common->version);
658 pr_info(" brdgCtl: %08x\n", data->brdgCtl);
660 pr_info(" portStatusReg: %08x\n", data->portStatusReg);
661 pr_info(" rootCmplxStatus: %08x\n", data->rootCmplxStatus);
662 pr_info(" busAgentStatus: %08x\n", data->busAgentStatus);
664 pr_info(" deviceStatus: %08x\n", data->deviceStatus);
665 pr_info(" slotStatus: %08x\n", data->slotStatus);
666 pr_info(" linkStatus: %08x\n", data->linkStatus);
667 pr_info(" devCmdStatus: %08x\n", data->devCmdStatus);
668 pr_info(" devSecStatus: %08x\n", data->devSecStatus);
670 pr_info(" rootErrorStatus: %08x\n", data->rootErrorStatus);
671 pr_info(" uncorrErrorStatus: %08x\n", data->uncorrErrorStatus);
672 pr_info(" corrErrorStatus: %08x\n", data->corrErrorStatus);
673 pr_info(" tlpHdr1: %08x\n", data->tlpHdr1);
674 pr_info(" tlpHdr2: %08x\n", data->tlpHdr2);
675 pr_info(" tlpHdr3: %08x\n", data->tlpHdr3);
676 pr_info(" tlpHdr4: %08x\n", data->tlpHdr4);
677 pr_info(" sourceId: %08x\n", data->sourceId);
679 pr_info(" errorClass: %016llx\n", data->errorClass);
680 pr_info(" correlator: %016llx\n", data->correlator);
681 pr_info(" p7iocPlssr: %016llx\n", data->p7iocPlssr);
682 pr_info(" p7iocCsr: %016llx\n", data->p7iocCsr);
683 pr_info(" lemFir: %016llx\n", data->lemFir);
684 pr_info(" lemErrorMask: %016llx\n", data->lemErrorMask);
685 pr_info(" lemWOF: %016llx\n", data->lemWOF);
686 pr_info(" phbErrorStatus: %016llx\n", data->phbErrorStatus);
687 pr_info(" phbFirstErrorStatus: %016llx\n", data->phbFirstErrorStatus);
688 pr_info(" phbErrorLog0: %016llx\n", data->phbErrorLog0);
689 pr_info(" phbErrorLog1: %016llx\n", data->phbErrorLog1);
690 pr_info(" mmioErrorStatus: %016llx\n", data->mmioErrorStatus);
691 pr_info(" mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
692 pr_info(" mmioErrorLog0: %016llx\n", data->mmioErrorLog0);
693 pr_info(" mmioErrorLog1: %016llx\n", data->mmioErrorLog1);
694 pr_info(" dma0ErrorStatus: %016llx\n", data->dma0ErrorStatus);
695 pr_info(" dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
696 pr_info(" dma0ErrorLog0: %016llx\n", data->dma0ErrorLog0);
697 pr_info(" dma0ErrorLog1: %016llx\n", data->dma0ErrorLog1);
698 pr_info(" dma1ErrorStatus: %016llx\n", data->dma1ErrorStatus);
699 pr_info(" dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
700 pr_info(" dma1ErrorLog0: %016llx\n", data->dma1ErrorLog0);
701 pr_info(" dma1ErrorLog1: %016llx\n", data->dma1ErrorLog1);
703 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
704 if ((data->pestA[i] >> 63) == 0 &&
705 (data->pestB[i] >> 63) == 0)
708 pr_info(" PE[%3d] PESTA: %016llx\n", i, data->pestA[i]);
709 pr_info(" PESTB: %016llx\n", data->pestB[i]);
713 static void ioda_eeh_phb_diag(struct pci_controller *hose)
715 struct pnv_phb *phb = hose->private_data;
716 struct OpalIoPhbErrorCommon *common;
719 common = (struct OpalIoPhbErrorCommon *)phb->diag.blob;
720 rc = opal_pci_get_phb_diag_data2(phb->opal_id, common, PAGE_SIZE);
721 if (rc != OPAL_SUCCESS) {
722 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
723 __func__, hose->global_number, rc);
727 switch (common->ioType) {
728 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
729 ioda_eeh_p7ioc_phb_diag(hose, common);
732 pr_warning("%s: Unrecognized I/O chip %d\n",
733 __func__, common->ioType);
737 static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
740 struct eeh_pe *phb_pe;
742 phb_pe = eeh_phb_pe_get(hose);
744 pr_warning("%s Can't find PE for PHB#%d\n",
745 __func__, hose->global_number);
753 static int ioda_eeh_get_pe(struct pci_controller *hose,
754 u16 pe_no, struct eeh_pe **pe)
756 struct eeh_pe *phb_pe, *dev_pe;
759 /* Find the PHB PE */
760 if (ioda_eeh_get_phb_pe(hose, &phb_pe))
763 /* Find the PE according to PE# */
764 memset(&dev, 0, sizeof(struct eeh_dev));
766 dev.pe_config_addr = pe_no;
767 dev_pe = eeh_pe_get(&dev);
769 pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
770 __func__, hose->global_number, pe_no);
779 * ioda_eeh_next_error - Retrieve next error for EEH core to handle
780 * @pe: The affected PE
782 * The function is expected to be called by EEH core while it gets
783 * special EEH event (without binding PE). The function calls to
784 * OPAL APIs for next error to handle. The informational error is
785 * handled internally by platform. However, the dead IOC, dead PHB,
786 * fenced PHB and frozen PE should be handled by EEH core eventually.
788 static int ioda_eeh_next_error(struct eeh_pe **pe)
790 struct pci_controller *hose, *tmp;
793 u16 err_type, severity;
798 * While running here, it's safe to purge the event queue.
799 * And we should keep the cached OPAL notifier event sychronized
800 * between the kernel and firmware.
802 eeh_remove_event(NULL);
803 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
805 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
807 * If the subordinate PCI buses of the PHB has been
808 * removed, we needn't take care of it any more.
810 phb = hose->private_data;
811 if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
814 rc = opal_pci_next_error(phb->opal_id,
815 &frozen_pe_no, &err_type, &severity);
817 /* If OPAL API returns error, we needn't proceed */
818 if (rc != OPAL_SUCCESS) {
819 pr_devel("%s: Invalid return value on "
820 "PHB#%x (0x%lx) from opal_pci_next_error",
821 __func__, hose->global_number, rc);
825 /* If the PHB doesn't have error, stop processing */
826 if (err_type == OPAL_EEH_NO_ERROR ||
827 severity == OPAL_EEH_SEV_NO_ERROR) {
828 pr_devel("%s: No error found on PHB#%x\n",
829 __func__, hose->global_number);
834 * Processing the error. We're expecting the error with
835 * highest priority reported upon multiple errors on the
838 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
839 __func__, err_type, severity,
840 frozen_pe_no, hose->global_number);
842 case OPAL_EEH_IOC_ERROR:
843 if (severity == OPAL_EEH_SEV_IOC_DEAD) {
844 list_for_each_entry_safe(hose, tmp,
845 &hose_list, list_node) {
846 phb = hose->private_data;
847 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
850 pr_err("EEH: dead IOC detected\n");
853 } else if (severity == OPAL_EEH_SEV_INF) {
854 pr_info("EEH: IOC informative error "
856 ioda_eeh_hub_diag(hose);
860 case OPAL_EEH_PHB_ERROR:
861 if (severity == OPAL_EEH_SEV_PHB_DEAD) {
862 if (ioda_eeh_get_phb_pe(hose, pe))
865 pr_err("EEH: dead PHB#%x detected\n",
866 hose->global_number);
867 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
870 } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
871 if (ioda_eeh_get_phb_pe(hose, pe))
874 pr_err("EEH: fenced PHB#%x detected\n",
875 hose->global_number);
878 } else if (severity == OPAL_EEH_SEV_INF) {
879 pr_info("EEH: PHB#%x informative error "
881 hose->global_number);
882 ioda_eeh_phb_diag(hose);
886 case OPAL_EEH_PE_ERROR:
887 if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
890 pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
891 (*pe)->addr, (*pe)->phb->global_number);
902 struct pnv_eeh_ops ioda_eeh_ops = {
903 .post_init = ioda_eeh_post_init,
904 .set_option = ioda_eeh_set_option,
905 .get_state = ioda_eeh_get_state,
906 .reset = ioda_eeh_reset,
907 .get_log = ioda_eeh_get_log,
908 .configure_bridge = ioda_eeh_configure_bridge,
909 .next_error = ioda_eeh_next_error