arch/powerpc/platforms/8xx/mpc885ads_setup.c

   1 /*
   2  * Platform setup for the Freescale mpc885ads board
   3  *
   4  * Vitaly Bordug <vbordug@ru.mvista.com>
   5  *
   6  * Copyright 2005 MontaVista Software Inc.
   7  *
   8  * Heavily modified by Scott Wood <scottwood@freescale.com>
   9  * Copyright 2007 Freescale Semiconductor, Inc.
  10  *
  11  * This file is licensed under the terms of the GNU General Public License
  12  * version 2. This program is licensed "as is" without any warranty of any
  13  * kind, whether express or implied.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/param.h>
  19 #include <linux/string.h>
  20 #include <linux/ioport.h>
  21 #include <linux/device.h>
  22 #include <linux/delay.h>
  23
  24 #include <linux/fs_uart_pd.h>
  25 #include <linux/fsl_devices.h>
  26 #include <linux/mii.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_fdt.h>
  29 #include <linux/of_platform.h>
  30
  31 #include <asm/delay.h>
  32 #include <asm/io.h>
  33 #include <asm/machdep.h>
  34 #include <asm/page.h>
  35 #include <asm/processor.h>
  36 #include <asm/time.h>
  37 #include <asm/8xx_immap.h>
  38 #include <asm/cpm1.h>
  39 #include <asm/udbg.h>
  40
  41 #include "mpc885ads.h"
  42 #include "mpc8xx.h"
  43 #include "pic.h"
  44
  45 static u32 __iomem *bcsr, *bcsr5;
  46
  47 struct cpm_pin {
  48         int port, pin, flags;
  49 };
  50
  51 static struct cpm_pin mpc885ads_pins[] = {
  52         /* SMC1 */
  53         {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
  54         {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
  55
  56         /* SMC2 */
  57 #ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
  58         {CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
  59         {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
  60 #endif
  61
  62         /* SCC3 */
  63         {CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
  64         {CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
  65         {CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
  66         {CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
  67         {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
  68         {CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
  69         {CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
  70
  71         /* MII1 */
  72         {CPM_PORTA, 0, CPM_PIN_INPUT},
  73         {CPM_PORTA, 1, CPM_PIN_INPUT},
  74         {CPM_PORTA, 2, CPM_PIN_INPUT},
  75         {CPM_PORTA, 3, CPM_PIN_INPUT},
  76         {CPM_PORTA, 4, CPM_PIN_OUTPUT},
  77         {CPM_PORTA, 10, CPM_PIN_OUTPUT},
  78         {CPM_PORTA, 11, CPM_PIN_OUTPUT},
  79         {CPM_PORTB, 19, CPM_PIN_INPUT},
  80         {CPM_PORTB, 31, CPM_PIN_INPUT},
  81         {CPM_PORTC, 12, CPM_PIN_INPUT},
  82         {CPM_PORTC, 13, CPM_PIN_INPUT},
  83         {CPM_PORTE, 30, CPM_PIN_OUTPUT},
  84         {CPM_PORTE, 31, CPM_PIN_OUTPUT},
  85
  86         /* MII2 */
  87 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
  88         {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  89         {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  90         {CPM_PORTE, 16, CPM_PIN_OUTPUT},
  91         {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  92         {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  93         {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  94         {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  95         {CPM_PORTE, 21, CPM_PIN_OUTPUT},
  96         {CPM_PORTE, 22, CPM_PIN_OUTPUT},
  97         {CPM_PORTE, 23, CPM_PIN_OUTPUT},
  98         {CPM_PORTE, 24, CPM_PIN_OUTPUT},
  99         {CPM_PORTE, 25, CPM_PIN_OUTPUT},
 100         {CPM_PORTE, 26, CPM_PIN_OUTPUT},
 101         {CPM_PORTE, 27, CPM_PIN_OUTPUT},
 102         {CPM_PORTE, 28, CPM_PIN_OUTPUT},
 103         {CPM_PORTE, 29, CPM_PIN_OUTPUT},
 104 #endif
 105         /* I2C */
 106         {CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
 107         {CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
 108 };
 109
 110 static void __init init_ioports(void)
 111 {
 112         int i;
 113
 114         for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
 115                 struct cpm_pin *pin = &mpc885ads_pins[i];
 116                 cpm1_set_pin(pin->port, pin->pin, pin->flags);
 117         }
 118
 119         cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
 120         cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
 121         cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
 122         cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
 123
 124         /* Set FEC1 and FEC2 to MII mode */
 125         clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
 126 }
 127
 128 static void __init mpc885ads_setup_arch(void)
 129 {
 130         struct device_node *np;
 131
 132         cpm_reset();
 133         init_ioports();
 134
 135         np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
 136         if (!np) {
 137                 printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
 138                 return;
 139         }
 140
 141         bcsr = of_iomap(np, 0);
 142         bcsr5 = of_iomap(np, 1);
 143         of_node_put(np);
 144
 145         if (!bcsr || !bcsr5) {
 146                 printk(KERN_CRIT "Could not remap BCSR\n");
 147                 return;
 148         }
 149
 150         clrbits32(&bcsr[1], BCSR1_RS232EN_1);
 151 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 152         setbits32(&bcsr[1], BCSR1_RS232EN_2);
 153 #else
 154         clrbits32(&bcsr[1], BCSR1_RS232EN_2);
 155 #endif
 156
 157         clrbits32(bcsr5, BCSR5_MII1_EN);
 158         setbits32(bcsr5, BCSR5_MII1_RST);
 159         udelay(1000);
 160         clrbits32(bcsr5, BCSR5_MII1_RST);
 161
 162 #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
 163         clrbits32(bcsr5, BCSR5_MII2_EN);
 164         setbits32(bcsr5, BCSR5_MII2_RST);
 165         udelay(1000);
 166         clrbits32(bcsr5, BCSR5_MII2_RST);
 167 #else
 168         setbits32(bcsr5, BCSR5_MII2_EN);
 169 #endif
 170
 171 #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
 172         clrbits32(&bcsr[4], BCSR4_ETH10_RST);
 173         udelay(1000);
 174         setbits32(&bcsr[4], BCSR4_ETH10_RST);
 175
 176         setbits32(&bcsr[1], BCSR1_ETHEN);
 177
 178         np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
 179 #else
 180         np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
 181 #endif
 182
 183         /* The SCC3 enet registers overlap the SMC1 registers, so
 184          * one of the two must be removed from the device tree.
 185          */
 186
 187         if (np) {
 188                 of_detach_node(np);
 189                 of_node_put(np);
 190         }
 191 }
 192
 193 static const struct of_device_id of_bus_ids[] __initconst = {
 194         { .name = "soc", },
 195         { .name = "cpm", },
 196         { .name = "localbus", },
 197         {},
 198 };
 199
 200 static int __init declare_of_platform_devices(void)
 201 {
 202         /* Publish the QE devices */
 203         of_platform_bus_probe(NULL, of_bus_ids, NULL);
 204
 205         return 0;
 206 }
 207 machine_device_initcall(mpc885_ads, declare_of_platform_devices);
 208
 209 define_machine(mpc885_ads) {
 210         .name                   = "Freescale MPC885 ADS",
 211         .compatible             = "fsl,mpc885ads",
 212         .setup_arch             = mpc885ads_setup_arch,
 213         .init_IRQ               = mpc8xx_pic_init,
 214         .get_irq                = mpc8xx_get_irq,
 215         .restart                = mpc8xx_restart,
 216         .calibrate_decr         = mpc8xx_calibrate_decr,
 217         .progress               = udbg_progress,
 218 };