1 // SPDX-License-Identifier: GPL-2.0-only
3 * eBPF JIT compiler for PPC32
5 * Copyright 2020 Christophe Leroy <christophe.leroy@csgroup.eu>
8 * Based on PPC64 eBPF JIT compiler by Naveen N. Rao
10 #include <linux/moduleloader.h>
11 #include <asm/cacheflush.h>
12 #include <asm/asm-compat.h>
13 #include <linux/netdevice.h>
14 #include <linux/filter.h>
15 #include <linux/if_vlan.h>
16 #include <asm/kprobes.h>
17 #include <linux/bpf.h>
24 * [ prev sp ] <-------------
25 * [ nv gpr save area ] 16 * 4 |
26 * fp (r31) --> [ ebpf stack space ] upto 512 |
27 * [ frame header ] 16 |
28 * sp (r1) ---> [ stack pointer ] --------------
31 /* for gpr non volatile registers r17 to r31 (14) + tail call */
32 #define BPF_PPC_STACK_SAVE (15 * 4 + 4)
33 /* stack frame, ensure this is quadword aligned */
34 #define BPF_PPC_STACKFRAME(ctx) (STACK_FRAME_MIN_SIZE + BPF_PPC_STACK_SAVE + (ctx)->stack_size)
36 #define PPC_EX32(r, i) EMIT(PPC_RAW_LI((r), (i) < 0 ? -1 : 0))
38 /* PPC NVR range -- update this if we ever use NVRs below r17 */
39 #define BPF_PPC_NVR_MIN _R17
40 #define BPF_PPC_TC _R16
42 /* BPF register usage */
43 #define TMP_REG (MAX_BPF_JIT_REG + 0)
45 /* BPF to ppc register mappings */
46 void bpf_jit_init_reg_mapping(struct codegen_context *ctx)
48 /* function return value */
49 ctx->b2p[BPF_REG_0] = _R12;
50 /* function arguments */
51 ctx->b2p[BPF_REG_1] = _R4;
52 ctx->b2p[BPF_REG_2] = _R6;
53 ctx->b2p[BPF_REG_3] = _R8;
54 ctx->b2p[BPF_REG_4] = _R10;
55 ctx->b2p[BPF_REG_5] = _R22;
56 /* non volatile registers */
57 ctx->b2p[BPF_REG_6] = _R24;
58 ctx->b2p[BPF_REG_7] = _R26;
59 ctx->b2p[BPF_REG_8] = _R28;
60 ctx->b2p[BPF_REG_9] = _R30;
61 /* frame pointer aka BPF_REG_10 */
62 ctx->b2p[BPF_REG_FP] = _R18;
63 /* eBPF jit internal registers */
64 ctx->b2p[BPF_REG_AX] = _R20;
65 ctx->b2p[TMP_REG] = _R31; /* 32 bits */
68 static int bpf_jit_stack_offsetof(struct codegen_context *ctx, int reg)
70 if ((reg >= BPF_PPC_NVR_MIN && reg < 32) || reg == BPF_PPC_TC)
71 return BPF_PPC_STACKFRAME(ctx) - 4 * (32 - reg);
73 WARN(true, "BPF JIT is asking about unknown registers, will crash the stack");
74 /* Use the hole we have left for alignment */
75 return BPF_PPC_STACKFRAME(ctx) - 4;
78 #define SEEN_VREG_MASK 0x1ff80000 /* Volatile registers r3-r12 */
79 #define SEEN_NVREG_FULL_MASK 0x0003ffff /* Non volatile registers r14-r31 */
80 #define SEEN_NVREG_TEMP_MASK 0x00001e01 /* BPF_REG_5, BPF_REG_AX, TMP_REG */
82 static inline bool bpf_has_stack_frame(struct codegen_context *ctx)
85 * We only need a stack frame if:
86 * - we call other functions (kernel helpers), or
87 * - we use non volatile registers, or
88 * - we use tail call counter
89 * - the bpf program uses its stack area
90 * The latter condition is deduced from the usage of BPF_REG_FP
92 return ctx->seen & (SEEN_FUNC | SEEN_TAILCALL | SEEN_NVREG_FULL_MASK) ||
93 bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP));
96 void bpf_jit_realloc_regs(struct codegen_context *ctx)
98 unsigned int nvreg_mask;
100 if (ctx->seen & SEEN_FUNC)
101 nvreg_mask = SEEN_NVREG_TEMP_MASK;
103 nvreg_mask = SEEN_NVREG_FULL_MASK;
105 while (ctx->seen & nvreg_mask &&
106 (ctx->seen & SEEN_VREG_MASK) != SEEN_VREG_MASK) {
107 int old = 32 - fls(ctx->seen & (nvreg_mask & 0xaaaaaaab));
108 int new = 32 - fls(~ctx->seen & (SEEN_VREG_MASK & 0xaaaaaaaa));
111 for (i = BPF_REG_0; i <= TMP_REG; i++) {
112 if (ctx->b2p[i] != old)
115 bpf_set_seen_register(ctx, new);
116 bpf_clear_seen_register(ctx, old);
118 bpf_set_seen_register(ctx, new - 1);
119 bpf_clear_seen_register(ctx, old - 1);
126 void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx)
130 /* Initialize tail_call_cnt, to be skipped if we do tail calls. */
131 if (ctx->seen & SEEN_TAILCALL)
132 EMIT(PPC_RAW_LI(_R4, 0));
136 #define BPF_TAILCALL_PROLOGUE_SIZE 4
138 if (bpf_has_stack_frame(ctx))
139 EMIT(PPC_RAW_STWU(_R1, _R1, -BPF_PPC_STACKFRAME(ctx)));
141 if (ctx->seen & SEEN_TAILCALL)
142 EMIT(PPC_RAW_STW(_R4, _R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC)));
144 /* First arg comes in as a 32 bits pointer. */
145 EMIT(PPC_RAW_MR(bpf_to_ppc(BPF_REG_1), _R3));
146 EMIT(PPC_RAW_LI(bpf_to_ppc(BPF_REG_1) - 1, 0));
149 * We need a stack frame, but we don't necessarily need to
150 * save/restore LR unless we call other functions
152 if (ctx->seen & SEEN_FUNC)
153 EMIT(PPC_RAW_MFLR(_R0));
156 * Back up non-volatile regs -- registers r18-r31
158 for (i = BPF_PPC_NVR_MIN; i <= 31; i++)
159 if (bpf_is_seen_register(ctx, i))
160 EMIT(PPC_RAW_STW(i, _R1, bpf_jit_stack_offsetof(ctx, i)));
162 /* If needed retrieve arguments 9 and 10, ie 5th 64 bits arg.*/
163 if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_5))) {
164 EMIT(PPC_RAW_LWZ(bpf_to_ppc(BPF_REG_5) - 1, _R1, BPF_PPC_STACKFRAME(ctx)) + 8);
165 EMIT(PPC_RAW_LWZ(bpf_to_ppc(BPF_REG_5), _R1, BPF_PPC_STACKFRAME(ctx)) + 12);
168 /* Setup frame pointer to point to the bpf stack area */
169 if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_FP))) {
170 EMIT(PPC_RAW_LI(bpf_to_ppc(BPF_REG_FP) - 1, 0));
171 EMIT(PPC_RAW_ADDI(bpf_to_ppc(BPF_REG_FP), _R1,
172 STACK_FRAME_MIN_SIZE + ctx->stack_size));
175 if (ctx->seen & SEEN_FUNC)
176 EMIT(PPC_RAW_STW(_R0, _R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF));
179 static void bpf_jit_emit_common_epilogue(u32 *image, struct codegen_context *ctx)
184 for (i = BPF_PPC_NVR_MIN; i <= 31; i++)
185 if (bpf_is_seen_register(ctx, i))
186 EMIT(PPC_RAW_LWZ(i, _R1, bpf_jit_stack_offsetof(ctx, i)));
188 if (ctx->seen & SEEN_FUNC)
189 EMIT(PPC_RAW_LWZ(_R0, _R1, BPF_PPC_STACKFRAME(ctx) + PPC_LR_STKOFF));
191 /* Tear down our stack frame */
192 if (bpf_has_stack_frame(ctx))
193 EMIT(PPC_RAW_ADDI(_R1, _R1, BPF_PPC_STACKFRAME(ctx)));
195 if (ctx->seen & SEEN_FUNC)
196 EMIT(PPC_RAW_MTLR(_R0));
200 void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx)
202 EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(BPF_REG_0)));
204 bpf_jit_emit_common_epilogue(image, ctx);
209 int bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func)
211 s32 rel = (s32)func - (s32)(image + ctx->idx);
213 if (image && rel < 0x2000000 && rel >= -0x2000000) {
219 /* Load function address into r0 */
220 EMIT(PPC_RAW_LIS(_R0, IMM_H(func)));
221 EMIT(PPC_RAW_ORI(_R0, _R0, IMM_L(func)));
222 EMIT(PPC_RAW_MTCTR(_R0));
223 EMIT(PPC_RAW_BCTRL());
229 static int bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 out)
232 * By now, the eBPF program has already setup parameters in r3-r6
233 * r3-r4/BPF_REG_1 - pointer to ctx -- passed as is to the next bpf program
234 * r5-r6/BPF_REG_2 - pointer to bpf_array
235 * r7-r8/BPF_REG_3 - index in bpf_array
237 int b2p_bpf_array = bpf_to_ppc(BPF_REG_2);
238 int b2p_index = bpf_to_ppc(BPF_REG_3);
241 * if (index >= array->map.max_entries)
244 EMIT(PPC_RAW_LWZ(_R0, b2p_bpf_array, offsetof(struct bpf_array, map.max_entries)));
245 EMIT(PPC_RAW_CMPLW(b2p_index, _R0));
246 EMIT(PPC_RAW_LWZ(_R0, _R1, bpf_jit_stack_offsetof(ctx, BPF_PPC_TC)));
247 PPC_BCC_SHORT(COND_GE, out);
250 * if (tail_call_cnt >= MAX_TAIL_CALL_CNT)
253 EMIT(PPC_RAW_CMPLWI(_R0, MAX_TAIL_CALL_CNT));
254 /* tail_call_cnt++; */
255 EMIT(PPC_RAW_ADDIC(_R0, _R0, 1));
256 PPC_BCC_SHORT(COND_GE, out);
258 /* prog = array->ptrs[index]; */
259 EMIT(PPC_RAW_RLWINM(_R3, b2p_index, 2, 0, 29));
260 EMIT(PPC_RAW_ADD(_R3, _R3, b2p_bpf_array));
261 EMIT(PPC_RAW_LWZ(_R3, _R3, offsetof(struct bpf_array, ptrs)));
267 EMIT(PPC_RAW_CMPLWI(_R3, 0));
268 PPC_BCC_SHORT(COND_EQ, out);
270 /* goto *(prog->bpf_func + prologue_size); */
271 EMIT(PPC_RAW_LWZ(_R3, _R3, offsetof(struct bpf_prog, bpf_func)));
272 EMIT(PPC_RAW_ADDIC(_R3, _R3, BPF_TAILCALL_PROLOGUE_SIZE));
273 EMIT(PPC_RAW_MTCTR(_R3));
275 EMIT(PPC_RAW_MR(_R3, bpf_to_ppc(BPF_REG_1)));
277 /* Put tail_call_cnt in r4 */
278 EMIT(PPC_RAW_MR(_R4, _R0));
280 /* tear restore NVRs, ... */
281 bpf_jit_emit_common_epilogue(image, ctx);
283 EMIT(PPC_RAW_BCTR());
289 /* Assemble the body code between the prologue & epilogue */
290 int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *ctx,
291 u32 *addrs, int pass)
293 const struct bpf_insn *insn = fp->insnsi;
297 /* Start of epilogue code - will only be valid 2nd pass onwards */
298 u32 exit_addr = addrs[flen];
300 for (i = 0; i < flen; i++) {
301 u32 code = insn[i].code;
302 u32 dst_reg = bpf_to_ppc(insn[i].dst_reg);
303 u32 dst_reg_h = dst_reg - 1;
304 u32 src_reg = bpf_to_ppc(insn[i].src_reg);
305 u32 src_reg_h = src_reg - 1;
306 u32 ax_reg = bpf_to_ppc(BPF_REG_AX);
307 u32 tmp_reg = bpf_to_ppc(TMP_REG);
308 u32 size = BPF_SIZE(code);
309 u32 save_reg, ret_reg;
310 s16 off = insn[i].off;
311 s32 imm = insn[i].imm;
312 bool func_addr_fixed;
319 * addrs[] maps a BPF bytecode address into a real offset from
320 * the start of the body code.
322 addrs[i] = ctx->idx * 4;
325 * As an optimization, we note down which registers
326 * are used so that we can only save/restore those in our
327 * prologue and epilogue. We do this here regardless of whether
328 * the actual BPF instruction uses src/dst registers or not
329 * (for instance, BPF_CALL does not use them). The expectation
330 * is that those instructions will have src_reg/dst_reg set to
331 * 0. Even otherwise, we just lose some prologue/epilogue
332 * optimization but everything else should work without
335 if (dst_reg >= 3 && dst_reg < 32) {
336 bpf_set_seen_register(ctx, dst_reg);
337 bpf_set_seen_register(ctx, dst_reg_h);
340 if (src_reg >= 3 && src_reg < 32) {
341 bpf_set_seen_register(ctx, src_reg);
342 bpf_set_seen_register(ctx, src_reg_h);
347 * Arithmetic operations: ADD/SUB/MUL/DIV/MOD/NEG
349 case BPF_ALU | BPF_ADD | BPF_X: /* (u32) dst += (u32) src */
350 EMIT(PPC_RAW_ADD(dst_reg, dst_reg, src_reg));
352 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst += src */
353 EMIT(PPC_RAW_ADDC(dst_reg, dst_reg, src_reg));
354 EMIT(PPC_RAW_ADDE(dst_reg_h, dst_reg_h, src_reg_h));
356 case BPF_ALU | BPF_SUB | BPF_X: /* (u32) dst -= (u32) src */
357 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, src_reg));
359 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst -= src */
360 EMIT(PPC_RAW_SUBFC(dst_reg, src_reg, dst_reg));
361 EMIT(PPC_RAW_SUBFE(dst_reg_h, src_reg_h, dst_reg_h));
363 case BPF_ALU | BPF_SUB | BPF_K: /* (u32) dst -= (u32) imm */
366 case BPF_ALU | BPF_ADD | BPF_K: /* (u32) dst += (u32) imm */
367 if (IMM_HA(imm) & 0xffff)
368 EMIT(PPC_RAW_ADDIS(dst_reg, dst_reg, IMM_HA(imm)));
370 EMIT(PPC_RAW_ADDI(dst_reg, dst_reg, IMM_L(imm)));
372 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst -= imm */
375 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst += imm */
379 if (imm >= -32768 && imm < 32768) {
380 EMIT(PPC_RAW_ADDIC(dst_reg, dst_reg, imm));
383 EMIT(PPC_RAW_ADDC(dst_reg, dst_reg, _R0));
385 if (imm >= 0 || (BPF_OP(code) == BPF_SUB && imm == 0x80000000))
386 EMIT(PPC_RAW_ADDZE(dst_reg_h, dst_reg_h));
388 EMIT(PPC_RAW_ADDME(dst_reg_h, dst_reg_h));
390 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst *= src */
391 bpf_set_seen_register(ctx, tmp_reg);
392 EMIT(PPC_RAW_MULW(_R0, dst_reg, src_reg_h));
393 EMIT(PPC_RAW_MULW(dst_reg_h, dst_reg_h, src_reg));
394 EMIT(PPC_RAW_MULHWU(tmp_reg, dst_reg, src_reg));
395 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, src_reg));
396 EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, _R0));
397 EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, tmp_reg));
399 case BPF_ALU | BPF_MUL | BPF_X: /* (u32) dst *= (u32) src */
400 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, src_reg));
402 case BPF_ALU | BPF_MUL | BPF_K: /* (u32) dst *= (u32) imm */
403 if (imm >= -32768 && imm < 32768) {
404 EMIT(PPC_RAW_MULI(dst_reg, dst_reg, imm));
407 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, _R0));
410 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst *= imm */
412 PPC_LI32(dst_reg, 0);
413 PPC_LI32(dst_reg_h, 0);
419 EMIT(PPC_RAW_SUBFIC(dst_reg, dst_reg, 0));
420 EMIT(PPC_RAW_SUBFZE(dst_reg_h, dst_reg_h));
423 bpf_set_seen_register(ctx, tmp_reg);
424 PPC_LI32(tmp_reg, imm);
425 EMIT(PPC_RAW_MULW(dst_reg_h, dst_reg_h, tmp_reg));
427 EMIT(PPC_RAW_SUB(dst_reg_h, dst_reg_h, dst_reg));
428 EMIT(PPC_RAW_MULHWU(_R0, dst_reg, tmp_reg));
429 EMIT(PPC_RAW_MULW(dst_reg, dst_reg, tmp_reg));
430 EMIT(PPC_RAW_ADD(dst_reg_h, dst_reg_h, _R0));
432 case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */
433 EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, src_reg));
435 case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */
436 EMIT(PPC_RAW_DIVWU(_R0, dst_reg, src_reg));
437 EMIT(PPC_RAW_MULW(_R0, src_reg, _R0));
438 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, _R0));
440 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst /= src */
442 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst %= src */
444 case BPF_ALU | BPF_DIV | BPF_K: /* (u32) dst /= (u32) imm */
451 EMIT(PPC_RAW_DIVWU(dst_reg, dst_reg, _R0));
453 case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */
457 if (!is_power_of_2((u32)imm)) {
458 bpf_set_seen_register(ctx, tmp_reg);
459 PPC_LI32(tmp_reg, imm);
460 EMIT(PPC_RAW_DIVWU(_R0, dst_reg, tmp_reg));
461 EMIT(PPC_RAW_MULW(_R0, tmp_reg, _R0));
462 EMIT(PPC_RAW_SUB(dst_reg, dst_reg, _R0));
466 EMIT(PPC_RAW_LI(dst_reg, 0));
468 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 32 - ilog2((u32)imm), 31));
471 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst %= imm */
476 if (!is_power_of_2(imm))
479 EMIT(PPC_RAW_LI(dst_reg, 0));
481 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 32 - ilog2(imm), 31));
482 EMIT(PPC_RAW_LI(dst_reg_h, 0));
484 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst /= imm */
487 if (!is_power_of_2(abs(imm)))
491 EMIT(PPC_RAW_SUBFIC(dst_reg, dst_reg, 0));
492 EMIT(PPC_RAW_SUBFZE(dst_reg_h, dst_reg_h));
498 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 32 - imm, imm, 31));
499 EMIT(PPC_RAW_RLWIMI(dst_reg, dst_reg_h, 32 - imm, 0, imm - 1));
500 EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg_h, imm));
502 case BPF_ALU | BPF_NEG: /* (u32) dst = -dst */
503 EMIT(PPC_RAW_NEG(dst_reg, dst_reg));
505 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
506 EMIT(PPC_RAW_SUBFIC(dst_reg, dst_reg, 0));
507 EMIT(PPC_RAW_SUBFZE(dst_reg_h, dst_reg_h));
511 * Logical operations: AND/OR/XOR/[A]LSH/[A]RSH
513 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
514 EMIT(PPC_RAW_AND(dst_reg, dst_reg, src_reg));
515 EMIT(PPC_RAW_AND(dst_reg_h, dst_reg_h, src_reg_h));
517 case BPF_ALU | BPF_AND | BPF_X: /* (u32) dst = dst & src */
518 EMIT(PPC_RAW_AND(dst_reg, dst_reg, src_reg));
520 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
522 EMIT(PPC_RAW_LI(dst_reg_h, 0));
524 case BPF_ALU | BPF_AND | BPF_K: /* (u32) dst = dst & imm */
526 EMIT(PPC_RAW_ANDI(dst_reg, dst_reg, IMM_L(imm)));
527 } else if (!IMM_L(imm)) {
528 EMIT(PPC_RAW_ANDIS(dst_reg, dst_reg, IMM_H(imm)));
529 } else if (imm == (((1 << fls(imm)) - 1) ^ ((1 << (ffs(i) - 1)) - 1))) {
530 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0,
531 32 - fls(imm), 32 - ffs(imm)));
534 EMIT(PPC_RAW_AND(dst_reg, dst_reg, _R0));
537 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
538 EMIT(PPC_RAW_OR(dst_reg, dst_reg, src_reg));
539 EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, src_reg_h));
541 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
542 EMIT(PPC_RAW_OR(dst_reg, dst_reg, src_reg));
544 case BPF_ALU64 | BPF_OR | BPF_K:/* dst = dst | imm */
547 EMIT(PPC_RAW_LI(dst_reg_h, -1));
549 case BPF_ALU | BPF_OR | BPF_K:/* dst = (u32) dst | (u32) imm */
551 EMIT(PPC_RAW_ORI(dst_reg, dst_reg, IMM_L(imm)));
553 EMIT(PPC_RAW_ORIS(dst_reg, dst_reg, IMM_H(imm)));
555 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst ^= src */
556 if (dst_reg == src_reg) {
557 EMIT(PPC_RAW_LI(dst_reg, 0));
558 EMIT(PPC_RAW_LI(dst_reg_h, 0));
560 EMIT(PPC_RAW_XOR(dst_reg, dst_reg, src_reg));
561 EMIT(PPC_RAW_XOR(dst_reg_h, dst_reg_h, src_reg_h));
564 case BPF_ALU | BPF_XOR | BPF_X: /* (u32) dst ^= src */
565 if (dst_reg == src_reg)
566 EMIT(PPC_RAW_LI(dst_reg, 0));
568 EMIT(PPC_RAW_XOR(dst_reg, dst_reg, src_reg));
570 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst ^= imm */
572 EMIT(PPC_RAW_NOR(dst_reg_h, dst_reg_h, dst_reg_h));
574 case BPF_ALU | BPF_XOR | BPF_K: /* (u32) dst ^= (u32) imm */
576 EMIT(PPC_RAW_XORI(dst_reg, dst_reg, IMM_L(imm)));
578 EMIT(PPC_RAW_XORIS(dst_reg, dst_reg, IMM_H(imm)));
580 case BPF_ALU | BPF_LSH | BPF_X: /* (u32) dst <<= (u32) src */
581 EMIT(PPC_RAW_SLW(dst_reg, dst_reg, src_reg));
583 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst <<= src; */
584 bpf_set_seen_register(ctx, tmp_reg);
585 EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32));
586 EMIT(PPC_RAW_SLW(dst_reg_h, dst_reg_h, src_reg));
587 EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32));
588 EMIT(PPC_RAW_SRW(_R0, dst_reg, _R0));
589 EMIT(PPC_RAW_SLW(tmp_reg, dst_reg, tmp_reg));
590 EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, _R0));
591 EMIT(PPC_RAW_SLW(dst_reg, dst_reg, src_reg));
592 EMIT(PPC_RAW_OR(dst_reg_h, dst_reg_h, tmp_reg));
594 case BPF_ALU | BPF_LSH | BPF_K: /* (u32) dst <<= (u32) imm */
597 EMIT(PPC_RAW_SLWI(dst_reg, dst_reg, imm));
599 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst <<= imm */
605 EMIT(PPC_RAW_RLWINM(dst_reg_h, dst_reg_h, imm, 0, 31 - imm));
606 EMIT(PPC_RAW_RLWIMI(dst_reg_h, dst_reg, imm, 32 - imm, 31));
607 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, imm, 0, 31 - imm));
611 EMIT(PPC_RAW_RLWINM(dst_reg_h, dst_reg, imm, 0, 31 - imm));
613 EMIT(PPC_RAW_LI(dst_reg_h, 0));
614 EMIT(PPC_RAW_LI(dst_reg, 0));
616 case BPF_ALU | BPF_RSH | BPF_X: /* (u32) dst >>= (u32) src */
617 EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg));
619 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst >>= src */
620 bpf_set_seen_register(ctx, tmp_reg);
621 EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32));
622 EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg));
623 EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32));
624 EMIT(PPC_RAW_SLW(_R0, dst_reg_h, _R0));
625 EMIT(PPC_RAW_SRW(tmp_reg, dst_reg_h, tmp_reg));
626 EMIT(PPC_RAW_OR(dst_reg, dst_reg, _R0));
627 EMIT(PPC_RAW_SRW(dst_reg_h, dst_reg_h, src_reg));
628 EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp_reg));
630 case BPF_ALU | BPF_RSH | BPF_K: /* (u32) dst >>= (u32) imm */
633 EMIT(PPC_RAW_SRWI(dst_reg, dst_reg, imm));
635 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst >>= imm */
641 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 32 - imm, imm, 31));
642 EMIT(PPC_RAW_RLWIMI(dst_reg, dst_reg_h, 32 - imm, 0, imm - 1));
643 EMIT(PPC_RAW_RLWINM(dst_reg_h, dst_reg_h, 32 - imm, imm, 31));
647 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg_h, 64 - imm, imm - 32, 31));
649 EMIT(PPC_RAW_LI(dst_reg, 0));
650 EMIT(PPC_RAW_LI(dst_reg_h, 0));
652 case BPF_ALU | BPF_ARSH | BPF_X: /* (s32) dst >>= src */
653 EMIT(PPC_RAW_SRAW(dst_reg, dst_reg, src_reg));
655 case BPF_ALU64 | BPF_ARSH | BPF_X: /* (s64) dst >>= src */
656 bpf_set_seen_register(ctx, tmp_reg);
657 EMIT(PPC_RAW_SUBFIC(_R0, src_reg, 32));
658 EMIT(PPC_RAW_SRW(dst_reg, dst_reg, src_reg));
659 EMIT(PPC_RAW_SLW(_R0, dst_reg_h, _R0));
660 EMIT(PPC_RAW_ADDI(tmp_reg, src_reg, 32));
661 EMIT(PPC_RAW_OR(dst_reg, dst_reg, _R0));
662 EMIT(PPC_RAW_RLWINM(_R0, tmp_reg, 0, 26, 26));
663 EMIT(PPC_RAW_SRAW(tmp_reg, dst_reg_h, tmp_reg));
664 EMIT(PPC_RAW_SRAW(dst_reg_h, dst_reg_h, src_reg));
665 EMIT(PPC_RAW_SLW(tmp_reg, tmp_reg, _R0));
666 EMIT(PPC_RAW_OR(dst_reg, dst_reg, tmp_reg));
668 case BPF_ALU | BPF_ARSH | BPF_K: /* (s32) dst >>= imm */
671 EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg, imm));
673 case BPF_ALU64 | BPF_ARSH | BPF_K: /* (s64) dst >>= imm */
679 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 32 - imm, imm, 31));
680 EMIT(PPC_RAW_RLWIMI(dst_reg, dst_reg_h, 32 - imm, 0, imm - 1));
681 EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg_h, imm));
685 EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg_h, imm - 32));
687 EMIT(PPC_RAW_SRAWI(dst_reg, dst_reg_h, 31));
688 EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg_h, 31));
694 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
695 if (dst_reg == src_reg)
697 EMIT(PPC_RAW_MR(dst_reg, src_reg));
698 EMIT(PPC_RAW_MR(dst_reg_h, src_reg_h));
700 case BPF_ALU | BPF_MOV | BPF_X: /* (u32) dst = src */
701 /* special mov32 for zext */
703 EMIT(PPC_RAW_LI(dst_reg_h, 0));
704 else if (dst_reg != src_reg)
705 EMIT(PPC_RAW_MR(dst_reg, src_reg));
707 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = (s64) imm */
708 PPC_LI32(dst_reg, imm);
709 PPC_EX32(dst_reg_h, imm);
711 case BPF_ALU | BPF_MOV | BPF_K: /* (u32) dst = imm */
712 PPC_LI32(dst_reg, imm);
718 case BPF_ALU | BPF_END | BPF_FROM_LE:
721 /* Copy 16 bits to upper part */
722 EMIT(PPC_RAW_RLWIMI(dst_reg, dst_reg, 16, 0, 15));
723 /* Rotate 8 bits right & mask */
724 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 24, 16, 31));
728 * Rotate word left by 8 bits:
729 * 2 bytes are already in their final position
730 * -- byte 2 and 4 (of bytes 1, 2, 3 and 4)
732 EMIT(PPC_RAW_RLWINM(_R0, dst_reg, 8, 0, 31));
733 /* Rotate 24 bits and insert byte 1 */
734 EMIT(PPC_RAW_RLWIMI(_R0, dst_reg, 24, 0, 7));
735 /* Rotate 24 bits and insert byte 3 */
736 EMIT(PPC_RAW_RLWIMI(_R0, dst_reg, 24, 16, 23));
737 EMIT(PPC_RAW_MR(dst_reg, _R0));
740 bpf_set_seen_register(ctx, tmp_reg);
741 EMIT(PPC_RAW_RLWINM(tmp_reg, dst_reg, 8, 0, 31));
742 EMIT(PPC_RAW_RLWINM(_R0, dst_reg_h, 8, 0, 31));
743 /* Rotate 24 bits and insert byte 1 */
744 EMIT(PPC_RAW_RLWIMI(tmp_reg, dst_reg, 24, 0, 7));
745 EMIT(PPC_RAW_RLWIMI(_R0, dst_reg_h, 24, 0, 7));
746 /* Rotate 24 bits and insert byte 3 */
747 EMIT(PPC_RAW_RLWIMI(tmp_reg, dst_reg, 24, 16, 23));
748 EMIT(PPC_RAW_RLWIMI(_R0, dst_reg_h, 24, 16, 23));
749 EMIT(PPC_RAW_MR(dst_reg, _R0));
750 EMIT(PPC_RAW_MR(dst_reg_h, tmp_reg));
754 case BPF_ALU | BPF_END | BPF_FROM_BE:
757 /* zero-extend 16 bits into 32 bits */
758 EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 16, 31));
768 * BPF_ST NOSPEC (speculation barrier)
770 case BPF_ST | BPF_NOSPEC:
776 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src */
777 EMIT(PPC_RAW_STB(src_reg, dst_reg, off));
779 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
781 EMIT(PPC_RAW_STB(_R0, dst_reg, off));
783 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
784 EMIT(PPC_RAW_STH(src_reg, dst_reg, off));
786 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
788 EMIT(PPC_RAW_STH(_R0, dst_reg, off));
790 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
791 EMIT(PPC_RAW_STW(src_reg, dst_reg, off));
793 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
795 EMIT(PPC_RAW_STW(_R0, dst_reg, off));
797 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
798 EMIT(PPC_RAW_STW(src_reg_h, dst_reg, off));
799 EMIT(PPC_RAW_STW(src_reg, dst_reg, off + 4));
801 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
803 EMIT(PPC_RAW_STW(_R0, dst_reg, off + 4));
805 EMIT(PPC_RAW_STW(_R0, dst_reg, off));
809 * BPF_STX ATOMIC (atomic ops)
811 case BPF_STX | BPF_ATOMIC | BPF_W:
815 bpf_set_seen_register(ctx, tmp_reg);
816 bpf_set_seen_register(ctx, ax_reg);
818 /* Get offset into TMP_REG */
819 EMIT(PPC_RAW_LI(tmp_reg, off));
820 tmp_idx = ctx->idx * 4;
821 /* load value from memory into r0 */
822 EMIT(PPC_RAW_LWARX(_R0, tmp_reg, dst_reg, 0));
824 /* Save old value in BPF_REG_AX */
826 EMIT(PPC_RAW_MR(ax_reg, _R0));
830 case BPF_ADD | BPF_FETCH:
831 EMIT(PPC_RAW_ADD(_R0, _R0, src_reg));
834 case BPF_AND | BPF_FETCH:
835 EMIT(PPC_RAW_AND(_R0, _R0, src_reg));
838 case BPF_OR | BPF_FETCH:
839 EMIT(PPC_RAW_OR(_R0, _R0, src_reg));
842 case BPF_XOR | BPF_FETCH:
843 EMIT(PPC_RAW_XOR(_R0, _R0, src_reg));
847 * Return old value in BPF_REG_0 for BPF_CMPXCHG &
848 * in src_reg for other cases.
850 ret_reg = bpf_to_ppc(BPF_REG_0);
852 /* Compare with old value in BPF_REG_0 */
853 EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), _R0));
854 /* Don't set if different from old value */
855 PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4);
861 pr_err_ratelimited("eBPF filter atomic op code %02x (@%d) unsupported\n",
866 /* store new value */
867 EMIT(PPC_RAW_STWCX(save_reg, tmp_reg, dst_reg));
868 /* we're done if this succeeded */
869 PPC_BCC_SHORT(COND_NE, tmp_idx);
871 /* For the BPF_FETCH variant, get old data into src_reg */
872 if (imm & BPF_FETCH) {
873 EMIT(PPC_RAW_MR(ret_reg, ax_reg));
874 if (!fp->aux->verifier_zext)
875 EMIT(PPC_RAW_LI(ret_reg - 1, 0)); /* higher 32-bit */
879 case BPF_STX | BPF_ATOMIC | BPF_DW: /* *(u64 *)(dst + off) += src */
885 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
886 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
887 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
888 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
889 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
890 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
891 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
892 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
894 * As PTR_TO_BTF_ID that uses BPF_PROBE_MEM mode could either be a valid
895 * kernel pointer or NULL but not a userspace address, execute BPF_PROBE_MEM
896 * load only if addr is kernel address (see is_kernel_addr()), otherwise
897 * set dst_reg=0 and move on.
899 if (BPF_MODE(code) == BPF_PROBE_MEM) {
900 PPC_LI32(_R0, TASK_SIZE - off);
901 EMIT(PPC_RAW_CMPLW(src_reg, _R0));
902 PPC_BCC_SHORT(COND_GT, (ctx->idx + 4) * 4);
903 EMIT(PPC_RAW_LI(dst_reg, 0));
905 * For BPF_DW case, "li reg_h,0" would be needed when
906 * !fp->aux->verifier_zext. Emit NOP otherwise.
908 * Note that "li reg_h,0" is emitted for BPF_B/H/W case,
909 * if necessary. So, jump there insted of emitting an
910 * additional "li reg_h,0" instruction.
912 if (size == BPF_DW && !fp->aux->verifier_zext)
913 EMIT(PPC_RAW_LI(dst_reg_h, 0));
917 * Need to jump two instructions instead of one for BPF_DW case
918 * as there are two load instructions for dst_reg_h & dst_reg
922 PPC_JMP((ctx->idx + 3) * 4);
924 PPC_JMP((ctx->idx + 2) * 4);
929 EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off));
932 EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off));
935 EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off));
938 EMIT(PPC_RAW_LWZ(dst_reg_h, src_reg, off));
939 EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off + 4));
943 if (size != BPF_DW && !fp->aux->verifier_zext)
944 EMIT(PPC_RAW_LI(dst_reg_h, 0));
946 if (BPF_MODE(code) == BPF_PROBE_MEM) {
947 int insn_idx = ctx->idx - 1;
951 * In case of BPF_DW, two lwz instructions are emitted, one
952 * for higher 32-bit and another for lower 32-bit. So, set
953 * ex->insn to the first of the two and jump over both
954 * instructions in fixup.
956 * Similarly, with !verifier_zext, two instructions are
957 * emitted for BPF_B/H/W case. So, set ex->insn to the
958 * instruction that could fault and skip over both
961 if (size == BPF_DW || !fp->aux->verifier_zext) {
966 ret = bpf_add_extable_entry(fp, image, pass, ctx, insn_idx,
975 * 16 byte instruction that uses two 'struct bpf_insn'
977 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
979 PPC_LI32(dst_reg_h, (u32)insn[i + 1].imm);
980 PPC_LI32(dst_reg, (u32)insn[i].imm);
981 /* padding to allow full 4 instructions for later patching */
982 for (j = ctx->idx - tmp_idx; j < 4; j++)
984 /* Adjust for two bpf instructions */
985 addrs[++i] = ctx->idx * 4;
991 case BPF_JMP | BPF_EXIT:
993 * If this isn't the very last instruction, branch to
994 * the epilogue. If we _are_ the last instruction,
995 * we'll just fall through to the epilogue.
998 ret = bpf_jit_emit_exit_insn(image, ctx, _R0, exit_addr);
1002 /* else fall through to the epilogue */
1006 * Call kernel helper or bpf function
1008 case BPF_JMP | BPF_CALL:
1009 ctx->seen |= SEEN_FUNC;
1011 ret = bpf_jit_get_func_addr(fp, &insn[i], false,
1012 &func_addr, &func_addr_fixed);
1016 if (bpf_is_seen_register(ctx, bpf_to_ppc(BPF_REG_5))) {
1017 EMIT(PPC_RAW_STW(bpf_to_ppc(BPF_REG_5) - 1, _R1, 8));
1018 EMIT(PPC_RAW_STW(bpf_to_ppc(BPF_REG_5), _R1, 12));
1021 ret = bpf_jit_emit_func_call_rel(image, ctx, func_addr);
1025 EMIT(PPC_RAW_MR(bpf_to_ppc(BPF_REG_0) - 1, _R3));
1026 EMIT(PPC_RAW_MR(bpf_to_ppc(BPF_REG_0), _R4));
1030 * Jumps and branches
1032 case BPF_JMP | BPF_JA:
1033 PPC_JMP(addrs[i + 1 + off]);
1036 case BPF_JMP | BPF_JGT | BPF_K:
1037 case BPF_JMP | BPF_JGT | BPF_X:
1038 case BPF_JMP | BPF_JSGT | BPF_K:
1039 case BPF_JMP | BPF_JSGT | BPF_X:
1040 case BPF_JMP32 | BPF_JGT | BPF_K:
1041 case BPF_JMP32 | BPF_JGT | BPF_X:
1042 case BPF_JMP32 | BPF_JSGT | BPF_K:
1043 case BPF_JMP32 | BPF_JSGT | BPF_X:
1044 true_cond = COND_GT;
1046 case BPF_JMP | BPF_JLT | BPF_K:
1047 case BPF_JMP | BPF_JLT | BPF_X:
1048 case BPF_JMP | BPF_JSLT | BPF_K:
1049 case BPF_JMP | BPF_JSLT | BPF_X:
1050 case BPF_JMP32 | BPF_JLT | BPF_K:
1051 case BPF_JMP32 | BPF_JLT | BPF_X:
1052 case BPF_JMP32 | BPF_JSLT | BPF_K:
1053 case BPF_JMP32 | BPF_JSLT | BPF_X:
1054 true_cond = COND_LT;
1056 case BPF_JMP | BPF_JGE | BPF_K:
1057 case BPF_JMP | BPF_JGE | BPF_X:
1058 case BPF_JMP | BPF_JSGE | BPF_K:
1059 case BPF_JMP | BPF_JSGE | BPF_X:
1060 case BPF_JMP32 | BPF_JGE | BPF_K:
1061 case BPF_JMP32 | BPF_JGE | BPF_X:
1062 case BPF_JMP32 | BPF_JSGE | BPF_K:
1063 case BPF_JMP32 | BPF_JSGE | BPF_X:
1064 true_cond = COND_GE;
1066 case BPF_JMP | BPF_JLE | BPF_K:
1067 case BPF_JMP | BPF_JLE | BPF_X:
1068 case BPF_JMP | BPF_JSLE | BPF_K:
1069 case BPF_JMP | BPF_JSLE | BPF_X:
1070 case BPF_JMP32 | BPF_JLE | BPF_K:
1071 case BPF_JMP32 | BPF_JLE | BPF_X:
1072 case BPF_JMP32 | BPF_JSLE | BPF_K:
1073 case BPF_JMP32 | BPF_JSLE | BPF_X:
1074 true_cond = COND_LE;
1076 case BPF_JMP | BPF_JEQ | BPF_K:
1077 case BPF_JMP | BPF_JEQ | BPF_X:
1078 case BPF_JMP32 | BPF_JEQ | BPF_K:
1079 case BPF_JMP32 | BPF_JEQ | BPF_X:
1080 true_cond = COND_EQ;
1082 case BPF_JMP | BPF_JNE | BPF_K:
1083 case BPF_JMP | BPF_JNE | BPF_X:
1084 case BPF_JMP32 | BPF_JNE | BPF_K:
1085 case BPF_JMP32 | BPF_JNE | BPF_X:
1086 true_cond = COND_NE;
1088 case BPF_JMP | BPF_JSET | BPF_K:
1089 case BPF_JMP | BPF_JSET | BPF_X:
1090 case BPF_JMP32 | BPF_JSET | BPF_K:
1091 case BPF_JMP32 | BPF_JSET | BPF_X:
1092 true_cond = COND_NE;
1097 case BPF_JMP | BPF_JGT | BPF_X:
1098 case BPF_JMP | BPF_JLT | BPF_X:
1099 case BPF_JMP | BPF_JGE | BPF_X:
1100 case BPF_JMP | BPF_JLE | BPF_X:
1101 case BPF_JMP | BPF_JEQ | BPF_X:
1102 case BPF_JMP | BPF_JNE | BPF_X:
1103 /* unsigned comparison */
1104 EMIT(PPC_RAW_CMPLW(dst_reg_h, src_reg_h));
1105 PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4);
1106 EMIT(PPC_RAW_CMPLW(dst_reg, src_reg));
1108 case BPF_JMP32 | BPF_JGT | BPF_X:
1109 case BPF_JMP32 | BPF_JLT | BPF_X:
1110 case BPF_JMP32 | BPF_JGE | BPF_X:
1111 case BPF_JMP32 | BPF_JLE | BPF_X:
1112 case BPF_JMP32 | BPF_JEQ | BPF_X:
1113 case BPF_JMP32 | BPF_JNE | BPF_X:
1114 /* unsigned comparison */
1115 EMIT(PPC_RAW_CMPLW(dst_reg, src_reg));
1117 case BPF_JMP | BPF_JSGT | BPF_X:
1118 case BPF_JMP | BPF_JSLT | BPF_X:
1119 case BPF_JMP | BPF_JSGE | BPF_X:
1120 case BPF_JMP | BPF_JSLE | BPF_X:
1121 /* signed comparison */
1122 EMIT(PPC_RAW_CMPW(dst_reg_h, src_reg_h));
1123 PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4);
1124 EMIT(PPC_RAW_CMPLW(dst_reg, src_reg));
1126 case BPF_JMP32 | BPF_JSGT | BPF_X:
1127 case BPF_JMP32 | BPF_JSLT | BPF_X:
1128 case BPF_JMP32 | BPF_JSGE | BPF_X:
1129 case BPF_JMP32 | BPF_JSLE | BPF_X:
1130 /* signed comparison */
1131 EMIT(PPC_RAW_CMPW(dst_reg, src_reg));
1133 case BPF_JMP | BPF_JSET | BPF_X:
1134 EMIT(PPC_RAW_AND_DOT(_R0, dst_reg_h, src_reg_h));
1135 PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4);
1136 EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, src_reg));
1138 case BPF_JMP32 | BPF_JSET | BPF_X: {
1139 EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, src_reg));
1141 case BPF_JMP | BPF_JNE | BPF_K:
1142 case BPF_JMP | BPF_JEQ | BPF_K:
1143 case BPF_JMP | BPF_JGT | BPF_K:
1144 case BPF_JMP | BPF_JLT | BPF_K:
1145 case BPF_JMP | BPF_JGE | BPF_K:
1146 case BPF_JMP | BPF_JLE | BPF_K:
1148 * Need sign-extended load, so only positive
1149 * values can be used as imm in cmplwi
1151 if (imm >= 0 && imm < 32768) {
1152 EMIT(PPC_RAW_CMPLWI(dst_reg_h, 0));
1153 PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4);
1154 EMIT(PPC_RAW_CMPLWI(dst_reg, imm));
1156 /* sign-extending load ... but unsigned comparison */
1158 EMIT(PPC_RAW_CMPLW(dst_reg_h, _R0));
1160 PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4);
1161 EMIT(PPC_RAW_CMPLW(dst_reg, _R0));
1164 case BPF_JMP32 | BPF_JNE | BPF_K:
1165 case BPF_JMP32 | BPF_JEQ | BPF_K:
1166 case BPF_JMP32 | BPF_JGT | BPF_K:
1167 case BPF_JMP32 | BPF_JLT | BPF_K:
1168 case BPF_JMP32 | BPF_JGE | BPF_K:
1169 case BPF_JMP32 | BPF_JLE | BPF_K:
1170 if (imm >= 0 && imm < 65536) {
1171 EMIT(PPC_RAW_CMPLWI(dst_reg, imm));
1174 EMIT(PPC_RAW_CMPLW(dst_reg, _R0));
1178 case BPF_JMP | BPF_JSGT | BPF_K:
1179 case BPF_JMP | BPF_JSLT | BPF_K:
1180 case BPF_JMP | BPF_JSGE | BPF_K:
1181 case BPF_JMP | BPF_JSLE | BPF_K:
1182 if (imm >= 0 && imm < 65536) {
1183 EMIT(PPC_RAW_CMPWI(dst_reg_h, imm < 0 ? -1 : 0));
1184 PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4);
1185 EMIT(PPC_RAW_CMPLWI(dst_reg, imm));
1187 /* sign-extending load */
1188 EMIT(PPC_RAW_CMPWI(dst_reg_h, imm < 0 ? -1 : 0));
1190 PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4);
1191 EMIT(PPC_RAW_CMPLW(dst_reg, _R0));
1194 case BPF_JMP32 | BPF_JSGT | BPF_K:
1195 case BPF_JMP32 | BPF_JSLT | BPF_K:
1196 case BPF_JMP32 | BPF_JSGE | BPF_K:
1197 case BPF_JMP32 | BPF_JSLE | BPF_K:
1199 * signed comparison, so any 16-bit value
1200 * can be used in cmpwi
1202 if (imm >= -32768 && imm < 32768) {
1203 EMIT(PPC_RAW_CMPWI(dst_reg, imm));
1205 /* sign-extending load */
1207 EMIT(PPC_RAW_CMPW(dst_reg, _R0));
1210 case BPF_JMP | BPF_JSET | BPF_K:
1211 /* andi does not sign-extend the immediate */
1212 if (imm >= 0 && imm < 32768) {
1213 /* PPC_ANDI is _only/always_ dot-form */
1214 EMIT(PPC_RAW_ANDI(_R0, dst_reg, imm));
1218 EMIT(PPC_RAW_CMPWI(dst_reg_h, 0));
1219 PPC_BCC_SHORT(COND_NE, (ctx->idx + 2) * 4);
1221 EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, _R0));
1224 case BPF_JMP32 | BPF_JSET | BPF_K:
1225 /* andi does not sign-extend the immediate */
1226 if (imm >= 0 && imm < 32768) {
1227 /* PPC_ANDI is _only/always_ dot-form */
1228 EMIT(PPC_RAW_ANDI(_R0, dst_reg, imm));
1231 EMIT(PPC_RAW_AND_DOT(_R0, dst_reg, _R0));
1235 PPC_BCC(true_cond, addrs[i + 1 + off]);
1241 case BPF_JMP | BPF_TAIL_CALL:
1242 ctx->seen |= SEEN_TAILCALL;
1243 ret = bpf_jit_emit_tail_call(image, ctx, addrs[i + 1]);
1250 * The filter contains something cruel & unusual.
1251 * We don't handle it, but also there shouldn't be
1252 * anything missing from our list.
1254 pr_err_ratelimited("eBPF filter opcode %04x (@%d) unsupported\n", code, i);
1257 if (BPF_CLASS(code) == BPF_ALU && !fp->aux->verifier_zext &&
1258 !insn_is_zext(&insn[i + 1]) && !(BPF_OP(code) == BPF_END && imm == 64))
1259 EMIT(PPC_RAW_LI(dst_reg_h, 0));
1262 /* Set end-of-body-code address for exit. */
1263 addrs[i] = ctx->idx * 4;