1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains the routines for initializing the MMU
4 * on the 8xx series of chips.
7 * Derived from arch/powerpc/mm/40x_mmu.c:
10 #include <linux/memblock.h>
11 #include <linux/hugetlb.h>
13 #include <mm/mmu_decl.h>
15 #define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT)
17 static unsigned long block_mapped_ram;
20 * Return PA for this VA if it is in an area mapped with LTLBs or fixmap.
21 * Otherwise, returns 0
23 phys_addr_t v_block_mapped(unsigned long va)
25 unsigned long p = PHYS_IMMR_BASE;
27 if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE)
28 return p + va - VIRT_IMMR_BASE;
29 if (va >= PAGE_OFFSET && va < PAGE_OFFSET + block_mapped_ram)
35 * Return VA for a given PA mapped with LTLBs or fixmap
36 * Return 0 if not mapped
38 unsigned long p_block_mapped(phys_addr_t pa)
40 unsigned long p = PHYS_IMMR_BASE;
42 if (pa >= p && pa < p + IMMR_SIZE)
43 return VIRT_IMMR_BASE + pa - p;
44 if (pa < block_mapped_ram)
45 return (unsigned long)__va(pa);
49 static pte_t __init *early_hugepd_alloc_kernel(hugepd_t *pmdp, unsigned long va)
51 if (hpd_val(*pmdp) == 0) {
52 pte_t *ptep = memblock_alloc(sizeof(pte_basic_t), SZ_4K);
57 hugepd_populate_kernel((hugepd_t *)pmdp, ptep, PAGE_SHIFT_8M);
58 hugepd_populate_kernel((hugepd_t *)pmdp + 1, ptep, PAGE_SHIFT_8M);
60 return hugepte_offset(*(hugepd_t *)pmdp, va, PGDIR_SHIFT);
63 static int __ref __early_map_kernel_hugepage(unsigned long va, phys_addr_t pa,
64 pgprot_t prot, int psize, bool new)
66 pmd_t *pmdp = pmd_off_k(va);
69 if (WARN_ON(psize != MMU_PAGE_512K && psize != MMU_PAGE_8M))
73 if (WARN_ON(slab_is_available()))
76 if (psize == MMU_PAGE_512K)
77 ptep = early_pte_alloc_kernel(pmdp, va);
79 ptep = early_hugepd_alloc_kernel((hugepd_t *)pmdp, va);
81 if (psize == MMU_PAGE_512K)
82 ptep = pte_offset_kernel(pmdp, va);
84 ptep = hugepte_offset(*(hugepd_t *)pmdp, va, PGDIR_SHIFT);
90 /* The PTE should never be already present */
91 if (new && WARN_ON(pte_present(*ptep) && pgprot_val(prot)))
94 set_huge_pte_at(&init_mm, va, ptep, pte_mkhuge(pfn_pte(pa >> PAGE_SHIFT, prot)));
100 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
102 void __init MMU_init_hw(void)
106 static bool immr_is_mapped __initdata;
108 void __init mmu_mapin_immr(void)
113 immr_is_mapped = true;
115 __early_map_kernel_hugepage(VIRT_IMMR_BASE, PHYS_IMMR_BASE,
116 PAGE_KERNEL_NCG, MMU_PAGE_512K, true);
119 static void mmu_mapin_ram_chunk(unsigned long offset, unsigned long top,
120 pgprot_t prot, bool new)
122 unsigned long v = PAGE_OFFSET + offset;
123 unsigned long p = offset;
125 WARN_ON(!IS_ALIGNED(offset, SZ_512K) || !IS_ALIGNED(top, SZ_512K));
127 for (; p < ALIGN(p, SZ_8M) && p < top; p += SZ_512K, v += SZ_512K)
128 __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_512K, new);
129 for (; p < ALIGN_DOWN(top, SZ_8M) && p < top; p += SZ_8M, v += SZ_8M)
130 __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_8M, new);
131 for (; p < ALIGN_DOWN(top, SZ_512K) && p < top; p += SZ_512K, v += SZ_512K)
132 __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_512K, new);
135 flush_tlb_kernel_range(PAGE_OFFSET + v, PAGE_OFFSET + top);
138 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
140 unsigned long etext8 = ALIGN(__pa(_etext), SZ_8M);
141 unsigned long sinittext = __pa(_sinittext);
142 bool strict_boundary = strict_kernel_rwx_enabled() || debug_pagealloc_enabled_or_kfence();
143 unsigned long boundary = strict_boundary ? sinittext : etext8;
144 unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M);
146 WARN_ON(top < einittext8);
150 mmu_mapin_ram_chunk(0, boundary, PAGE_KERNEL_TEXT, true);
151 if (debug_pagealloc_enabled_or_kfence()) {
154 mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL_TEXT, true);
155 mmu_mapin_ram_chunk(einittext8, top, PAGE_KERNEL, true);
159 memblock_set_current_limit(top);
161 block_mapped_ram = top;
166 void mmu_mark_initmem_nx(void)
168 unsigned long etext8 = ALIGN(__pa(_etext), SZ_8M);
169 unsigned long sinittext = __pa(_sinittext);
170 unsigned long boundary = strict_kernel_rwx_enabled() ? sinittext : etext8;
171 unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M);
173 if (!debug_pagealloc_enabled_or_kfence())
174 mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL, false);
176 mmu_pin_tlb(block_mapped_ram, false);
179 #ifdef CONFIG_STRICT_KERNEL_RWX
180 void mmu_mark_rodata_ro(void)
182 unsigned long sinittext = __pa(_sinittext);
184 mmu_mapin_ram_chunk(0, sinittext, PAGE_KERNEL_ROX, false);
185 if (IS_ENABLED(CONFIG_PIN_TLB_DATA))
186 mmu_pin_tlb(block_mapped_ram, true);
190 void __init setup_initial_memory_limit(phys_addr_t first_memblock_base,
191 phys_addr_t first_memblock_size)
193 /* We don't currently support the first MEMBLOCK not mapping 0
194 * physical on those processors
196 BUG_ON(first_memblock_base != 0);
198 /* 8xx can only access 32MB at the moment */
199 memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_32M));
202 int pud_clear_huge(pud_t *pud)
207 int pmd_clear_huge(pmd_t *pmd)