2 * native hashtable management.
4 * SMP scalability work:
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
18 #include <linux/processor.h>
19 #include <linux/threads.h>
20 #include <linux/smp.h>
22 #include <asm/machdep.h>
24 #include <asm/mmu_context.h>
25 #include <asm/pgtable.h>
26 #include <asm/tlbflush.h>
27 #include <asm/trace.h>
29 #include <asm/cputable.h>
31 #include <asm/kexec.h>
32 #include <asm/ppc-opcode.h>
34 #include <misc/cxl-base.h>
37 #define DBG_LOW(fmt...) udbg_printf(fmt)
39 #define DBG_LOW(fmt...)
43 #define HPTE_LOCK_BIT 3
45 #define HPTE_LOCK_BIT (56+3)
48 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
50 static inline unsigned long ___tlbie(unsigned long vpn, int psize,
51 int apsize, int ssize)
58 * We need 14 to 65 bits of va for a tlibe of 4K page
59 * With vpn we ignore the lower VPN_SHIFT bits already.
60 * And top two bits are already ignored because we can
61 * only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
64 va = vpn << VPN_SHIFT;
66 * clear top 16 bits of 64bit va, non SLS segment
67 * Older versions of the architecture (2.02 and earler) require the
68 * masking of the top 16 bits.
70 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
71 va &= ~(0xffffULL << 48);
75 /* clear out bits after (52) [0....52.....63] */
76 va &= ~((1ul << (64 - 52)) - 1);
78 sllp = get_sllp_encoding(apsize);
80 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
81 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
85 /* We need 14 to 14 + i bits of va */
86 penc = mmu_psize_defs[psize].penc[apsize];
87 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
92 * We don't need all the bits, but rest of the bits
93 * must be ignored by the processor.
94 * vpn cover upto 65 bits of va. (0...65) and we need
97 va |= (vpn & 0xfe); /* AVAL */
99 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
100 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
107 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
111 rb = ___tlbie(vpn, psize, apsize, ssize);
112 trace_tlbie(0, 0, rb, 0, 0, 0, 0);
115 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
121 /* VPN_SHIFT can be atmost 12 */
122 va = vpn << VPN_SHIFT;
124 * clear top 16 bits of 64 bit va, non SLS segment
125 * Older versions of the architecture (2.02 and earler) require the
126 * masking of the top 16 bits.
128 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
129 va &= ~(0xffffULL << 48);
133 /* clear out bits after(52) [0....52.....63] */
134 va &= ~((1ul << (64 - 52)) - 1);
136 sllp = get_sllp_encoding(apsize);
138 asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,0", %1)
139 : : "r" (va), "i" (CPU_FTR_ARCH_206)
143 /* We need 14 to 14 + i bits of va */
144 penc = mmu_psize_defs[psize].penc[apsize];
145 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
150 * We don't need all the bits, but rest of the bits
151 * must be ignored by the processor.
152 * vpn cover upto 65 bits of va. (0...65) and we need
157 asm volatile(ASM_FTR_IFSET("tlbiel %0", "tlbiel %0,1", %1)
158 : : "r" (va), "i" (CPU_FTR_ARCH_206)
162 trace_tlbie(0, 1, va, 0, 0, 0, 0);
166 static inline void tlbie(unsigned long vpn, int psize, int apsize,
167 int ssize, int local)
169 unsigned int use_local;
170 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
172 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use();
175 use_local = mmu_psize_defs[psize].tlbiel;
176 if (lock_tlbie && !use_local)
177 raw_spin_lock(&native_tlbie_lock);
178 asm volatile("ptesync": : :"memory");
180 __tlbiel(vpn, psize, apsize, ssize);
181 asm volatile("ptesync": : :"memory");
183 __tlbie(vpn, psize, apsize, ssize);
184 asm volatile("eieio; tlbsync; ptesync": : :"memory");
186 if (lock_tlbie && !use_local)
187 raw_spin_unlock(&native_tlbie_lock);
190 static inline void native_lock_hpte(struct hash_pte *hptep)
192 unsigned long *word = (unsigned long *)&hptep->v;
195 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
198 while(test_bit(HPTE_LOCK_BIT, word))
204 static inline void native_unlock_hpte(struct hash_pte *hptep)
206 unsigned long *word = (unsigned long *)&hptep->v;
208 clear_bit_unlock(HPTE_LOCK_BIT, word);
211 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
212 unsigned long pa, unsigned long rflags,
213 unsigned long vflags, int psize, int apsize, int ssize)
215 struct hash_pte *hptep = htab_address + hpte_group;
216 unsigned long hpte_v, hpte_r;
219 if (!(vflags & HPTE_V_BOLTED)) {
220 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
221 " rflags=%lx, vflags=%lx, psize=%d)\n",
222 hpte_group, vpn, pa, rflags, vflags, psize);
225 for (i = 0; i < HPTES_PER_GROUP; i++) {
226 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
227 /* retry with lock held */
228 native_lock_hpte(hptep);
229 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
231 native_unlock_hpte(hptep);
237 if (i == HPTES_PER_GROUP)
240 hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
241 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
243 if (!(vflags & HPTE_V_BOLTED)) {
244 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
248 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
249 hpte_r = hpte_old_to_new_r(hpte_v, hpte_r);
250 hpte_v = hpte_old_to_new_v(hpte_v);
253 hptep->r = cpu_to_be64(hpte_r);
254 /* Guarantee the second dword is visible before the valid bit */
257 * Now set the first dword including the valid bit
258 * NOTE: this also unlocks the hpte
260 hptep->v = cpu_to_be64(hpte_v);
262 __asm__ __volatile__ ("ptesync" : : : "memory");
264 return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
267 static long native_hpte_remove(unsigned long hpte_group)
269 struct hash_pte *hptep;
272 unsigned long hpte_v;
274 DBG_LOW(" remove(group=%lx)\n", hpte_group);
276 /* pick a random entry to start at */
277 slot_offset = mftb() & 0x7;
279 for (i = 0; i < HPTES_PER_GROUP; i++) {
280 hptep = htab_address + hpte_group + slot_offset;
281 hpte_v = be64_to_cpu(hptep->v);
283 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
284 /* retry with lock held */
285 native_lock_hpte(hptep);
286 hpte_v = be64_to_cpu(hptep->v);
287 if ((hpte_v & HPTE_V_VALID)
288 && !(hpte_v & HPTE_V_BOLTED))
290 native_unlock_hpte(hptep);
297 if (i == HPTES_PER_GROUP)
300 /* Invalidate the hpte. NOTE: this also unlocks it */
306 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
307 unsigned long vpn, int bpsize,
308 int apsize, int ssize, unsigned long flags)
310 struct hash_pte *hptep = htab_address + slot;
311 unsigned long hpte_v, want_v;
312 int ret = 0, local = 0;
314 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
316 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
317 vpn, want_v & HPTE_V_AVPN, slot, newpp);
319 hpte_v = be64_to_cpu(hptep->v);
320 if (cpu_has_feature(CPU_FTR_ARCH_300))
321 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
323 * We need to invalidate the TLB always because hpte_remove doesn't do
324 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
325 * random entry from it. When we do that we don't invalidate the TLB
326 * (hpte_remove) because we assume the old translation is still
327 * technically "valid".
329 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
330 DBG_LOW(" -> miss\n");
333 native_lock_hpte(hptep);
334 /* recheck with locks held */
335 hpte_v = be64_to_cpu(hptep->v);
336 if (cpu_has_feature(CPU_FTR_ARCH_300))
337 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
338 if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) ||
339 !(hpte_v & HPTE_V_VALID))) {
342 DBG_LOW(" -> hit\n");
343 /* Update the HPTE */
344 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
345 ~(HPTE_R_PPP | HPTE_R_N)) |
346 (newpp & (HPTE_R_PPP | HPTE_R_N |
349 native_unlock_hpte(hptep);
352 if (flags & HPTE_LOCAL_UPDATE)
355 * Ensure it is out of the tlb too if it is not a nohpte fault
357 if (!(flags & HPTE_NOHPTE_UPDATE))
358 tlbie(vpn, bpsize, apsize, ssize, local);
363 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
365 struct hash_pte *hptep;
369 unsigned long want_v, hpte_v;
371 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
372 want_v = hpte_encode_avpn(vpn, psize, ssize);
374 /* Bolted mappings are only ever in the primary group */
375 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
376 for (i = 0; i < HPTES_PER_GROUP; i++) {
377 hptep = htab_address + slot;
378 hpte_v = be64_to_cpu(hptep->v);
379 if (cpu_has_feature(CPU_FTR_ARCH_300))
380 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
382 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
392 * Update the page protection bits. Intended to be used to create
393 * guard pages for kernel data structures on pages which are bolted
394 * in the HPT. Assumes pages being operated on will not be stolen.
396 * No need to lock here because we should be the only user.
398 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
399 int psize, int ssize)
404 struct hash_pte *hptep;
406 vsid = get_kernel_vsid(ea, ssize);
407 vpn = hpt_vpn(ea, vsid, ssize);
409 slot = native_hpte_find(vpn, psize, ssize);
411 panic("could not find page to bolt\n");
412 hptep = htab_address + slot;
414 /* Update the HPTE */
415 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
416 ~(HPTE_R_PPP | HPTE_R_N)) |
417 (newpp & (HPTE_R_PPP | HPTE_R_N)));
419 * Ensure it is out of the tlb too. Bolted entries base and
420 * actual page size will be same.
422 tlbie(vpn, psize, psize, ssize, 0);
426 * Remove a bolted kernel entry. Memory hotplug uses this.
428 * No need to lock here because we should be the only user.
430 static int native_hpte_removebolted(unsigned long ea, int psize, int ssize)
435 struct hash_pte *hptep;
437 vsid = get_kernel_vsid(ea, ssize);
438 vpn = hpt_vpn(ea, vsid, ssize);
440 slot = native_hpte_find(vpn, psize, ssize);
444 hptep = htab_address + slot;
446 VM_WARN_ON(!(be64_to_cpu(hptep->v) & HPTE_V_BOLTED));
448 /* Invalidate the hpte */
451 /* Invalidate the TLB */
452 tlbie(vpn, psize, psize, ssize, 0);
457 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
458 int bpsize, int apsize, int ssize, int local)
460 struct hash_pte *hptep = htab_address + slot;
461 unsigned long hpte_v;
462 unsigned long want_v;
465 local_irq_save(flags);
467 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
469 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
470 native_lock_hpte(hptep);
471 hpte_v = be64_to_cpu(hptep->v);
472 if (cpu_has_feature(CPU_FTR_ARCH_300))
473 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
476 * We need to invalidate the TLB always because hpte_remove doesn't do
477 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
478 * random entry from it. When we do that we don't invalidate the TLB
479 * (hpte_remove) because we assume the old translation is still
480 * technically "valid".
482 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
483 native_unlock_hpte(hptep);
485 /* Invalidate the hpte. NOTE: this also unlocks it */
488 /* Invalidate the TLB */
489 tlbie(vpn, bpsize, apsize, ssize, local);
491 local_irq_restore(flags);
494 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
495 static void native_hugepage_invalidate(unsigned long vsid,
497 unsigned char *hpte_slot_array,
498 int psize, int ssize, int local)
501 struct hash_pte *hptep;
502 int actual_psize = MMU_PAGE_16M;
503 unsigned int max_hpte_count, valid;
504 unsigned long flags, s_addr = addr;
505 unsigned long hpte_v, want_v, shift;
506 unsigned long hidx, vpn = 0, hash, slot;
508 shift = mmu_psize_defs[psize].shift;
509 max_hpte_count = 1U << (PMD_SHIFT - shift);
511 local_irq_save(flags);
512 for (i = 0; i < max_hpte_count; i++) {
513 valid = hpte_valid(hpte_slot_array, i);
516 hidx = hpte_hash_index(hpte_slot_array, i);
519 addr = s_addr + (i * (1ul << shift));
520 vpn = hpt_vpn(addr, vsid, ssize);
521 hash = hpt_hash(vpn, shift, ssize);
522 if (hidx & _PTEIDX_SECONDARY)
525 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
526 slot += hidx & _PTEIDX_GROUP_IX;
528 hptep = htab_address + slot;
529 want_v = hpte_encode_avpn(vpn, psize, ssize);
530 native_lock_hpte(hptep);
531 hpte_v = be64_to_cpu(hptep->v);
532 if (cpu_has_feature(CPU_FTR_ARCH_300))
533 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
535 /* Even if we miss, we need to invalidate the TLB */
536 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
537 native_unlock_hpte(hptep);
539 /* Invalidate the hpte. NOTE: this also unlocks it */
542 * We need to do tlb invalidate for all the address, tlbie
543 * instruction compares entry_VA in tlb with the VA specified
546 tlbie(vpn, psize, actual_psize, ssize, local);
548 local_irq_restore(flags);
551 static void native_hugepage_invalidate(unsigned long vsid,
553 unsigned char *hpte_slot_array,
554 int psize, int ssize, int local)
556 WARN(1, "%s called without THP support\n", __func__);
560 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
561 int *psize, int *apsize, int *ssize, unsigned long *vpn)
563 unsigned long avpn, pteg, vpi;
564 unsigned long hpte_v = be64_to_cpu(hpte->v);
565 unsigned long hpte_r = be64_to_cpu(hpte->r);
566 unsigned long vsid, seg_off;
567 int size, a_size, shift;
568 /* Look at the 8 bit LP value */
569 unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
571 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
572 hpte_v = hpte_new_to_old_v(hpte_v, hpte_r);
573 hpte_r = hpte_new_to_old_r(hpte_r);
575 if (!(hpte_v & HPTE_V_LARGE)) {
577 a_size = MMU_PAGE_4K;
579 size = hpte_page_sizes[lp] & 0xf;
580 a_size = hpte_page_sizes[lp] >> 4;
582 /* This works for all page sizes, and for 256M and 1T segments */
583 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
584 shift = mmu_psize_defs[size].shift;
586 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
587 pteg = slot / HPTES_PER_GROUP;
588 if (hpte_v & HPTE_V_SECONDARY)
592 case MMU_SEGSIZE_256M:
593 /* We only have 28 - 23 bits of seg_off in avpn */
594 seg_off = (avpn & 0x1f) << 23;
596 /* We can find more bits from the pteg value */
598 vpi = (vsid ^ pteg) & htab_hash_mask;
599 seg_off |= vpi << shift;
601 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
604 /* We only have 40 - 23 bits of seg_off in avpn */
605 seg_off = (avpn & 0x1ffff) << 23;
608 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
609 seg_off |= vpi << shift;
611 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
621 * clear all mappings on kexec. All cpus are in real mode (or they will
622 * be when they isi), and we are the only one left. We rely on our kernel
623 * mapping being 0xC0's and the hardware ignoring those two real bits.
625 * This must be called with interrupts disabled.
627 * Taking the native_tlbie_lock is unsafe here due to the possibility of
628 * lockdep being on. On pre POWER5 hardware, not taking the lock could
629 * cause deadlock. POWER5 and newer not taking the lock is fine. This only
630 * gets called during boot before secondary CPUs have come up and during
631 * crashdump and all bets are off anyway.
633 * TODO: add batching support when enabled. remember, no dynamic memory here,
634 * although there is the control page available...
636 static void native_hpte_clear(void)
638 unsigned long vpn = 0;
639 unsigned long slot, slots;
640 struct hash_pte *hptep = htab_address;
641 unsigned long hpte_v;
642 unsigned long pteg_count;
643 int psize, apsize, ssize;
645 pteg_count = htab_hash_mask + 1;
647 slots = pteg_count * HPTES_PER_GROUP;
649 for (slot = 0; slot < slots; slot++, hptep++) {
651 * we could lock the pte here, but we are the only cpu
652 * running, right? and for crash dump, we probably
653 * don't want to wait for a maybe bad cpu.
655 hpte_v = be64_to_cpu(hptep->v);
658 * Call __tlbie() here rather than tlbie() since we can't take the
661 if (hpte_v & HPTE_V_VALID) {
662 hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
664 ___tlbie(vpn, psize, apsize, ssize);
668 asm volatile("eieio; tlbsync; ptesync":::"memory");
672 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
673 * the lock all the time
675 static void native_flush_hash_range(unsigned long number, int local)
678 unsigned long hash, index, hidx, shift, slot;
679 struct hash_pte *hptep;
680 unsigned long hpte_v;
681 unsigned long want_v;
684 struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
685 unsigned long psize = batch->psize;
686 int ssize = batch->ssize;
688 unsigned int use_local;
690 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) &&
691 mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use();
693 local_irq_save(flags);
695 for (i = 0; i < number; i++) {
699 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
700 hash = hpt_hash(vpn, shift, ssize);
701 hidx = __rpte_to_hidx(pte, index);
702 if (hidx & _PTEIDX_SECONDARY)
704 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
705 slot += hidx & _PTEIDX_GROUP_IX;
706 hptep = htab_address + slot;
707 want_v = hpte_encode_avpn(vpn, psize, ssize);
708 native_lock_hpte(hptep);
709 hpte_v = be64_to_cpu(hptep->v);
710 if (cpu_has_feature(CPU_FTR_ARCH_300))
711 hpte_v = hpte_new_to_old_v(hpte_v,
712 be64_to_cpu(hptep->r));
713 if (!HPTE_V_COMPARE(hpte_v, want_v) ||
714 !(hpte_v & HPTE_V_VALID))
715 native_unlock_hpte(hptep);
718 } pte_iterate_hashed_end();
722 asm volatile("ptesync":::"memory");
723 for (i = 0; i < number; i++) {
727 pte_iterate_hashed_subpages(pte, psize,
729 __tlbiel(vpn, psize, psize, ssize);
730 } pte_iterate_hashed_end();
732 asm volatile("ptesync":::"memory");
734 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
737 raw_spin_lock(&native_tlbie_lock);
739 asm volatile("ptesync":::"memory");
740 for (i = 0; i < number; i++) {
744 pte_iterate_hashed_subpages(pte, psize,
746 __tlbie(vpn, psize, psize, ssize);
747 } pte_iterate_hashed_end();
749 asm volatile("eieio; tlbsync; ptesync":::"memory");
752 raw_spin_unlock(&native_tlbie_lock);
755 local_irq_restore(flags);
758 static int native_register_proc_table(unsigned long base, unsigned long page_size,
759 unsigned long table_size)
761 unsigned long patb1 = base << 25; /* VSID */
763 patb1 |= (page_size << 5); /* sllp */
766 partition_tb->patb1 = cpu_to_be64(patb1);
770 void __init hpte_init_native(void)
772 mmu_hash_ops.hpte_invalidate = native_hpte_invalidate;
773 mmu_hash_ops.hpte_updatepp = native_hpte_updatepp;
774 mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;
775 mmu_hash_ops.hpte_removebolted = native_hpte_removebolted;
776 mmu_hash_ops.hpte_insert = native_hpte_insert;
777 mmu_hash_ops.hpte_remove = native_hpte_remove;
778 mmu_hash_ops.hpte_clear_all = native_hpte_clear;
779 mmu_hash_ops.flush_hash_range = native_flush_hash_range;
780 mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate;
782 if (cpu_has_feature(CPU_FTR_ARCH_300))
783 register_process_table = native_register_proc_table;