1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Page table handling routines for radix page table.
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
8 #define pr_fmt(fmt) "radix-mmu: " fmt
11 #include <linux/kernel.h>
12 #include <linux/sched/mm.h>
13 #include <linux/memblock.h>
14 #include <linux/of_fdt.h>
16 #include <linux/hugetlb.h>
17 #include <linux/string_helpers.h>
18 #include <linux/stop_machine.h>
20 #include <asm/pgtable.h>
21 #include <asm/pgalloc.h>
22 #include <asm/mmu_context.h>
24 #include <asm/machdep.h>
26 #include <asm/firmware.h>
27 #include <asm/powernv.h>
28 #include <asm/sections.h>
29 #include <asm/trace.h>
30 #include <asm/uaccess.h>
31 #include <asm/ultravisor.h>
33 #include <trace/events/thp.h>
35 unsigned int mmu_pid_bits;
36 unsigned int mmu_base_pid;
38 static __ref void *early_alloc_pgtable(unsigned long size, int nid,
39 unsigned long region_start, unsigned long region_end)
41 phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT;
42 phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE;
46 min_addr = region_start;
48 max_addr = region_end;
50 ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid);
53 panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n",
54 __func__, size, size, nid, &min_addr, &max_addr);
59 static int early_map_kernel_page(unsigned long ea, unsigned long pa,
61 unsigned int map_page_size,
63 unsigned long region_start, unsigned long region_end)
65 unsigned long pfn = pa >> PAGE_SHIFT;
71 pgdp = pgd_offset_k(ea);
72 if (pgd_none(*pgdp)) {
73 pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid,
74 region_start, region_end);
75 pgd_populate(&init_mm, pgdp, pudp);
77 pudp = pud_offset(pgdp, ea);
78 if (map_page_size == PUD_SIZE) {
82 if (pud_none(*pudp)) {
83 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid,
84 region_start, region_end);
85 pud_populate(&init_mm, pudp, pmdp);
87 pmdp = pmd_offset(pudp, ea);
88 if (map_page_size == PMD_SIZE) {
89 ptep = pmdp_ptep(pmdp);
92 if (!pmd_present(*pmdp)) {
93 ptep = early_alloc_pgtable(PAGE_SIZE, nid,
94 region_start, region_end);
95 pmd_populate_kernel(&init_mm, pmdp, ptep);
97 ptep = pte_offset_kernel(pmdp, ea);
100 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
106 * nid, region_start, and region_end are hints to try to place the page
107 * table memory in the same node or region.
109 static int __map_kernel_page(unsigned long ea, unsigned long pa,
111 unsigned int map_page_size,
113 unsigned long region_start, unsigned long region_end)
115 unsigned long pfn = pa >> PAGE_SHIFT;
121 * Make sure task size is correct as per the max adddr
123 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
125 #ifdef CONFIG_PPC_64K_PAGES
126 BUILD_BUG_ON(RADIX_KERN_MAP_SIZE != (1UL << MAX_EA_BITS_PER_CONTEXT));
129 if (unlikely(!slab_is_available()))
130 return early_map_kernel_page(ea, pa, flags, map_page_size,
131 nid, region_start, region_end);
134 * Should make page table allocation functions be able to take a
135 * node, so we can place kernel page tables on the right nodes after
138 pgdp = pgd_offset_k(ea);
139 pudp = pud_alloc(&init_mm, pgdp, ea);
142 if (map_page_size == PUD_SIZE) {
143 ptep = (pte_t *)pudp;
146 pmdp = pmd_alloc(&init_mm, pudp, ea);
149 if (map_page_size == PMD_SIZE) {
150 ptep = pmdp_ptep(pmdp);
153 ptep = pte_alloc_kernel(pmdp, ea);
158 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
163 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
165 unsigned int map_page_size)
167 return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0);
170 #ifdef CONFIG_STRICT_KERNEL_RWX
171 void radix__change_memory_range(unsigned long start, unsigned long end,
180 start = ALIGN_DOWN(start, PAGE_SIZE);
181 end = PAGE_ALIGN(end); // aligns up
183 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
186 for (idx = start; idx < end; idx += PAGE_SIZE) {
187 pgdp = pgd_offset_k(idx);
188 pudp = pud_alloc(&init_mm, pgdp, idx);
191 if (pud_is_leaf(*pudp)) {
192 ptep = (pte_t *)pudp;
195 pmdp = pmd_alloc(&init_mm, pudp, idx);
198 if (pmd_is_leaf(*pmdp)) {
199 ptep = pmdp_ptep(pmdp);
202 ptep = pte_alloc_kernel(pmdp, idx);
206 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
209 radix__flush_tlb_kernel_range(start, end);
212 void radix__mark_rodata_ro(void)
214 unsigned long start, end;
216 start = (unsigned long)_stext;
217 end = (unsigned long)__init_begin;
219 radix__change_memory_range(start, end, _PAGE_WRITE);
222 void radix__mark_initmem_nx(void)
224 unsigned long start = (unsigned long)__init_begin;
225 unsigned long end = (unsigned long)__init_end;
227 radix__change_memory_range(start, end, _PAGE_EXEC);
229 #endif /* CONFIG_STRICT_KERNEL_RWX */
231 static inline void __meminit
232 print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec)
239 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
241 pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf,
242 exec ? " (exec)" : "");
245 static unsigned long next_boundary(unsigned long addr, unsigned long end)
247 #ifdef CONFIG_STRICT_KERNEL_RWX
248 if (addr < __pa_symbol(__init_begin))
249 return __pa_symbol(__init_begin);
254 static int __meminit create_physical_mapping(unsigned long start,
258 unsigned long vaddr, addr, mapping_size = 0;
259 bool prev_exec, exec = false;
263 start = _ALIGN_UP(start, PAGE_SIZE);
264 for (addr = start; addr < end; addr += mapping_size) {
265 unsigned long gap, previous_size;
268 gap = next_boundary(addr, end) - addr;
269 previous_size = mapping_size;
272 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
273 mmu_psize_defs[MMU_PAGE_1G].shift) {
274 mapping_size = PUD_SIZE;
276 } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
277 mmu_psize_defs[MMU_PAGE_2M].shift) {
278 mapping_size = PMD_SIZE;
281 mapping_size = PAGE_SIZE;
282 psize = mmu_virtual_psize;
285 vaddr = (unsigned long)__va(addr);
287 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
288 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) {
289 prot = PAGE_KERNEL_X;
296 if (mapping_size != previous_size || exec != prev_exec) {
297 print_mapping(start, addr, previous_size, prev_exec);
301 rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end);
305 update_page_count(psize, 1);
308 print_mapping(start, addr, mapping_size, exec);
312 static void __init radix_init_pgtable(void)
314 unsigned long rts_field;
315 struct memblock_region *reg;
317 /* We don't support slb for radix */
320 * Create the linear mapping, using standard page size for now
322 for_each_memblock(memory, reg) {
324 * The memblock allocator is up at this point, so the
325 * page tables will be allocated within the range. No
326 * need or a node (which we don't have yet).
329 if ((reg->base + reg->size) >= RADIX_VMALLOC_START) {
330 pr_warn("Outside the supported range\n");
334 WARN_ON(create_physical_mapping(reg->base,
335 reg->base + reg->size,
339 /* Find out how many PID bits are supported */
340 if (cpu_has_feature(CPU_FTR_HVMODE)) {
343 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
345 * When KVM is possible, we only use the top half of the
346 * PID space to avoid collisions between host and guest PIDs
347 * which can cause problems due to prefetch when exiting the
350 mmu_base_pid = 1 << (mmu_pid_bits - 1);
355 /* The guest uses the bottom half of the PID space */
362 * Allocate Partition table and process table for the
365 BUG_ON(PRTB_SIZE_SHIFT > 36);
366 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0);
368 * Fill in the process table.
370 rts_field = radix__get_tree_size();
371 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
374 * The init_mm context is given the first available (non-zero) PID,
375 * which is the "guard PID" and contains no page table. PIDR should
376 * never be set to zero because that duplicates the kernel address
377 * space at the 0x0... offset (quadrant 0)!
379 * An arbitrary PID that may later be allocated by the PID allocator
380 * for userspace processes must not be used either, because that
381 * would cause stale user mappings for that PID on CPUs outside of
382 * the TLB invalidation scheme (because it won't be in mm_cpumask).
384 * So permanently carve out one PID for the purpose of a guard PID.
386 init_mm.context.id = mmu_base_pid;
390 static void __init radix_init_partition_table(void)
392 unsigned long rts_field, dw0, dw1;
394 mmu_partition_table_init();
395 rts_field = radix__get_tree_size();
396 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
397 dw1 = __pa(process_tb) | (PRTB_SIZE_SHIFT - 12) | PATB_GR;
398 mmu_partition_table_set_entry(0, dw0, dw1, false);
400 pr_info("Initializing Radix MMU\n");
403 static int __init get_idx_from_shift(unsigned int shift)
424 static int __init radix_dt_scan_page_sizes(unsigned long node,
425 const char *uname, int depth,
432 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
434 /* We are scanning "cpu" nodes only */
435 if (type == NULL || strcmp(type, "cpu") != 0)
438 /* Find MMU PID size */
439 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
440 if (prop && size == 4)
441 mmu_pid_bits = be32_to_cpup(prop);
443 /* Grab page size encodings */
444 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
448 pr_info("Page sizes from device-tree:\n");
449 for (; size >= 4; size -= 4, ++prop) {
451 struct mmu_psize_def *def;
453 /* top 3 bit is AP encoding */
454 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
455 ap = be32_to_cpu(prop[0]) >> 29;
456 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
458 idx = get_idx_from_shift(shift);
462 def = &mmu_psize_defs[idx];
468 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
472 void __init radix__early_init_devtree(void)
477 * Try to find the available page sizes in the device-tree
479 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
480 if (rc != 0) /* Found */
483 * let's assume we have page 4k and 64k support
485 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
486 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
488 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
489 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
494 static void radix_init_amor(void)
497 * In HV mode, we init AMOR (Authority Mask Override Register) so that
498 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
499 * Register), enable key 0 and set it to 1.
501 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
503 mtspr(SPRN_AMOR, (3ul << 62));
506 #ifdef CONFIG_PPC_KUEP
507 void setup_kuep(bool disabled)
509 if (disabled || !early_radix_enabled())
512 if (smp_processor_id() == boot_cpuid)
513 pr_info("Activating Kernel Userspace Execution Prevention\n");
516 * Radix always uses key0 of the IAMR to determine if an access is
517 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
520 mtspr(SPRN_IAMR, (1ul << 62));
524 #ifdef CONFIG_PPC_KUAP
525 void setup_kuap(bool disabled)
527 if (disabled || !early_radix_enabled())
530 if (smp_processor_id() == boot_cpuid) {
531 pr_info("Activating Kernel Userspace Access Prevention\n");
532 cur_cpu_spec->mmu_features |= MMU_FTR_RADIX_KUAP;
535 /* Make sure userspace can't change the AMR */
536 mtspr(SPRN_UAMOR, 0);
537 mtspr(SPRN_AMR, AMR_KUAP_BLOCKED);
542 void __init radix__early_init_mmu(void)
546 #ifdef CONFIG_PPC_64K_PAGES
547 /* PAGE_SIZE mappings */
548 mmu_virtual_psize = MMU_PAGE_64K;
550 mmu_virtual_psize = MMU_PAGE_4K;
553 #ifdef CONFIG_SPARSEMEM_VMEMMAP
554 /* vmemmap mapping */
555 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
557 * map vmemmap using 2M if available
559 mmu_vmemmap_psize = MMU_PAGE_2M;
561 mmu_vmemmap_psize = mmu_virtual_psize;
564 * initialize page table size
566 __pte_index_size = RADIX_PTE_INDEX_SIZE;
567 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
568 __pud_index_size = RADIX_PUD_INDEX_SIZE;
569 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
570 __pud_cache_index = RADIX_PUD_INDEX_SIZE;
571 __pte_table_size = RADIX_PTE_TABLE_SIZE;
572 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
573 __pud_table_size = RADIX_PUD_TABLE_SIZE;
574 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
576 __pmd_val_bits = RADIX_PMD_VAL_BITS;
577 __pud_val_bits = RADIX_PUD_VAL_BITS;
578 __pgd_val_bits = RADIX_PGD_VAL_BITS;
580 __kernel_virt_start = RADIX_KERN_VIRT_START;
581 __vmalloc_start = RADIX_VMALLOC_START;
582 __vmalloc_end = RADIX_VMALLOC_END;
583 __kernel_io_start = RADIX_KERN_IO_START;
584 __kernel_io_end = RADIX_KERN_IO_END;
585 vmemmap = (struct page *)RADIX_VMEMMAP_START;
586 ioremap_bot = IOREMAP_BASE;
589 pci_io_base = ISA_IO_BASE;
591 __pte_frag_nr = RADIX_PTE_FRAG_NR;
592 __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
593 __pmd_frag_nr = RADIX_PMD_FRAG_NR;
594 __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT;
596 radix_init_pgtable();
598 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
599 lpcr = mfspr(SPRN_LPCR);
600 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
601 radix_init_partition_table();
604 radix_init_pseries();
607 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
609 /* Switch to the guard PID before turning on MMU */
610 radix__switch_mmu_context(NULL, &init_mm);
614 void radix__early_init_mmu_secondary(void)
618 * update partition table control register and UPRT
620 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
621 lpcr = mfspr(SPRN_LPCR);
622 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
624 set_ptcr_when_no_uv(__pa(partition_tb) |
625 (PATB_SIZE_SHIFT - 12));
630 radix__switch_mmu_context(NULL, &init_mm);
634 void radix__mmu_cleanup_all(void)
638 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
639 lpcr = mfspr(SPRN_LPCR);
640 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
641 set_ptcr_when_no_uv(0);
642 powernv_set_nmmu_ptcr(0);
643 radix__flush_tlb_all();
647 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
648 phys_addr_t first_memblock_size)
651 * We don't currently support the first MEMBLOCK not mapping 0
652 * physical on those processors
654 BUG_ON(first_memblock_base != 0);
657 * Radix mode is not limited by RMA / VRMA addressing.
659 ppc64_rma_size = ULONG_MAX;
662 #ifdef CONFIG_MEMORY_HOTPLUG
663 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
668 for (i = 0; i < PTRS_PER_PTE; i++) {
674 pte_free_kernel(&init_mm, pte_start);
678 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
683 for (i = 0; i < PTRS_PER_PMD; i++) {
689 pmd_free(&init_mm, pmd_start);
693 struct change_mapping_params {
697 unsigned long aligned_start;
698 unsigned long aligned_end;
701 static int __meminit stop_machine_change_mapping(void *data)
703 struct change_mapping_params *params =
704 (struct change_mapping_params *)data;
709 spin_unlock(&init_mm.page_table_lock);
710 pte_clear(&init_mm, params->aligned_start, params->pte);
711 create_physical_mapping(__pa(params->aligned_start), __pa(params->start), -1);
712 create_physical_mapping(__pa(params->end), __pa(params->aligned_end), -1);
713 spin_lock(&init_mm.page_table_lock);
717 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
723 pte = pte_start + pte_index(addr);
724 for (; addr < end; addr = next, pte++) {
725 next = (addr + PAGE_SIZE) & PAGE_MASK;
729 if (!pte_present(*pte))
732 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
734 * The vmemmap_free() and remove_section_mapping()
735 * codepaths call us with aligned addresses.
737 WARN_ONCE(1, "%s: unaligned range\n", __func__);
741 pte_clear(&init_mm, addr, pte);
746 * clear the pte and potentially split the mapping helper
748 static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end,
749 unsigned long size, pte_t *pte)
751 unsigned long mask = ~(size - 1);
752 unsigned long aligned_start = addr & mask;
753 unsigned long aligned_end = addr + size;
754 struct change_mapping_params params;
755 bool split_region = false;
757 if ((end - addr) < size) {
759 * We're going to clear the PTE, but not flushed
760 * the mapping, time to remap and flush. The
761 * effects if visible outside the processor or
762 * if we are running in code close to the
763 * mapping we cleared, we are in trouble.
765 if (overlaps_kernel_text(aligned_start, addr) ||
766 overlaps_kernel_text(end, aligned_end)) {
768 * Hack, just return, don't pte_clear
770 WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
771 "text, not splitting\n", addr, end);
781 params.aligned_start = addr & ~(size - 1);
782 params.aligned_end = min_t(unsigned long, aligned_end,
783 (unsigned long)__va(memblock_end_of_DRAM()));
784 stop_machine(stop_machine_change_mapping, ¶ms, NULL);
788 pte_clear(&init_mm, addr, pte);
791 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
798 pmd = pmd_start + pmd_index(addr);
799 for (; addr < end; addr = next, pmd++) {
800 next = pmd_addr_end(addr, end);
802 if (!pmd_present(*pmd))
805 if (pmd_is_leaf(*pmd)) {
806 split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
810 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
811 remove_pte_table(pte_base, addr, next);
812 free_pte_table(pte_base, pmd);
816 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
823 pud = pud_start + pud_index(addr);
824 for (; addr < end; addr = next, pud++) {
825 next = pud_addr_end(addr, end);
827 if (!pud_present(*pud))
830 if (pud_is_leaf(*pud)) {
831 split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
835 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
836 remove_pmd_table(pmd_base, addr, next);
837 free_pmd_table(pmd_base, pud);
841 static void __meminit remove_pagetable(unsigned long start, unsigned long end)
843 unsigned long addr, next;
847 spin_lock(&init_mm.page_table_lock);
849 for (addr = start; addr < end; addr = next) {
850 next = pgd_addr_end(addr, end);
852 pgd = pgd_offset_k(addr);
853 if (!pgd_present(*pgd))
856 if (pgd_is_leaf(*pgd)) {
857 split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
861 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
862 remove_pud_table(pud_base, addr, next);
865 spin_unlock(&init_mm.page_table_lock);
866 radix__flush_tlb_kernel_range(start, end);
869 int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid)
871 if (end >= RADIX_VMALLOC_START) {
872 pr_warn("Outside the supported range\n");
876 return create_physical_mapping(__pa(start), __pa(end), nid);
879 int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end)
881 remove_pagetable(start, end);
884 #endif /* CONFIG_MEMORY_HOTPLUG */
886 #ifdef CONFIG_SPARSEMEM_VMEMMAP
887 static int __map_kernel_page_nid(unsigned long ea, unsigned long pa,
888 pgprot_t flags, unsigned int map_page_size,
891 return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0);
894 int __meminit radix__vmemmap_create_mapping(unsigned long start,
895 unsigned long page_size,
898 /* Create a PTE encoding */
899 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
900 int nid = early_pfn_to_nid(phys >> PAGE_SHIFT);
903 if ((start + page_size) >= RADIX_VMEMMAP_END) {
904 pr_warn("Outside the supported range\n");
908 ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid);
914 #ifdef CONFIG_MEMORY_HOTPLUG
915 void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
917 remove_pagetable(start, start + page_size);
922 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
924 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
925 pmd_t *pmdp, unsigned long clr,
930 #ifdef CONFIG_DEBUG_VM
931 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
932 assert_spin_locked(pmd_lockptr(mm, pmdp));
935 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
936 trace_hugepage_update(addr, old, clr, set);
941 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
947 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
948 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
949 VM_BUG_ON(pmd_devmap(*pmdp));
951 * khugepaged calls this for normal pmd
956 /*FIXME!! Verify whether we need this kick below */
957 serialize_against_pte_lookup(vma->vm_mm);
959 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
965 * For us pgtable_t is pte_t *. Inorder to save the deposisted
966 * page table, we consider the allocated page table as a list
967 * head. On withdraw we need to make sure we zero out the used
968 * list_head memory area.
970 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
973 struct list_head *lh = (struct list_head *) pgtable;
975 assert_spin_locked(pmd_lockptr(mm, pmdp));
978 if (!pmd_huge_pte(mm, pmdp))
981 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
982 pmd_huge_pte(mm, pmdp) = pgtable;
985 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
989 struct list_head *lh;
991 assert_spin_locked(pmd_lockptr(mm, pmdp));
994 pgtable = pmd_huge_pte(mm, pmdp);
995 lh = (struct list_head *) pgtable;
997 pmd_huge_pte(mm, pmdp) = NULL;
999 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
1002 ptep = (pte_t *) pgtable;
1009 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
1010 unsigned long addr, pmd_t *pmdp)
1015 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
1016 old_pmd = __pmd(old);
1018 * Serialize against find_current_mm_pte which does lock-less
1019 * lookup in page tables with local interrupts disabled. For huge pages
1020 * it casts pmd_t to pte_t. Since format of pte_t is different from
1021 * pmd_t we want to prevent transit from pmd pointing to page table
1022 * to pmd pointing to huge page (and back) while interrupts are disabled.
1023 * We clear pmd to possibly replace it with page table pointer in
1024 * different code paths. So make sure we wait for the parallel
1025 * find_current_mm_pte to finish.
1027 serialize_against_pte_lookup(mm);
1031 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1033 void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
1034 pte_t entry, unsigned long address, int psize)
1036 struct mm_struct *mm = vma->vm_mm;
1037 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
1038 _PAGE_RW | _PAGE_EXEC);
1040 unsigned long change = pte_val(entry) ^ pte_val(*ptep);
1042 * To avoid NMMU hang while relaxing access, we need mark
1043 * the pte invalid in between.
1045 if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) {
1046 unsigned long old_pte, new_pte;
1048 old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID);
1052 new_pte = old_pte | set;
1053 radix__flush_tlb_page_psize(mm, address, psize);
1054 __radix_pte_update(ptep, _PAGE_INVALID, new_pte);
1056 __radix_pte_update(ptep, 0, set);
1058 * Book3S does not require a TLB flush when relaxing access
1059 * restrictions when the address space is not attached to a
1060 * NMMU, because the core MMU will reload the pte after taking
1061 * an access fault, which is defined by the architectue.
1064 /* See ptesync comment in radix__set_pte_at */
1067 void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
1068 unsigned long addr, pte_t *ptep,
1069 pte_t old_pte, pte_t pte)
1071 struct mm_struct *mm = vma->vm_mm;
1074 * To avoid NMMU hang while relaxing access we need to flush the tlb before
1075 * we set the new value. We need to do this only for radix, because hash
1076 * translation does flush when updating the linux pte.
1078 if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) &&
1079 (atomic_read(&mm->context.copros) > 0))
1080 radix__flush_tlb_page(vma, addr);
1082 set_pte_at(mm, addr, ptep, pte);
1085 int __init arch_ioremap_pud_supported(void)
1087 /* HPT does not cope with large pages in the vmalloc area */
1088 return radix_enabled();
1091 int __init arch_ioremap_pmd_supported(void)
1093 return radix_enabled();
1096 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
1101 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
1103 pte_t *ptep = (pte_t *)pud;
1104 pte_t new_pud = pfn_pte(__phys_to_pfn(addr), prot);
1106 if (!radix_enabled())
1109 set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pud);
1114 int pud_clear_huge(pud_t *pud)
1116 if (pud_huge(*pud)) {
1124 int pud_free_pmd_page(pud_t *pud, unsigned long addr)
1129 pmd = (pmd_t *)pud_page_vaddr(*pud);
1132 flush_tlb_kernel_range(addr, addr + PUD_SIZE);
1134 for (i = 0; i < PTRS_PER_PMD; i++) {
1135 if (!pmd_none(pmd[i])) {
1137 pte = (pte_t *)pmd_page_vaddr(pmd[i]);
1139 pte_free_kernel(&init_mm, pte);
1143 pmd_free(&init_mm, pmd);
1148 int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
1150 pte_t *ptep = (pte_t *)pmd;
1151 pte_t new_pmd = pfn_pte(__phys_to_pfn(addr), prot);
1153 if (!radix_enabled())
1156 set_pte_at(&init_mm, 0 /* radix unused */, ptep, new_pmd);
1161 int pmd_clear_huge(pmd_t *pmd)
1163 if (pmd_huge(*pmd)) {
1171 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
1175 pte = (pte_t *)pmd_page_vaddr(*pmd);
1178 flush_tlb_kernel_range(addr, addr + PMD_SIZE);
1180 pte_free_kernel(&init_mm, pte);
1185 int __init arch_ioremap_p4d_supported(void)