2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
33 #include <asm/xive-regs.h>
34 #include <asm/thread_info.h>
36 /* Sign-extend HDEC if not on POWER9 */
37 #define EXTEND_HDEC(reg) \
40 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
42 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
44 /* Values in HSTATE_NAPPING(r13) */
45 #define NAPPING_CEDE 1
46 #define NAPPING_NOVCPU 2
48 /* Stack frame offsets for kvmppc_hv_entry */
50 #define STACK_SLOT_TRAP (SFS-4)
51 #define STACK_SLOT_TID (SFS-16)
52 #define STACK_SLOT_PSSCR (SFS-24)
53 #define STACK_SLOT_PID (SFS-32)
54 #define STACK_SLOT_IAMR (SFS-40)
55 #define STACK_SLOT_CIABR (SFS-48)
56 #define STACK_SLOT_DAWR (SFS-56)
57 #define STACK_SLOT_DAWRX (SFS-64)
58 #define STACK_SLOT_HFSCR (SFS-72)
61 * Call kvmppc_hv_entry in real mode.
62 * Must be called with interrupts hard-disabled.
66 * LR = return address to continue at after eventually re-enabling MMU
68 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
70 std r0, PPC_LR_STKOFF(r1)
73 std r10, HSTATE_HOST_MSR(r13)
74 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
79 mtmsrd r0,1 /* clear RI in MSR */
86 /* On P9, do LPCR setting, if necessary */
87 ld r3, HSTATE_SPLIT_MODE(r13)
90 lwz r4, KVM_SPLIT_DO_SET(r3)
96 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
98 ld r4, HSTATE_KVM_VCPU(r13)
101 /* Back from guest - restore host state and return to caller */
104 /* Restore host DABR and DABRX */
105 ld r5,HSTATE_DABR(r13)
109 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
112 ld r3,PACA_SPRG_VDSO(r13)
113 mtspr SPRN_SPRG_VDSO_WRITE,r3
115 /* Reload the host's PMU registers */
116 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
117 lbz r4, LPPACA_PMCINUSE(r3)
119 beq 23f /* skip if not */
121 ld r3, HSTATE_MMCR0(r13)
122 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
125 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
126 lwz r3, HSTATE_PMC1(r13)
127 lwz r4, HSTATE_PMC2(r13)
128 lwz r5, HSTATE_PMC3(r13)
129 lwz r6, HSTATE_PMC4(r13)
130 lwz r8, HSTATE_PMC5(r13)
131 lwz r9, HSTATE_PMC6(r13)
138 ld r3, HSTATE_MMCR0(r13)
139 ld r4, HSTATE_MMCR1(r13)
140 ld r5, HSTATE_MMCRA(r13)
141 ld r6, HSTATE_SIAR(r13)
142 ld r7, HSTATE_SDAR(r13)
148 ld r8, HSTATE_MMCR2(r13)
149 ld r9, HSTATE_SIER(r13)
152 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
158 * Reload DEC. HDEC interrupts were disabled when
159 * we reloaded the host's LPCR value.
161 ld r3, HSTATE_DECEXP(r13)
166 /* hwthread_req may have got set by cede or no vcpu, so clear it */
168 stb r0, HSTATE_HWTHREAD_REQ(r13)
171 * For external interrupts we need to call the Linux
172 * handler to process the interrupt. We do that by jumping
173 * to absolute address 0x500 for external interrupts.
174 * The [h]rfid at the end of the handler will return to
175 * the book3s_hv_interrupts.S code. For other interrupts
176 * we do the rfid to get back to the book3s_hv_interrupts.S
179 ld r8, 112+PPC_LR_STKOFF(r1)
181 ld r7, HSTATE_HOST_MSR(r13)
183 /* Return the trap number on this thread as the return value */
187 * If we came back from the guest via a relocation-on interrupt,
188 * we will be in virtual mode at this point, which makes it a
189 * little easier to get back to the caller.
192 andi. r0, r0, MSR_IR /* in real mode? */
195 /* RFI into the highmem handler */
199 mtmsrd r6, 1 /* Clear RI in MSR */
204 /* Virtual-mode return */
209 kvmppc_primary_no_guest:
210 /* We handle this much like a ceded vcpu */
211 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
212 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
213 /* HDEC value came from DEC in the first place, it will fit */
217 * Make sure the primary has finished the MMU switch.
218 * We should never get here on a secondary thread, but
219 * check it for robustness' sake.
221 ld r5, HSTATE_KVM_VCORE(r13)
222 65: lbz r0, VCORE_IN_GUEST(r5)
229 /* set our bit in napping_threads */
230 ld r5, HSTATE_KVM_VCORE(r13)
231 lbz r7, HSTATE_PTID(r13)
234 addi r6, r5, VCORE_NAPPING_THREADS
239 /* order napping_threads update vs testing entry_exit_map */
242 lwz r7, VCORE_ENTRY_EXIT(r5)
244 bge kvm_novcpu_exit /* another thread already exiting */
245 li r3, NAPPING_NOVCPU
246 stb r3, HSTATE_NAPPING(r13)
248 li r3, 0 /* Don't wake on privileged (OS) doorbell */
253 * Entered from kvm_start_guest if kvm_hstate.napping is set
259 ld r1, HSTATE_HOST_R1(r13)
260 ld r5, HSTATE_KVM_VCORE(r13)
262 stb r0, HSTATE_NAPPING(r13)
264 /* check the wake reason */
265 bl kvmppc_check_wake_reason
268 * Restore volatile registers since we could have called
269 * a C routine in kvmppc_check_wake_reason.
272 ld r5, HSTATE_KVM_VCORE(r13)
274 /* see if any other thread is already exiting */
275 lwz r0, VCORE_ENTRY_EXIT(r5)
279 /* clear our bit in napping_threads */
280 lbz r7, HSTATE_PTID(r13)
283 addi r6, r5, VCORE_NAPPING_THREADS
289 /* See if the wake reason means we need to exit */
293 /* See if our timeslice has expired (HDEC is negative) */
296 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
300 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
301 ld r4, HSTATE_KVM_VCPU(r13)
303 beq kvmppc_primary_no_guest
305 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
306 addi r3, r4, VCPU_TB_RMENTRY
307 bl kvmhv_start_timing
312 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
313 ld r4, HSTATE_KVM_VCPU(r13)
316 addi r3, r4, VCPU_TB_RMEXIT
317 bl kvmhv_accumulate_time
320 stw r12, STACK_SLOT_TRAP(r1)
321 bl kvmhv_commence_exit
323 b kvmhv_switch_to_host
326 * We come in here when wakened from nap mode.
327 * Relocation is off and most register values are lost.
328 * r13 points to the PACA.
329 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
331 .globl kvm_start_guest
333 /* Set runlatch bit the minute you wake up from nap */
339 * Could avoid this and pass it through in r3. For now,
340 * code expects it to be in SRR1.
346 li r0,KVM_HWTHREAD_IN_KVM
347 stb r0,HSTATE_HWTHREAD_STATE(r13)
349 /* NV GPR values from power7_idle() will no longer be valid */
351 stb r0,PACA_NAPSTATELOST(r13)
353 /* were we napping due to cede? */
354 lbz r0,HSTATE_NAPPING(r13)
355 cmpwi r0,NAPPING_CEDE
357 cmpwi r0,NAPPING_NOVCPU
358 beq kvm_novcpu_wakeup
360 ld r1,PACAEMERGSP(r13)
361 subi r1,r1,STACK_FRAME_OVERHEAD
364 * We weren't napping due to cede, so this must be a secondary
365 * thread being woken up to run a guest, or being woken up due
366 * to a stray IPI. (Or due to some machine check or hypervisor
367 * maintenance interrupt while the core is in KVM.)
370 /* Check the wake reason in SRR1 to see why we got here */
371 bl kvmppc_check_wake_reason
373 * kvmppc_check_wake_reason could invoke a C routine, but we
374 * have no volatile registers to restore when we return.
380 /* get vcore pointer, NULL if we have nothing to run */
381 ld r5,HSTATE_KVM_VCORE(r13)
383 /* if we have no vcore to run, go back to sleep */
386 kvm_secondary_got_guest:
388 /* Set HSTATE_DSCR(r13) to something sensible */
389 ld r6, PACA_DSCR_DEFAULT(r13)
390 std r6, HSTATE_DSCR(r13)
392 /* On thread 0 of a subcore, set HDEC to max */
393 lbz r4, HSTATE_PTID(r13)
396 LOAD_REG_ADDR(r6, decrementer_max)
399 /* and set per-LPAR registers, if doing dynamic micro-threading */
400 ld r6, HSTATE_SPLIT_MODE(r13)
404 ld r0, KVM_SPLIT_RPR(r6)
406 ld r0, KVM_SPLIT_PMMAR(r6)
408 ld r0, KVM_SPLIT_LDBAR(r6)
412 /* On P9 we use the split_info for coordinating LPCR changes */
413 lwz r4, KVM_SPLIT_DO_SET(r6)
420 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
422 /* Order load of vcpu after load of vcore */
424 ld r4, HSTATE_KVM_VCPU(r13)
427 /* Back from the guest, go back to nap */
428 /* Clear our vcpu and vcore pointers so we don't come back in early */
430 std r0, HSTATE_KVM_VCPU(r13)
432 * Once we clear HSTATE_KVM_VCORE(r13), the code in
433 * kvmppc_run_core() is going to assume that all our vcpu
434 * state is visible in memory. This lwsync makes sure
438 std r0, HSTATE_KVM_VCORE(r13)
441 * All secondaries exiting guest will fall through this path.
442 * Before proceeding, just check for HMI interrupt and
443 * invoke opal hmi handler. By now we are sure that the
444 * primary thread on this core/subcore has already made partition
445 * switch/TB resync and we are good to call opal hmi handler.
447 cmpwi r12, BOOK3S_INTERRUPT_HMI
450 li r3,0 /* NULL argument */
451 bl hmi_exception_realmode
453 * At this point we have finished executing in the guest.
454 * We need to wait for hwthread_req to become zero, since
455 * we may not turn on the MMU while hwthread_req is non-zero.
456 * While waiting we also need to check if we get given a vcpu to run.
459 lbz r3, HSTATE_HWTHREAD_REQ(r13)
463 li r0, KVM_HWTHREAD_IN_KERNEL
464 stb r0, HSTATE_HWTHREAD_STATE(r13)
465 /* need to recheck hwthread_req after a barrier, to avoid race */
467 lbz r3, HSTATE_HWTHREAD_REQ(r13)
471 * We jump to pnv_wakeup_loss, which will return to the caller
472 * of power7_nap in the powernv cpu offline loop. The value we
473 * put in r3 becomes the return value for power7_nap. pnv_wakeup_loss
474 * requires SRR1 in r12.
478 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
485 ld r5, HSTATE_KVM_VCORE(r13)
488 ld r3, HSTATE_SPLIT_MODE(r13)
491 lwz r0, KVM_SPLIT_DO_SET(r3)
494 lwz r0, KVM_SPLIT_DO_RESTORE(r3)
497 lbz r0, KVM_SPLIT_DO_NAP(r3)
503 b kvm_secondary_got_guest
505 54: li r0, KVM_HWTHREAD_IN_KVM
506 stb r0, HSTATE_HWTHREAD_STATE(r13)
510 /* Set LPCR, LPIDR etc. on P9 */
518 bl kvmhv_p9_restore_lpcr
523 * Here the primary thread is trying to return the core to
524 * whole-core mode, so we need to nap.
528 * When secondaries are napping in kvm_unsplit_nap() with
529 * hwthread_req = 1, HMI goes ignored even though subcores are
530 * already exited the guest. Hence HMI keeps waking up secondaries
531 * from nap in a loop and secondaries always go back to nap since
532 * no vcore is assigned to them. This makes impossible for primary
533 * thread to get hold of secondary threads resulting into a soft
534 * lockup in KVM path.
536 * Let us check if HMI is pending and handle it before we go to nap.
538 cmpwi r12, BOOK3S_INTERRUPT_HMI
540 li r3, 0 /* NULL argument */
541 bl hmi_exception_realmode
544 * Ensure that secondary doesn't nap when it has
545 * its vcore pointer set.
547 sync /* matches smp_mb() before setting split_info.do_nap */
548 ld r0, HSTATE_KVM_VCORE(r13)
551 /* clear any pending message */
553 lis r6, (PPC_DBELL_SERVER << (63-36))@h
555 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
556 /* Set kvm_split_mode.napped[tid] = 1 */
557 ld r3, HSTATE_SPLIT_MODE(r13)
559 lbz r4, HSTATE_TID(r13)
560 addi r4, r4, KVM_SPLIT_NAPPED
562 /* Check the do_nap flag again after setting napped[] */
564 lbz r0, KVM_SPLIT_DO_NAP(r3)
567 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
569 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
576 /******************************************************************************
580 *****************************************************************************/
582 .global kvmppc_hv_entry
587 * R4 = vcpu pointer (or NULL)
592 * all other volatile GPRS = free
593 * Does not preserve non-volatile GPRs or CR fields
596 std r0, PPC_LR_STKOFF(r1)
599 /* Save R1 in the PACA */
600 std r1, HSTATE_HOST_R1(r13)
602 li r6, KVM_GUEST_MODE_HOST_HV
603 stb r6, HSTATE_IN_GUEST(r13)
605 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
606 /* Store initial timestamp */
609 addi r3, r4, VCPU_TB_RMENTRY
610 bl kvmhv_start_timing
614 /* Use cr7 as an indication of radix mode */
615 ld r5, HSTATE_KVM_VCORE(r13)
616 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
617 lbz r0, KVM_RADIX(r9)
621 * POWER7/POWER8 host -> guest partition switch code.
622 * We don't have to lock against concurrent tlbies,
623 * but we do have to coordinate across hardware threads.
625 /* Set bit in entry map iff exit map is zero. */
627 lbz r6, HSTATE_PTID(r13)
629 addi r8, r5, VCORE_ENTRY_EXIT
631 cmpwi r3, 0x100 /* any threads starting to exit? */
632 bge secondary_too_late /* if so we're too late to the party */
637 /* Primary thread switches to guest partition. */
643 li r0,LPID_RSVD /* switch to reserved LPID */
646 mtspr SPRN_SDR1,r6 /* switch to partition page table */
647 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
651 /* See if we need to flush the TLB */
652 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
655 * On POWER9, individual threads can come in here, but the
656 * TLB is shared between the 4 threads in a core, hence
657 * invalidating on one thread invalidates for all.
658 * Thus we make all 4 threads use the same bit here.
661 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
662 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
663 srdi r6,r6,6 /* doubleword number */
664 sldi r6,r6,3 /* address offset */
666 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
672 /* Flush the TLB of any entries for this LPID */
673 lwz r0,KVM_TLB_SETS(r9)
675 li r7,0x800 /* IS field = 0b10 */
677 li r0,0 /* RS for P9 version of tlbiel */
679 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
683 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
687 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
692 /* Add timebase offset onto timebase */
693 22: ld r8,VCORE_TB_OFFSET(r5)
696 mftb r6 /* current host timebase */
698 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
699 mftb r7 /* check if lower 24 bits overflowed */
704 addis r8,r8,0x100 /* if so, increment upper 40 bits */
707 /* Load guest PCR value to select appropriate compat mode */
708 37: ld r7, VCORE_PCR(r5)
715 /* DPDES and VTB are shared between threads */
716 ld r8, VCORE_DPDES(r5)
720 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
722 /* Mark the subcore state as inside guest */
723 bl kvmppc_subcore_enter_guest
725 ld r5, HSTATE_KVM_VCORE(r13)
726 ld r4, HSTATE_KVM_VCPU(r13)
728 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
730 /* Do we have a guest vcpu to run? */
732 beq kvmppc_primary_no_guest
734 /* Increment yield count if they have a VPA */
738 li r6, LPPACA_YIELDCOUNT
743 stb r6, VCPU_VPA_DIRTY(r4)
746 /* Save purr/spurr */
749 std r5,HSTATE_PURR(r13)
750 std r6,HSTATE_SPURR(r13)
756 /* Save host values of some registers */
762 std r5, STACK_SLOT_TID(r1)
763 std r6, STACK_SLOT_PSSCR(r1)
764 std r7, STACK_SLOT_PID(r1)
765 std r8, STACK_SLOT_IAMR(r1)
767 std r5, STACK_SLOT_HFSCR(r1)
768 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
773 std r5, STACK_SLOT_CIABR(r1)
774 std r6, STACK_SLOT_DAWR(r1)
775 std r7, STACK_SLOT_DAWRX(r1)
776 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
779 /* Set partition DABR */
780 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
781 lwz r5,VCPU_DABRX(r4)
786 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
788 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
791 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
794 END_FTR_SECTION_IFSET(CPU_FTR_TM)
797 /* Load guest PMU registers */
798 /* R4 is live here (vcpu pointer) */
800 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
801 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
805 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
808 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
809 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
810 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
811 lwz r6, VCPU_PMC + 8(r4)
812 lwz r7, VCPU_PMC + 12(r4)
813 lwz r8, VCPU_PMC + 16(r4)
814 lwz r9, VCPU_PMC + 20(r4)
822 ld r5, VCPU_MMCR + 8(r4)
823 ld r6, VCPU_MMCR + 16(r4)
831 ld r5, VCPU_MMCR + 24(r4)
835 BEGIN_FTR_SECTION_NESTED(96)
836 lwz r7, VCPU_PMC + 24(r4)
837 lwz r8, VCPU_PMC + 28(r4)
838 ld r9, VCPU_MMCR + 32(r4)
842 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
843 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
847 /* Load up FP, VMX and VSX registers */
850 ld r14, VCPU_GPR(R14)(r4)
851 ld r15, VCPU_GPR(R15)(r4)
852 ld r16, VCPU_GPR(R16)(r4)
853 ld r17, VCPU_GPR(R17)(r4)
854 ld r18, VCPU_GPR(R18)(r4)
855 ld r19, VCPU_GPR(R19)(r4)
856 ld r20, VCPU_GPR(R20)(r4)
857 ld r21, VCPU_GPR(R21)(r4)
858 ld r22, VCPU_GPR(R22)(r4)
859 ld r23, VCPU_GPR(R23)(r4)
860 ld r24, VCPU_GPR(R24)(r4)
861 ld r25, VCPU_GPR(R25)(r4)
862 ld r26, VCPU_GPR(R26)(r4)
863 ld r27, VCPU_GPR(R27)(r4)
864 ld r28, VCPU_GPR(R28)(r4)
865 ld r29, VCPU_GPR(R29)(r4)
866 ld r30, VCPU_GPR(R30)(r4)
867 ld r31, VCPU_GPR(R31)(r4)
869 /* Switch DSCR to guest value */
874 /* Skip next section on POWER7 */
876 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
877 /* Load up POWER8-specific registers */
879 lwz r6, VCPU_PSPB(r4)
885 ld r6, VCPU_DAWRX(r4)
886 ld r7, VCPU_CIABR(r4)
893 ld r8, VCPU_EBBHR(r4)
896 ld r5, VCPU_EBBRR(r4)
897 ld r6, VCPU_BESCR(r4)
898 lwz r7, VCPU_GUEST_PID(r4)
906 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
908 /* POWER8-only registers */
909 ld r5, VCPU_TCSCR(r4)
911 ld r7, VCPU_CSIGR(r4)
918 /* POWER9-only registers */
920 ld r6, VCPU_PSSCR(r4)
921 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
922 ld r7, VCPU_HFSCR(r4)
926 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
930 * Set the decrementer to the guest decrementer.
932 ld r8,VCPU_DEC_EXPIRES(r4)
933 /* r8 is a host timebase value here, convert to guest TB */
934 ld r5,HSTATE_KVM_VCORE(r13)
935 ld r6,VCORE_TB_OFFSET(r5)
941 ld r5, VCPU_SPRG0(r4)
942 ld r6, VCPU_SPRG1(r4)
943 ld r7, VCPU_SPRG2(r4)
944 ld r8, VCPU_SPRG3(r4)
950 /* Load up DAR and DSISR */
952 lwz r6, VCPU_DSISR(r4)
956 /* Restore AMR and UAMOR, set AMOR to all 1s */
964 /* Restore state of CTRL run bit; assume 1 on entry */
972 /* Secondary threads wait for primary to have done partition switch */
973 ld r5, HSTATE_KVM_VCORE(r13)
974 lbz r6, HSTATE_PTID(r13)
977 lbz r0, VCORE_IN_GUEST(r5)
981 20: lwz r3, VCORE_ENTRY_EXIT(r5)
984 lbz r0, VCORE_IN_GUEST(r5)
994 /* Check if HDEC expires soon */
997 cmpdi r3, 512 /* 1 microsecond */
1000 /* For hash guest, clear out and reload the SLB */
1002 lbz r0, KVM_RADIX(r6)
1010 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
1011 lwz r5,VCPU_SLB_MAX(r4)
1016 1: ld r8,VCPU_SLB_E(r6)
1017 ld r9,VCPU_SLB_V(r6)
1019 addi r6,r6,VCPU_SLB_SIZE
1023 #ifdef CONFIG_KVM_XICS
1024 /* We are entering the guest on that thread, push VCPU to XIVE */
1025 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1028 ld r11, VCPU_XIVE_SAVED_STATE(r4)
1032 lwz r11, VCPU_XIVE_CAM_WORD(r4)
1033 li r9, TM_QW1_OS + TM_WORD2
1036 stb r9, VCPU_XIVE_PUSHED(r4)
1040 * We clear the irq_pending flag. There is a small chance of a
1041 * race vs. the escalation interrupt happening on another
1042 * processor setting it again, but the only consequence is to
1043 * cause a spurrious wakeup on the next H_CEDE which is not an
1047 stb r0, VCPU_IRQ_PENDING(r4)
1050 * In single escalation mode, if the escalation interrupt is
1053 lbz r0, VCPU_XIVE_ESC_ON(r4)
1056 ld r10, VCPU_XIVE_ESC_RADDR(r4)
1057 li r9, XIVE_ESB_SET_PQ_01
1061 /* We have a possible subtle race here: The escalation interrupt might
1062 * have fired and be on its way to the host queue while we mask it,
1063 * and if we unmask it early enough (re-cede right away), there is
1064 * a theorical possibility that it fires again, thus landing in the
1065 * target queue more than once which is a big no-no.
1067 * Fortunately, solving this is rather easy. If the above load setting
1068 * PQ to 01 returns a previous value where P is set, then we know the
1069 * escalation interrupt is somewhere on its way to the host. In that
1070 * case we simply don't clear the xive_esc_on flag below. It will be
1071 * eventually cleared by the handler for the escalation interrupt.
1073 * Then, when doing a cede, we check that flag again before re-enabling
1074 * the escalation interrupt, and if set, we abort the cede.
1076 andi. r0, r0, XIVE_ESB_VAL_P
1079 /* Now P is 0, we can clear the flag */
1081 stb r0, VCPU_XIVE_ESC_ON(r4)
1084 #endif /* CONFIG_KVM_XICS */
1086 deliver_guest_interrupt:
1093 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
1095 ld r11, VCPU_MSR(r4)
1096 ld r6, VCPU_SRR0(r4)
1097 ld r7, VCPU_SRR1(r4)
1101 /* r11 = vcpu->arch.msr & ~MSR_HV */
1102 rldicl r11, r11, 63 - MSR_HV_LG, 1
1103 rotldi r11, r11, 1 + MSR_HV_LG
1104 ori r11, r11, MSR_ME
1106 /* Check if we can deliver an external or decrementer interrupt now */
1107 ld r0, VCPU_PENDING_EXC(r4)
1108 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1110 andi. r8, r11, MSR_EE
1112 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1113 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1117 li r0, BOOK3S_INTERRUPT_EXTERNAL
1121 /* On POWER9 check whether the guest has large decrementer enabled */
1122 andis. r8, r8, LPCR_LD@h
1124 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1127 li r0, BOOK3S_INTERRUPT_DECREMENTER
1130 12: mtspr SPRN_SRR0, r10
1132 mtspr SPRN_SRR1, r11
1134 bl kvmppc_msr_interrupt
1138 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1139 /* On POWER9, check for pending doorbell requests */
1140 lbz r0, VCPU_DBELL_REQ(r4)
1142 beq fast_guest_return
1143 ld r5, HSTATE_KVM_VCORE(r13)
1144 /* Set DPDES register so the CPU will take a doorbell interrupt */
1146 mtspr SPRN_DPDES, r0
1147 std r0, VCORE_DPDES(r5)
1148 /* Make sure other cpus see vcore->dpdes set before dbell req clear */
1150 /* Clear the pending doorbell request */
1152 stb r0, VCPU_DBELL_REQ(r4)
1157 * R10: value for HSRR0
1158 * R11: value for HSRR1
1163 stb r0,VCPU_CEDED(r4) /* cancel cede */
1164 mtspr SPRN_HSRR0,r10
1165 mtspr SPRN_HSRR1,r11
1167 /* Activate guest mode, so faults get handled by KVM */
1168 li r9, KVM_GUEST_MODE_GUEST_HV
1169 stb r9, HSTATE_IN_GUEST(r13)
1171 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1172 /* Accumulate timing */
1173 addi r3, r4, VCPU_TB_GUEST
1174 bl kvmhv_accumulate_time
1180 ld r5, VCPU_CFAR(r4)
1182 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1185 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1192 ld r1, VCPU_GPR(R1)(r4)
1193 ld r2, VCPU_GPR(R2)(r4)
1194 ld r3, VCPU_GPR(R3)(r4)
1195 ld r5, VCPU_GPR(R5)(r4)
1196 ld r6, VCPU_GPR(R6)(r4)
1197 ld r7, VCPU_GPR(R7)(r4)
1198 ld r8, VCPU_GPR(R8)(r4)
1199 ld r9, VCPU_GPR(R9)(r4)
1200 ld r10, VCPU_GPR(R10)(r4)
1201 ld r11, VCPU_GPR(R11)(r4)
1202 ld r12, VCPU_GPR(R12)(r4)
1203 ld r13, VCPU_GPR(R13)(r4)
1207 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1209 /* Move canary into DSISR to check for later */
1212 mtspr SPRN_HDSISR, r0
1213 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1215 ld r0, VCPU_GPR(R0)(r4)
1216 ld r4, VCPU_GPR(R4)(r4)
1222 stw r12, STACK_SLOT_TRAP(r1)
1225 stw r12, VCPU_TRAP(r4)
1226 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1227 addi r3, r4, VCPU_TB_RMEXIT
1228 bl kvmhv_accumulate_time
1230 11: b kvmhv_switch_to_host
1237 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1238 12: stw r12, VCPU_TRAP(r4)
1240 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1241 addi r3, r4, VCPU_TB_RMEXIT
1242 bl kvmhv_accumulate_time
1246 /******************************************************************************
1250 *****************************************************************************/
1253 * We come here from the first-level interrupt handlers.
1255 .globl kvmppc_interrupt_hv
1256 kvmppc_interrupt_hv:
1258 * Register contents:
1259 * R12 = (guest CR << 32) | interrupt vector
1261 * guest R12 saved in shadow VCPU SCRATCH0
1262 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1263 * guest R13 saved in SPRN_SCRATCH0
1265 std r9, HSTATE_SCRATCH2(r13)
1266 lbz r9, HSTATE_IN_GUEST(r13)
1267 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1268 beq kvmppc_bad_host_intr
1269 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1270 cmpwi r9, KVM_GUEST_MODE_GUEST
1271 ld r9, HSTATE_SCRATCH2(r13)
1272 beq kvmppc_interrupt_pr
1274 /* We're now back in the host but in guest MMU context */
1275 li r9, KVM_GUEST_MODE_HOST_HV
1276 stb r9, HSTATE_IN_GUEST(r13)
1278 ld r9, HSTATE_KVM_VCPU(r13)
1280 /* Save registers */
1282 std r0, VCPU_GPR(R0)(r9)
1283 std r1, VCPU_GPR(R1)(r9)
1284 std r2, VCPU_GPR(R2)(r9)
1285 std r3, VCPU_GPR(R3)(r9)
1286 std r4, VCPU_GPR(R4)(r9)
1287 std r5, VCPU_GPR(R5)(r9)
1288 std r6, VCPU_GPR(R6)(r9)
1289 std r7, VCPU_GPR(R7)(r9)
1290 std r8, VCPU_GPR(R8)(r9)
1291 ld r0, HSTATE_SCRATCH2(r13)
1292 std r0, VCPU_GPR(R9)(r9)
1293 std r10, VCPU_GPR(R10)(r9)
1294 std r11, VCPU_GPR(R11)(r9)
1295 ld r3, HSTATE_SCRATCH0(r13)
1296 std r3, VCPU_GPR(R12)(r9)
1297 /* CR is in the high half of r12 */
1301 ld r3, HSTATE_CFAR(r13)
1302 std r3, VCPU_CFAR(r9)
1303 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1305 ld r4, HSTATE_PPR(r13)
1306 std r4, VCPU_PPR(r9)
1307 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1309 /* Restore R1/R2 so we can handle faults */
1310 ld r1, HSTATE_HOST_R1(r13)
1313 mfspr r10, SPRN_SRR0
1314 mfspr r11, SPRN_SRR1
1315 std r10, VCPU_SRR0(r9)
1316 std r11, VCPU_SRR1(r9)
1317 /* trap is in the low half of r12, clear CR from the high half */
1319 andi. r0, r12, 2 /* need to read HSRR0/1? */
1321 mfspr r10, SPRN_HSRR0
1322 mfspr r11, SPRN_HSRR1
1324 1: std r10, VCPU_PC(r9)
1325 std r11, VCPU_MSR(r9)
1329 std r3, VCPU_GPR(R13)(r9)
1332 stw r12,VCPU_TRAP(r9)
1335 * Now that we have saved away SRR0/1 and HSRR0/1,
1336 * interrupts are recoverable in principle, so set MSR_RI.
1337 * This becomes important for relocation-on interrupts from
1338 * the guest, which we can get in radix mode on POWER9.
1343 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1344 addi r3, r9, VCPU_TB_RMINTR
1346 bl kvmhv_accumulate_time
1347 ld r5, VCPU_GPR(R5)(r9)
1348 ld r6, VCPU_GPR(R6)(r9)
1349 ld r7, VCPU_GPR(R7)(r9)
1350 ld r8, VCPU_GPR(R8)(r9)
1353 /* Save HEIR (HV emulation assist reg) in emul_inst
1354 if this is an HEI (HV emulation interrupt, e40) */
1355 li r3,KVM_INST_FETCH_FAILED
1356 stw r3,VCPU_LAST_INST(r9)
1357 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1360 11: stw r3,VCPU_HEIR(r9)
1362 /* these are volatile across C function calls */
1363 #ifdef CONFIG_RELOCATABLE
1364 ld r3, HSTATE_SCRATCH1(r13)
1370 std r3, VCPU_CTR(r9)
1371 std r4, VCPU_XER(r9)
1373 /* If this is a page table miss then see if it's theirs or ours */
1374 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1376 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1379 /* See if this is a leftover HDEC interrupt */
1380 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1386 bge fast_guest_return
1388 /* See if this is an hcall we can handle in real mode */
1389 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1390 beq hcall_try_real_mode
1392 /* Hypervisor doorbell - exit only if host IPI flag set */
1393 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1398 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1399 lbz r0, HSTATE_HOST_IPI(r13)
1404 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1405 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1407 mfspr r3, SPRN_HFSCR
1408 std r3, VCPU_HFSCR(r9)
1411 /* External interrupt ? */
1412 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1413 bne+ guest_exit_cont
1415 /* External interrupt, first check for host_ipi. If this is
1416 * set, we know the host wants us out so let's do it now
1421 * Restore the active volatile registers after returning from
1424 ld r9, HSTATE_KVM_VCPU(r13)
1425 li r12, BOOK3S_INTERRUPT_EXTERNAL
1428 * kvmppc_read_intr return codes:
1430 * Exit to host (r3 > 0)
1431 * 1 An interrupt is pending that needs to be handled by the host
1432 * Exit guest and return to host by branching to guest_exit_cont
1434 * 2 Passthrough that needs completion in the host
1435 * Exit guest and return to host by branching to guest_exit_cont
1436 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1437 * to indicate to the host to complete handling the interrupt
1439 * Before returning to guest, we check if any CPU is heading out
1440 * to the host and if so, we head out also. If no CPUs are heading
1441 * check return values <= 0.
1443 * Return to guest (r3 <= 0)
1444 * 0 No external interrupt is pending
1445 * -1 A guest wakeup IPI (which has now been cleared)
1446 * In either case, we return to guest to deliver any pending
1449 * -2 A PCI passthrough external interrupt was handled
1450 * (interrupt was delivered directly to guest)
1451 * Return to guest to deliver any pending guest interrupts.
1457 /* Return code = 2 */
1458 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1459 stw r12, VCPU_TRAP(r9)
1462 1: /* Return code <= 1 */
1466 /* Return code <= 0 */
1467 4: ld r5, HSTATE_KVM_VCORE(r13)
1468 lwz r0, VCORE_ENTRY_EXIT(r5)
1471 blt deliver_guest_interrupt
1473 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1474 /* Save more register state */
1477 std r6, VCPU_DAR(r9)
1478 stw r7, VCPU_DSISR(r9)
1479 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1480 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1482 std r6, VCPU_FAULT_DAR(r9)
1483 stw r7, VCPU_FAULT_DSISR(r9)
1485 /* See if it is a machine check */
1486 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1487 beq machine_check_realmode
1489 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1490 addi r3, r9, VCPU_TB_RMEXIT
1492 bl kvmhv_accumulate_time
1494 #ifdef CONFIG_KVM_XICS
1495 /* We are exiting, pull the VP from the XIVE */
1496 lbz r0, VCPU_XIVE_PUSHED(r9)
1499 li r7, TM_SPC_PULL_OS_CTX
1502 andi. r0, r0, MSR_DR /* in real mode? */
1504 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1507 /* First load to pull the context, we ignore the value */
1510 /* Second load to recover the context state (Words 0 and 1) */
1513 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1516 /* First load to pull the context, we ignore the value */
1519 /* Second load to recover the context state (Words 0 and 1) */
1521 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1522 /* Fixup some of the state for the next load */
1525 stb r10, VCPU_XIVE_PUSHED(r9)
1526 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1527 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1530 #endif /* CONFIG_KVM_XICS */
1532 /* For hash guest, read the guest SLB and save it away */
1534 lbz r0, KVM_RADIX(r5)
1537 bne 3f /* for radix, save 0 entries */
1538 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1543 andis. r0,r8,SLB_ESID_V@h
1545 add r8,r8,r6 /* put index in */
1547 std r8,VCPU_SLB_E(r7)
1548 std r3,VCPU_SLB_V(r7)
1549 addi r7,r7,VCPU_SLB_SIZE
1553 /* Finally clear out the SLB */
1558 3: stw r5,VCPU_SLB_MAX(r9)
1560 /* load host SLB entries */
1561 BEGIN_MMU_FTR_SECTION
1563 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1564 ld r8,PACA_SLBSHADOWPTR(r13)
1566 .rept SLB_NUM_BOLTED
1567 li r3, SLBSHADOW_SAVEAREA
1571 andis. r7,r5,SLB_ESID_V@h
1579 stw r12, STACK_SLOT_TRAP(r1)
1581 /* Increment exit count, poke other threads to exit */
1582 bl kvmhv_commence_exit
1584 ld r9, HSTATE_KVM_VCPU(r13)
1586 /* Stop others sending VCPU interrupts to this physical CPU */
1588 stw r0, VCPU_CPU(r9)
1589 stw r0, VCPU_THREAD_CPU(r9)
1591 /* Save guest CTRL register, set runlatch to 1 */
1593 stw r6,VCPU_CTRL(r9)
1600 * Save the guest PURR/SPURR
1605 ld r8,VCPU_SPURR(r9)
1606 std r5,VCPU_PURR(r9)
1607 std r6,VCPU_SPURR(r9)
1612 * Restore host PURR/SPURR and add guest times
1613 * so that the time in the guest gets accounted.
1615 ld r3,HSTATE_PURR(r13)
1616 ld r4,HSTATE_SPURR(r13)
1623 ld r3, HSTATE_KVM_VCORE(r13)
1626 /* On P9, if the guest has large decr enabled, don't sign extend */
1628 ld r4, VCORE_LPCR(r3)
1629 andis. r4, r4, LPCR_LD@h
1631 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1634 /* r5 is a guest timebase value here, convert to host TB */
1635 ld r4,VCORE_TB_OFFSET(r3)
1637 std r5,VCPU_DEC_EXPIRES(r9)
1641 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1642 /* Save POWER8-specific registers */
1646 std r5, VCPU_IAMR(r9)
1647 stw r6, VCPU_PSPB(r9)
1648 std r7, VCPU_FSCR(r9)
1652 std r7, VCPU_TAR(r9)
1653 mfspr r8, SPRN_EBBHR
1654 std r8, VCPU_EBBHR(r9)
1655 mfspr r5, SPRN_EBBRR
1656 mfspr r6, SPRN_BESCR
1659 std r5, VCPU_EBBRR(r9)
1660 std r6, VCPU_BESCR(r9)
1661 stw r7, VCPU_GUEST_PID(r9)
1662 std r8, VCPU_WORT(r9)
1664 mfspr r5, SPRN_TCSCR
1666 mfspr r7, SPRN_CSIGR
1668 std r5, VCPU_TCSCR(r9)
1669 std r6, VCPU_ACOP(r9)
1670 std r7, VCPU_CSIGR(r9)
1671 std r8, VCPU_TACR(r9)
1674 mfspr r6, SPRN_PSSCR
1675 std r5, VCPU_TID(r9)
1676 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1678 std r6, VCPU_PSSCR(r9)
1679 /* Restore host HFSCR value */
1680 ld r7, STACK_SLOT_HFSCR(r1)
1681 mtspr SPRN_HFSCR, r7
1682 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1684 * Restore various registers to 0, where non-zero values
1685 * set by the guest could disrupt the host.
1692 mtspr SPRN_TCSCR, r0
1693 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1696 mtspr SPRN_MMCRS, r0
1697 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1700 /* Save and reset AMR and UAMOR before turning on the MMU */
1704 std r6,VCPU_UAMOR(r9)
1707 mtspr SPRN_UAMOR, r6
1709 /* Switch DSCR back to host value */
1711 ld r7, HSTATE_DSCR(r13)
1712 std r8, VCPU_DSCR(r9)
1715 /* Save non-volatile GPRs */
1716 std r14, VCPU_GPR(R14)(r9)
1717 std r15, VCPU_GPR(R15)(r9)
1718 std r16, VCPU_GPR(R16)(r9)
1719 std r17, VCPU_GPR(R17)(r9)
1720 std r18, VCPU_GPR(R18)(r9)
1721 std r19, VCPU_GPR(R19)(r9)
1722 std r20, VCPU_GPR(R20)(r9)
1723 std r21, VCPU_GPR(R21)(r9)
1724 std r22, VCPU_GPR(R22)(r9)
1725 std r23, VCPU_GPR(R23)(r9)
1726 std r24, VCPU_GPR(R24)(r9)
1727 std r25, VCPU_GPR(R25)(r9)
1728 std r26, VCPU_GPR(R26)(r9)
1729 std r27, VCPU_GPR(R27)(r9)
1730 std r28, VCPU_GPR(R28)(r9)
1731 std r29, VCPU_GPR(R29)(r9)
1732 std r30, VCPU_GPR(R30)(r9)
1733 std r31, VCPU_GPR(R31)(r9)
1736 mfspr r3, SPRN_SPRG0
1737 mfspr r4, SPRN_SPRG1
1738 mfspr r5, SPRN_SPRG2
1739 mfspr r6, SPRN_SPRG3
1740 std r3, VCPU_SPRG0(r9)
1741 std r4, VCPU_SPRG1(r9)
1742 std r5, VCPU_SPRG2(r9)
1743 std r6, VCPU_SPRG3(r9)
1749 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1752 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
1755 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1758 /* Increment yield count if they have a VPA */
1759 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1762 li r4, LPPACA_YIELDCOUNT
1767 stb r3, VCPU_VPA_DIRTY(r9)
1769 /* Save PMU registers if requested */
1770 /* r8 and cr0.eq are live here */
1773 * POWER8 seems to have a hardware bug where setting
1774 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1775 * when some counters are already negative doesn't seem
1776 * to cause a performance monitor alert (and hence interrupt).
1777 * The effect of this is that when saving the PMU state,
1778 * if there is no PMU alert pending when we read MMCR0
1779 * before freezing the counters, but one becomes pending
1780 * before we read the counters, we lose it.
1781 * To work around this, we need a way to freeze the counters
1782 * before reading MMCR0. Normally, freezing the counters
1783 * is done by writing MMCR0 (to set MMCR0[FC]) which
1784 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1785 * we can also freeze the counters using MMCR2, by writing
1786 * 1s to all the counter freeze condition bits (there are
1787 * 9 bits each for 6 counters).
1789 li r3, -1 /* set all freeze bits */
1791 mfspr r10, SPRN_MMCR2
1792 mtspr SPRN_MMCR2, r3
1794 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1796 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1797 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1798 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1799 mfspr r6, SPRN_MMCRA
1800 /* Clear MMCRA in order to disable SDAR updates */
1802 mtspr SPRN_MMCRA, r7
1804 beq 21f /* if no VPA, save PMU stuff anyway */
1805 lbz r7, LPPACA_PMCINUSE(r8)
1806 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1808 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1810 21: mfspr r5, SPRN_MMCR1
1813 std r4, VCPU_MMCR(r9)
1814 std r5, VCPU_MMCR + 8(r9)
1815 std r6, VCPU_MMCR + 16(r9)
1817 std r10, VCPU_MMCR + 24(r9)
1818 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1819 std r7, VCPU_SIAR(r9)
1820 std r8, VCPU_SDAR(r9)
1827 stw r3, VCPU_PMC(r9)
1828 stw r4, VCPU_PMC + 4(r9)
1829 stw r5, VCPU_PMC + 8(r9)
1830 stw r6, VCPU_PMC + 12(r9)
1831 stw r7, VCPU_PMC + 16(r9)
1832 stw r8, VCPU_PMC + 20(r9)
1835 std r5, VCPU_SIER(r9)
1836 BEGIN_FTR_SECTION_NESTED(96)
1837 mfspr r6, SPRN_SPMC1
1838 mfspr r7, SPRN_SPMC2
1839 mfspr r8, SPRN_MMCRS
1840 stw r6, VCPU_PMC + 24(r9)
1841 stw r7, VCPU_PMC + 28(r9)
1842 std r8, VCPU_MMCR + 32(r9)
1844 mtspr SPRN_MMCRS, r4
1845 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1846 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1849 /* Restore host values of some registers */
1851 ld r5, STACK_SLOT_CIABR(r1)
1852 ld r6, STACK_SLOT_DAWR(r1)
1853 ld r7, STACK_SLOT_DAWRX(r1)
1854 mtspr SPRN_CIABR, r5
1856 mtspr SPRN_DAWRX, r7
1857 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1859 ld r5, STACK_SLOT_TID(r1)
1860 ld r6, STACK_SLOT_PSSCR(r1)
1861 ld r7, STACK_SLOT_PID(r1)
1862 ld r8, STACK_SLOT_IAMR(r1)
1864 mtspr SPRN_PSSCR, r6
1867 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1869 #ifdef CONFIG_PPC_RADIX_MMU
1871 * Are we running hash or radix ?
1874 lbz r0, KVM_RADIX(r5)
1878 /* Radix: Handle the case where the guest used an illegal PID */
1879 LOAD_REG_ADDR(r4, mmu_base_pid)
1880 lwz r3, VCPU_GUEST_PID(r9)
1886 * Illegal PID, the HW might have prefetched and cached in the TLB
1887 * some translations for the LPID 0 / guest PID combination which
1888 * Linux doesn't know about, so we need to flush that PID out of
1889 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1890 * the right context.
1896 /* Then do a congruence class local flush */
1898 lwz r0,KVM_TLB_SETS(r6)
1900 li r7,0x400 /* IS field = 0b01 */
1902 sldi r0,r3,32 /* RS has PID */
1903 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1908 2: /* Flush the ERAT on radix P9 DD1 guest exit */
1911 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1913 #endif /* CONFIG_PPC_RADIX_MMU */
1916 * POWER7/POWER8 guest -> host partition switch code.
1917 * We don't have to lock against tlbies but we do
1918 * have to coordinate the hardware threads.
1919 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1921 kvmhv_switch_to_host:
1922 /* Secondary threads wait for primary to do partition switch */
1923 ld r5,HSTATE_KVM_VCORE(r13)
1924 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1925 lbz r3,HSTATE_PTID(r13)
1929 13: lbz r3,VCORE_IN_GUEST(r5)
1935 /* Primary thread waits for all the secondaries to exit guest */
1936 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1937 rlwinm r0,r3,32-8,0xff
1943 /* Did we actually switch to the guest at all? */
1944 lbz r6, VCORE_IN_GUEST(r5)
1948 /* Primary thread switches back to host partition */
1949 lwz r7,KVM_HOST_LPID(r4)
1951 ld r6,KVM_HOST_SDR1(r4)
1952 li r8,LPID_RSVD /* switch to reserved LPID */
1955 mtspr SPRN_SDR1,r6 /* switch to host page table */
1956 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1961 /* DPDES and VTB are shared between threads */
1962 mfspr r7, SPRN_DPDES
1964 std r7, VCORE_DPDES(r5)
1965 std r8, VCORE_VTB(r5)
1966 /* clear DPDES so we don't get guest doorbells in the host */
1968 mtspr SPRN_DPDES, r8
1969 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1971 /* If HMI, call kvmppc_realmode_hmi_handler() */
1972 lwz r12, STACK_SLOT_TRAP(r1)
1973 cmpwi r12, BOOK3S_INTERRUPT_HMI
1975 bl kvmppc_realmode_hmi_handler
1979 * At this point kvmppc_realmode_hmi_handler may have resync-ed
1980 * the TB, and if it has, we must not subtract the guest timebase
1981 * offset from the timebase. So, skip it.
1983 * Also, do not call kvmppc_subcore_exit_guest() because it has
1984 * been invoked as part of kvmppc_realmode_hmi_handler().
1989 /* Subtract timebase offset from timebase */
1990 ld r8,VCORE_TB_OFFSET(r5)
1993 mftb r6 /* current guest timebase */
1995 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1996 mftb r7 /* check if lower 24 bits overflowed */
2001 addis r8,r8,0x100 /* if so, increment upper 40 bits */
2004 17: bl kvmppc_subcore_exit_guest
2006 30: ld r5,HSTATE_KVM_VCORE(r13)
2007 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
2010 ld r0, VCORE_PCR(r5)
2016 /* Signal secondary CPUs to continue */
2017 stb r0,VCORE_IN_GUEST(r5)
2018 19: lis r8,0x7fff /* MAX_INT@h */
2023 /* On POWER9 with HPT-on-radix we need to wait for all other threads */
2024 ld r3, HSTATE_SPLIT_MODE(r13)
2027 lwz r8, KVM_SPLIT_DO_RESTORE(r3)
2030 bl kvmhv_p9_restore_lpcr
2034 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2035 ld r8,KVM_HOST_LPCR(r4)
2039 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2040 /* Finish timing, if we have a vcpu */
2041 ld r4, HSTATE_KVM_VCPU(r13)
2045 bl kvmhv_accumulate_time
2048 /* Unset guest mode */
2049 li r0, KVM_GUEST_MODE_NONE
2050 stb r0, HSTATE_IN_GUEST(r13)
2052 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
2053 ld r0, SFS+PPC_LR_STKOFF(r1)
2059 * Check whether an HDSI is an HPTE not found fault or something else.
2060 * If it is an HPTE not found fault that is due to the guest accessing
2061 * a page that they have mapped but which we have paged out, then
2062 * we continue on with the guest exit path. In all other cases,
2063 * reflect the HDSI to the guest as a DSI.
2067 lbz r0, KVM_RADIX(r3)
2069 mfspr r6, SPRN_HDSISR
2071 /* Look for DSISR canary. If we find it, retry instruction */
2074 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2076 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
2077 /* HPTE not found fault or protection fault? */
2078 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
2079 beq 1f /* if not, send it to the guest */
2080 andi. r0, r11, MSR_DR /* data relocation enabled? */
2083 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2085 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2087 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2088 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
2089 bne 7f /* if no SLB entry found */
2090 4: std r4, VCPU_FAULT_DAR(r9)
2091 stw r6, VCPU_FAULT_DSISR(r9)
2093 /* Search the hash table. */
2094 mr r3, r9 /* vcpu pointer */
2095 li r7, 1 /* data fault */
2096 bl kvmppc_hpte_hv_fault
2097 ld r9, HSTATE_KVM_VCPU(r13)
2099 ld r11, VCPU_MSR(r9)
2100 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2101 cmpdi r3, 0 /* retry the instruction */
2103 cmpdi r3, -1 /* handle in kernel mode */
2105 cmpdi r3, -2 /* MMIO emulation; need instr word */
2108 /* Synthesize a DSI (or DSegI) for the guest */
2109 ld r4, VCPU_FAULT_DAR(r9)
2111 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2112 mtspr SPRN_DSISR, r6
2113 7: mtspr SPRN_DAR, r4
2114 mtspr SPRN_SRR0, r10
2115 mtspr SPRN_SRR1, r11
2117 bl kvmppc_msr_interrupt
2118 fast_interrupt_c_return:
2119 6: ld r7, VCPU_CTR(r9)
2126 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2127 ld r5, KVM_VRMA_SLB_V(r5)
2130 /* If this is for emulated MMIO, load the instruction word */
2131 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2133 /* Set guest mode to 'jump over instruction' so if lwz faults
2134 * we'll just continue at the next IP. */
2135 li r0, KVM_GUEST_MODE_SKIP
2136 stb r0, HSTATE_IN_GUEST(r13)
2138 /* Do the access with MSR:DR enabled */
2140 ori r4, r3, MSR_DR /* Enable paging for data */
2145 /* Store the result */
2146 stw r8, VCPU_LAST_INST(r9)
2148 /* Unset guest mode. */
2149 li r0, KVM_GUEST_MODE_HOST_HV
2150 stb r0, HSTATE_IN_GUEST(r13)
2154 std r4, VCPU_FAULT_DAR(r9)
2155 stw r6, VCPU_FAULT_DSISR(r9)
2158 std r5, VCPU_FAULT_GPA(r9)
2162 * Similarly for an HISI, reflect it to the guest as an ISI unless
2163 * it is an HPTE not found fault for a page that we have paged out.
2167 lbz r0, KVM_RADIX(r3)
2169 bne .Lradix_hisi /* for radix, just save ASDR */
2170 andis. r0, r11, SRR1_ISI_NOPT@h
2172 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2175 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2177 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2179 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2180 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2181 bne 7f /* if no SLB entry found */
2183 /* Search the hash table. */
2184 mr r3, r9 /* vcpu pointer */
2187 li r7, 0 /* instruction fault */
2188 bl kvmppc_hpte_hv_fault
2189 ld r9, HSTATE_KVM_VCPU(r13)
2191 ld r11, VCPU_MSR(r9)
2192 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2193 cmpdi r3, 0 /* retry the instruction */
2194 beq fast_interrupt_c_return
2195 cmpdi r3, -1 /* handle in kernel mode */
2198 /* Synthesize an ISI (or ISegI) for the guest */
2200 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2201 7: mtspr SPRN_SRR0, r10
2202 mtspr SPRN_SRR1, r11
2204 bl kvmppc_msr_interrupt
2205 b fast_interrupt_c_return
2207 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2208 ld r5, KVM_VRMA_SLB_V(r6)
2212 * Try to handle an hcall in real mode.
2213 * Returns to the guest if we handle it, or continues on up to
2214 * the kernel if we can't (i.e. if we don't have a handler for
2215 * it, or if the handler returns H_TOO_HARD).
2217 * r5 - r8 contain hcall args,
2218 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2220 hcall_try_real_mode:
2221 ld r3,VCPU_GPR(R3)(r9)
2223 /* sc 1 from userspace - reflect to guest syscall */
2224 bne sc_1_fast_return
2226 cmpldi r3,hcall_real_table_end - hcall_real_table
2228 /* See if this hcall is enabled for in-kernel handling */
2230 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2231 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2233 ld r0, KVM_ENABLED_HCALLS(r4)
2234 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2238 /* Get pointer to handler, if any, and call it */
2239 LOAD_REG_ADDR(r4, hcall_real_table)
2245 mr r3,r9 /* get vcpu pointer */
2246 ld r4,VCPU_GPR(R4)(r9)
2249 beq hcall_real_fallback
2250 ld r4,HSTATE_KVM_VCPU(r13)
2251 std r3,VCPU_GPR(R3)(r4)
2259 li r10, BOOK3S_INTERRUPT_SYSCALL
2260 bl kvmppc_msr_interrupt
2264 /* We've attempted a real mode hcall, but it's punted it back
2265 * to userspace. We need to restore some clobbered volatiles
2266 * before resuming the pass-it-to-qemu path */
2267 hcall_real_fallback:
2268 li r12,BOOK3S_INTERRUPT_SYSCALL
2269 ld r9, HSTATE_KVM_VCPU(r13)
2273 .globl hcall_real_table
2275 .long 0 /* 0 - unused */
2276 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2277 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2278 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2279 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2280 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2281 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2282 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2283 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2284 .long 0 /* 0x24 - H_SET_SPRG0 */
2285 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2300 #ifdef CONFIG_KVM_XICS
2301 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2302 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2303 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2304 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2305 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2307 .long 0 /* 0x64 - H_EOI */
2308 .long 0 /* 0x68 - H_CPPR */
2309 .long 0 /* 0x6c - H_IPI */
2310 .long 0 /* 0x70 - H_IPOLL */
2311 .long 0 /* 0x74 - H_XIRR */
2339 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2340 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2356 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2360 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2361 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2362 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2474 #ifdef CONFIG_KVM_XICS
2475 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2477 .long 0 /* 0x2fc - H_XIRR_X*/
2479 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2480 .globl hcall_real_table_end
2481 hcall_real_table_end:
2483 _GLOBAL(kvmppc_h_set_xdabr)
2484 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2486 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2489 6: li r3, H_PARAMETER
2492 _GLOBAL(kvmppc_h_set_dabr)
2493 li r5, DABRX_USER | DABRX_KERNEL
2497 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2498 std r4,VCPU_DABR(r3)
2499 stw r5, VCPU_DABRX(r3)
2500 mtspr SPRN_DABRX, r5
2501 /* Work around P7 bug where DABR can get corrupted on mtspr */
2502 1: mtspr SPRN_DABR,r4
2510 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2511 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2512 rlwimi r5, r4, 2, DAWRX_WT
2514 std r4, VCPU_DAWR(r3)
2515 std r5, VCPU_DAWRX(r3)
2517 mtspr SPRN_DAWRX, r5
2521 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2523 std r11,VCPU_MSR(r3)
2525 stb r0,VCPU_CEDED(r3)
2526 sync /* order setting ceded vs. testing prodded */
2527 lbz r5,VCPU_PRODDED(r3)
2529 bne kvm_cede_prodded
2530 li r12,0 /* set trap to 0 to say hcall is handled */
2531 stw r12,VCPU_TRAP(r3)
2533 std r0,VCPU_GPR(R3)(r3)
2536 * Set our bit in the bitmask of napping threads unless all the
2537 * other threads are already napping, in which case we send this
2540 ld r5,HSTATE_KVM_VCORE(r13)
2541 lbz r6,HSTATE_PTID(r13)
2542 lwz r8,VCORE_ENTRY_EXIT(r5)
2546 addi r6,r5,VCORE_NAPPING_THREADS
2553 /* order napping_threads update vs testing entry_exit_map */
2556 stb r0,HSTATE_NAPPING(r13)
2557 lwz r7,VCORE_ENTRY_EXIT(r5)
2559 bge 33f /* another thread already exiting */
2562 * Although not specifically required by the architecture, POWER7
2563 * preserves the following registers in nap mode, even if an SMT mode
2564 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2565 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2567 /* Save non-volatile GPRs */
2568 std r14, VCPU_GPR(R14)(r3)
2569 std r15, VCPU_GPR(R15)(r3)
2570 std r16, VCPU_GPR(R16)(r3)
2571 std r17, VCPU_GPR(R17)(r3)
2572 std r18, VCPU_GPR(R18)(r3)
2573 std r19, VCPU_GPR(R19)(r3)
2574 std r20, VCPU_GPR(R20)(r3)
2575 std r21, VCPU_GPR(R21)(r3)
2576 std r22, VCPU_GPR(R22)(r3)
2577 std r23, VCPU_GPR(R23)(r3)
2578 std r24, VCPU_GPR(R24)(r3)
2579 std r25, VCPU_GPR(R25)(r3)
2580 std r26, VCPU_GPR(R26)(r3)
2581 std r27, VCPU_GPR(R27)(r3)
2582 std r28, VCPU_GPR(R28)(r3)
2583 std r29, VCPU_GPR(R29)(r3)
2584 std r30, VCPU_GPR(R30)(r3)
2585 std r31, VCPU_GPR(R31)(r3)
2590 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2593 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2595 ld r9, HSTATE_KVM_VCPU(r13)
2597 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2601 * Set DEC to the smaller of DEC and HDEC, so that we wake
2602 * no later than the end of our timeslice (HDEC interrupts
2603 * don't wake us from nap).
2609 /* On P9 check whether the guest has large decrementer mode enabled */
2610 ld r6, HSTATE_KVM_VCORE(r13)
2611 ld r6, VCORE_LPCR(r6)
2612 andis. r6, r6, LPCR_LD@h
2614 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2621 /* save expiry time of guest decrementer */
2623 ld r4, HSTATE_KVM_VCPU(r13)
2624 ld r5, HSTATE_KVM_VCORE(r13)
2625 ld r6, VCORE_TB_OFFSET(r5)
2626 subf r3, r6, r3 /* convert to host TB value */
2627 std r3, VCPU_DEC_EXPIRES(r4)
2629 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2630 ld r4, HSTATE_KVM_VCPU(r13)
2631 addi r3, r4, VCPU_TB_CEDE
2632 bl kvmhv_accumulate_time
2635 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2638 * Take a nap until a decrementer or external or doobell interrupt
2639 * occurs, with PECE1 and PECE0 set in LPCR.
2640 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2641 * Also clear the runlatch bit before napping.
2644 mfspr r0, SPRN_CTRLF
2646 mtspr SPRN_CTRLT, r0
2649 stb r0,HSTATE_HWTHREAD_REQ(r13)
2651 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2653 ori r5, r5, LPCR_PECEDH
2654 rlwimi r5, r3, 0, LPCR_PECEDP
2655 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2657 kvm_nap_sequence: /* desired LPCR value in r5 */
2660 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2661 * enable state loss = 1 (allow SMT mode switch)
2662 * requested level = 0 (just stop dispatching)
2664 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2665 mtspr SPRN_PSSCR, r3
2666 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2667 li r4, LPCR_PECE_HVEE@higher
2670 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2674 std r0, HSTATE_SCRATCH0(r13)
2676 ld r0, HSTATE_SCRATCH0(r13)
2683 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2692 /* get vcpu pointer */
2693 ld r4, HSTATE_KVM_VCPU(r13)
2695 /* Woken by external or decrementer interrupt */
2696 ld r1, HSTATE_HOST_R1(r13)
2698 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2699 addi r3, r4, VCPU_TB_RMINTR
2700 bl kvmhv_accumulate_time
2703 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2706 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR
2708 bl kvmppc_restore_tm
2709 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2712 /* load up FP state */
2715 /* Restore guest decrementer */
2716 ld r3, VCPU_DEC_EXPIRES(r4)
2717 ld r5, HSTATE_KVM_VCORE(r13)
2718 ld r6, VCORE_TB_OFFSET(r5)
2719 add r3, r3, r6 /* convert host TB to guest TB value */
2725 ld r14, VCPU_GPR(R14)(r4)
2726 ld r15, VCPU_GPR(R15)(r4)
2727 ld r16, VCPU_GPR(R16)(r4)
2728 ld r17, VCPU_GPR(R17)(r4)
2729 ld r18, VCPU_GPR(R18)(r4)
2730 ld r19, VCPU_GPR(R19)(r4)
2731 ld r20, VCPU_GPR(R20)(r4)
2732 ld r21, VCPU_GPR(R21)(r4)
2733 ld r22, VCPU_GPR(R22)(r4)
2734 ld r23, VCPU_GPR(R23)(r4)
2735 ld r24, VCPU_GPR(R24)(r4)
2736 ld r25, VCPU_GPR(R25)(r4)
2737 ld r26, VCPU_GPR(R26)(r4)
2738 ld r27, VCPU_GPR(R27)(r4)
2739 ld r28, VCPU_GPR(R28)(r4)
2740 ld r29, VCPU_GPR(R29)(r4)
2741 ld r30, VCPU_GPR(R30)(r4)
2742 ld r31, VCPU_GPR(R31)(r4)
2744 /* Check the wake reason in SRR1 to see why we got here */
2745 bl kvmppc_check_wake_reason
2748 * Restore volatile registers since we could have called a
2749 * C routine in kvmppc_check_wake_reason
2751 * r3 tells us whether we need to return to host or not
2752 * WARNING: it gets checked further down:
2753 * should not modify r3 until this check is done.
2755 ld r4, HSTATE_KVM_VCPU(r13)
2757 /* clear our bit in vcore->napping_threads */
2758 34: ld r5,HSTATE_KVM_VCORE(r13)
2759 lbz r7,HSTATE_PTID(r13)
2762 addi r6,r5,VCORE_NAPPING_THREADS
2768 stb r0,HSTATE_NAPPING(r13)
2770 /* See if the wake reason saved in r3 means we need to exit */
2771 stw r12, VCPU_TRAP(r4)
2776 /* see if any other thread is already exiting */
2777 lwz r0,VCORE_ENTRY_EXIT(r5)
2781 b kvmppc_cede_reentry /* if not go back to guest */
2783 /* cede when already previously prodded case */
2786 stb r0,VCPU_PRODDED(r3)
2787 sync /* order testing prodded vs. clearing ceded */
2788 stb r0,VCPU_CEDED(r3)
2792 /* we've ceded but we want to give control to the host */
2794 ld r9, HSTATE_KVM_VCPU(r13)
2795 #ifdef CONFIG_KVM_XICS
2796 /* Abort if we still have a pending escalation */
2797 lbz r5, VCPU_XIVE_ESC_ON(r9)
2801 stb r0, VCPU_CEDED(r9)
2802 1: /* Enable XIVE escalation */
2803 li r5, XIVE_ESB_SET_PQ_00
2805 andi. r0, r0, MSR_DR /* in real mode? */
2807 ld r10, VCPU_XIVE_ESC_VADDR(r9)
2812 1: ld r10, VCPU_XIVE_ESC_RADDR(r9)
2818 stb r0, VCPU_XIVE_ESC_ON(r9)
2819 #endif /* CONFIG_KVM_XICS */
2820 3: b guest_exit_cont
2822 /* Try to handle a machine check in real mode */
2823 machine_check_realmode:
2824 mr r3, r9 /* get vcpu pointer */
2825 bl kvmppc_realmode_machine_check
2827 ld r9, HSTATE_KVM_VCPU(r13)
2828 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2830 * For the guest that is FWNMI capable, deliver all the MCE errors
2831 * (handled/unhandled) by exiting the guest with KVM_EXIT_NMI exit
2832 * reason. This new approach injects machine check errors in guest
2833 * address space to guest with additional information in the form
2834 * of RTAS event, thus enabling guest kernel to suitably handle
2837 * For the guest that is not FWNMI capable (old QEMU) fallback
2838 * to old behaviour for backward compatibility:
2839 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest either
2840 * through machine check interrupt (set HSRR0 to 0x200).
2841 * For handled errors (no-fatal), just go back to guest execution
2842 * with current HSRR0.
2843 * if we receive machine check with MSR(RI=0) then deliver it to
2844 * guest as machine check causing guest to crash.
2846 ld r11, VCPU_MSR(r9)
2847 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2848 bne mc_cont /* if so, exit to host */
2849 /* Check if guest is capable of handling NMI exit */
2850 ld r10, VCPU_KVM(r9)
2851 lbz r10, KVM_FWNMI(r10)
2852 cmpdi r10, 1 /* FWNMI capable? */
2853 beq mc_cont /* if so, exit with KVM_EXIT_NMI. */
2855 /* if not, fall through for backward compatibility. */
2856 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2857 beq 1f /* Deliver a machine check to guest */
2859 cmpdi r3, 0 /* Did we handle MCE ? */
2860 bne 2f /* Continue guest execution. */
2861 /* If not, deliver a machine check. SRR0/1 are already set */
2862 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2863 bl kvmppc_msr_interrupt
2864 2: b fast_interrupt_c_return
2867 * Check the reason we woke from nap, and take appropriate action.
2869 * 0 if nothing needs to be done
2870 * 1 if something happened that needs to be handled by the host
2871 * -1 if there was a guest wakeup (IPI or msgsnd)
2872 * -2 if we handled a PCI passthrough interrupt (returned by
2873 * kvmppc_read_intr only)
2875 * Also sets r12 to the interrupt vector for any interrupt that needs
2876 * to be handled now by the host (0x500 for external interrupt), or zero.
2877 * Modifies all volatile registers (since it may call a C function).
2878 * This routine calls kvmppc_read_intr, a C function, if an external
2879 * interrupt is pending.
2881 kvmppc_check_wake_reason:
2884 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2886 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2887 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2888 cmpwi r6, 8 /* was it an external interrupt? */
2889 beq 7f /* if so, see what it was */
2892 cmpwi r6, 6 /* was it the decrementer? */
2895 cmpwi r6, 5 /* privileged doorbell? */
2897 cmpwi r6, 3 /* hypervisor doorbell? */
2899 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2900 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2902 li r3, 1 /* anything else, return 1 */
2905 /* hypervisor doorbell */
2906 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2909 * Clear the doorbell as we will invoke the handler
2910 * explicitly in the guest exit path.
2912 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2914 /* see if it's a host IPI */
2919 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2920 lbz r0, HSTATE_HOST_IPI(r13)
2923 /* if not, return -1 */
2927 /* Woken up due to Hypervisor maintenance interrupt */
2928 4: li r12, BOOK3S_INTERRUPT_HMI
2932 /* external interrupt - create a stack frame so we can call C */
2934 std r0, PPC_LR_STKOFF(r1)
2935 stdu r1, -PPC_MIN_STKFRM(r1)
2938 li r12, BOOK3S_INTERRUPT_EXTERNAL
2943 * Return code of 2 means PCI passthrough interrupt, but
2944 * we need to return back to host to complete handling the
2945 * interrupt. Trap reason is expected in r12 by guest
2948 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2950 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2951 addi r1, r1, PPC_MIN_STKFRM
2956 * Save away FP, VMX and VSX registers.
2958 * N.B. r30 and r31 are volatile across this function,
2959 * thus it is not callable from C.
2966 #ifdef CONFIG_ALTIVEC
2968 oris r8,r8,MSR_VEC@h
2969 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2973 oris r8,r8,MSR_VSX@h
2974 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2977 addi r3,r3,VCPU_FPRS
2979 #ifdef CONFIG_ALTIVEC
2981 addi r3,r31,VCPU_VRS
2983 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2985 mfspr r6,SPRN_VRSAVE
2986 stw r6,VCPU_VRSAVE(r31)
2991 * Load up FP, VMX and VSX registers
2993 * N.B. r30 and r31 are volatile across this function,
2994 * thus it is not callable from C.
3001 #ifdef CONFIG_ALTIVEC
3003 oris r8,r8,MSR_VEC@h
3004 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3008 oris r8,r8,MSR_VSX@h
3009 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3012 addi r3,r4,VCPU_FPRS
3014 #ifdef CONFIG_ALTIVEC
3016 addi r3,r31,VCPU_VRS
3018 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3020 lwz r7,VCPU_VRSAVE(r31)
3021 mtspr SPRN_VRSAVE,r7
3026 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3028 * Save transactional state and TM-related registers.
3029 * Called with r9 pointing to the vcpu struct.
3030 * This can modify all checkpointed registers, but
3031 * restores r1, r2 and r9 (vcpu pointer) before exit.
3035 std r0, PPC_LR_STKOFF(r1)
3040 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3044 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3045 beq 1f /* TM not active in guest. */
3047 std r1, HSTATE_HOST_R1(r13)
3048 li r3, TM_CAUSE_KVM_RESCHED
3050 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3054 /* All GPRs are volatile at this point. */
3057 /* Temporarily store r13 and r9 so we have some regs to play with */
3060 std r9, PACATMSCRATCH(r13)
3061 ld r9, HSTATE_KVM_VCPU(r13)
3063 /* Get a few more GPRs free. */
3064 std r29, VCPU_GPRS_TM(29)(r9)
3065 std r30, VCPU_GPRS_TM(30)(r9)
3066 std r31, VCPU_GPRS_TM(31)(r9)
3068 /* Save away PPR and DSCR soon so don't run with user values. */
3071 mfspr r30, SPRN_DSCR
3072 ld r29, HSTATE_DSCR(r13)
3073 mtspr SPRN_DSCR, r29
3075 /* Save all but r9, r13 & r29-r31 */
3078 .if (reg != 9) && (reg != 13)
3079 std reg, VCPU_GPRS_TM(reg)(r9)
3083 /* ... now save r13 */
3085 std r4, VCPU_GPRS_TM(13)(r9)
3086 /* ... and save r9 */
3087 ld r4, PACATMSCRATCH(r13)
3088 std r4, VCPU_GPRS_TM(9)(r9)
3090 /* Reload stack pointer and TOC. */
3091 ld r1, HSTATE_HOST_R1(r13)
3094 /* Set MSR RI now we have r1 and r13 back. */
3098 /* Save away checkpinted SPRs. */
3099 std r31, VCPU_PPR_TM(r9)
3100 std r30, VCPU_DSCR_TM(r9)
3107 std r5, VCPU_LR_TM(r9)
3108 stw r6, VCPU_CR_TM(r9)
3109 std r7, VCPU_CTR_TM(r9)
3110 std r8, VCPU_AMR_TM(r9)
3111 std r10, VCPU_TAR_TM(r9)
3112 std r11, VCPU_XER_TM(r9)
3114 /* Restore r12 as trap number. */
3115 lwz r12, VCPU_TRAP(r9)
3118 addi r3, r9, VCPU_FPRS_TM
3120 addi r3, r9, VCPU_VRS_TM
3122 mfspr r6, SPRN_VRSAVE
3123 stw r6, VCPU_VRSAVE_TM(r9)
3126 * We need to save these SPRs after the treclaim so that the software
3127 * error code is recorded correctly in the TEXASR. Also the user may
3128 * change these outside of a transaction, so they must always be
3131 mfspr r5, SPRN_TFHAR
3132 mfspr r6, SPRN_TFIAR
3133 mfspr r7, SPRN_TEXASR
3134 std r5, VCPU_TFHAR(r9)
3135 std r6, VCPU_TFIAR(r9)
3136 std r7, VCPU_TEXASR(r9)
3138 ld r0, PPC_LR_STKOFF(r1)
3143 * Restore transactional state and TM-related registers.
3144 * Called with r4 pointing to the vcpu struct.
3145 * This potentially modifies all checkpointed registers.
3146 * It restores r1, r2, r4 from the PACA.
3150 std r0, PPC_LR_STKOFF(r1)
3152 /* Turn on TM/FP/VSX/VMX so we can restore them. */
3158 oris r5, r5, (MSR_VEC | MSR_VSX)@h
3162 * The user may change these outside of a transaction, so they must
3163 * always be context switched.
3165 ld r5, VCPU_TFHAR(r4)
3166 ld r6, VCPU_TFIAR(r4)
3167 ld r7, VCPU_TEXASR(r4)
3168 mtspr SPRN_TFHAR, r5
3169 mtspr SPRN_TFIAR, r6
3170 mtspr SPRN_TEXASR, r7
3173 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
3174 beqlr /* TM not active in guest */
3175 std r1, HSTATE_HOST_R1(r13)
3177 /* Make sure the failure summary is set, otherwise we'll program check
3178 * when we trechkpt. It's possible that this might have been not set
3179 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
3182 oris r7, r7, (TEXASR_FS)@h
3183 mtspr SPRN_TEXASR, r7
3186 * We need to load up the checkpointed state for the guest.
3187 * We need to do this early as it will blow away any GPRs, VSRs and
3192 addi r3, r31, VCPU_FPRS_TM
3194 addi r3, r31, VCPU_VRS_TM
3197 lwz r7, VCPU_VRSAVE_TM(r4)
3198 mtspr SPRN_VRSAVE, r7
3200 ld r5, VCPU_LR_TM(r4)
3201 lwz r6, VCPU_CR_TM(r4)
3202 ld r7, VCPU_CTR_TM(r4)
3203 ld r8, VCPU_AMR_TM(r4)
3204 ld r9, VCPU_TAR_TM(r4)
3205 ld r10, VCPU_XER_TM(r4)
3214 * Load up PPR and DSCR values but don't put them in the actual SPRs
3215 * till the last moment to avoid running with userspace PPR and DSCR for
3218 ld r29, VCPU_DSCR_TM(r4)
3219 ld r30, VCPU_PPR_TM(r4)
3221 std r2, PACATMSCRATCH(r13) /* Save TOC */
3223 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
3227 /* Load GPRs r0-r28 */
3230 ld reg, VCPU_GPRS_TM(reg)(r31)
3234 mtspr SPRN_DSCR, r29
3237 /* Load final GPRs */
3238 ld 29, VCPU_GPRS_TM(29)(r31)
3239 ld 30, VCPU_GPRS_TM(30)(r31)
3240 ld 31, VCPU_GPRS_TM(31)(r31)
3242 /* TM checkpointed state is now setup. All GPRs are now volatile. */
3245 /* Now let's get back the state we need. */
3248 ld r29, HSTATE_DSCR(r13)
3249 mtspr SPRN_DSCR, r29
3250 ld r4, HSTATE_KVM_VCPU(r13)
3251 ld r1, HSTATE_HOST_R1(r13)
3252 ld r2, PACATMSCRATCH(r13)
3254 /* Set the MSR RI since we have our registers back. */
3258 ld r0, PPC_LR_STKOFF(r1)
3264 * We come here if we get any exception or interrupt while we are
3265 * executing host real mode code while in guest MMU context.
3266 * r12 is (CR << 32) | vector
3267 * r13 points to our PACA
3268 * r12 is saved in HSTATE_SCRATCH0(r13)
3269 * ctr is saved in HSTATE_SCRATCH1(r13) if RELOCATABLE
3270 * r9 is saved in HSTATE_SCRATCH2(r13)
3271 * r13 is saved in HSPRG1
3272 * cfar is saved in HSTATE_CFAR(r13)
3273 * ppr is saved in HSTATE_PPR(r13)
3275 kvmppc_bad_host_intr:
3277 * Switch to the emergency stack, but start half-way down in
3278 * case we were already on it.
3282 ld r1, PACAEMERGSP(r13)
3283 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
3296 mfspr r3, SPRN_HSRR0
3297 mfspr r4, SPRN_HSRR1
3299 mfspr r6, SPRN_HDSISR
3301 1: mfspr r3, SPRN_SRR0
3304 mfspr r6, SPRN_DSISR
3309 ld r9, HSTATE_SCRATCH2(r13)
3310 ld r12, HSTATE_SCRATCH0(r13)
3315 ld r5, HSTATE_CFAR(r13)
3316 std r5, ORIG_GPR3(r1)
3318 #ifdef CONFIG_RELOCATABLE
3319 ld r4, HSTATE_SCRATCH1(r13)
3324 lbz r6, PACAIRQSOFTMASK(r13)
3330 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
3331 std r3, STACK_FRAME_OVERHEAD-16(r1)
3334 * On POWER9 do a minimal restore of the MMU and call C code,
3335 * which will print a message and panic.
3336 * XXX On POWER7 and POWER8, we just spin here since we don't
3337 * know what the other threads are doing (and we don't want to
3338 * coordinate with them) - but at least we now have register state
3339 * in memory that we might be able to look at from another CPU.
3343 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
3344 ld r9, HSTATE_KVM_VCPU(r13)
3345 ld r10, VCPU_KVM(r9)
3350 mtspr SPRN_CIABR, r0
3351 mtspr SPRN_DAWRX, r0
3353 /* Flush the ERAT on radix P9 DD1 guest exit */
3356 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
3358 BEGIN_MMU_FTR_SECTION
3360 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
3365 ld r8, PACA_SLBSHADOWPTR(r13)
3366 .rept SLB_NUM_BOLTED
3367 li r3, SLBSHADOW_SAVEAREA
3371 andis. r7, r5, SLB_ESID_V@h
3377 4: lwz r7, KVM_HOST_LPID(r10)
3380 ld r8, KVM_HOST_LPCR(r10)
3383 li r0, KVM_GUEST_MODE_NONE
3384 stb r0, HSTATE_IN_GUEST(r13)
3387 * Turn on the MMU and jump to C code
3391 addi r3, r3, 9f - 5b
3392 ld r4, PACAKMSR(r13)
3396 9: addi r3, r1, STACK_FRAME_OVERHEAD
3397 bl kvmppc_bad_interrupt
3401 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3402 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3403 * r11 has the guest MSR value (in/out)
3404 * r9 has a vcpu pointer (in)
3405 * r0 is used as a scratch register
3407 kvmppc_msr_interrupt:
3408 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3409 cmpwi r0, 2 /* Check if we are in transactional state.. */
3410 ld r11, VCPU_INTR_MSR(r9)
3412 /* ... if transactional, change to suspended */
3414 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3418 * This works around a hardware bug on POWER8E processors, where
3419 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3420 * performance monitor interrupt. Instead, when we need to have
3421 * an interrupt pending, we have to arrange for a counter to overflow.
3425 mtspr SPRN_MMCR2, r3
3426 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3427 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3428 mtspr SPRN_MMCR0, r3
3435 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3437 * Start timing an activity
3438 * r3 = pointer to time accumulation struct, r4 = vcpu
3441 ld r5, HSTATE_KVM_VCORE(r13)
3442 lbz r6, VCORE_IN_GUEST(r5)
3444 beq 5f /* if in guest, need to */
3445 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3448 std r3, VCPU_CUR_ACTIVITY(r4)
3449 std r5, VCPU_ACTIVITY_START(r4)
3453 * Accumulate time to one activity and start another.
3454 * r3 = pointer to new time accumulation struct, r4 = vcpu
3456 kvmhv_accumulate_time:
3457 ld r5, HSTATE_KVM_VCORE(r13)
3458 lbz r8, VCORE_IN_GUEST(r5)
3460 beq 4f /* if in guest, need to */
3461 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3462 4: ld r5, VCPU_CUR_ACTIVITY(r4)
3463 ld r6, VCPU_ACTIVITY_START(r4)
3464 std r3, VCPU_CUR_ACTIVITY(r4)
3467 std r7, VCPU_ACTIVITY_START(r4)
3471 ld r8, TAS_SEQCOUNT(r5)
3474 std r8, TAS_SEQCOUNT(r5)
3476 ld r7, TAS_TOTAL(r5)
3478 std r7, TAS_TOTAL(r5)
3484 3: std r3, TAS_MIN(r5)
3490 std r8, TAS_SEQCOUNT(r5)
projects / platform / kernel / linux-starfive.git / blob