1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
6 * Derived from book3s_rmhandlers.S and other files, which are:
8 * Copyright SUSE Linux Products GmbH 2009
10 * Authors: Alexander Graf <agraf@suse.de>
13 #include <asm/ppc_asm.h>
14 #include <asm/code-patching-asm.h>
15 #include <asm/kvm_asm.h>
19 #include <asm/ptrace.h>
20 #include <asm/hvcall.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/exception-64s.h>
23 #include <asm/kvm_book3s_asm.h>
24 #include <asm/book3s/64/mmu-hash.h>
25 #include <asm/export.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-compat.h>
30 #include <asm/feature-fixups.h>
31 #include <asm/cpuidle.h>
33 /* Values in HSTATE_NAPPING(r13) */
34 #define NAPPING_CEDE 1
35 #define NAPPING_NOVCPU 2
36 #define NAPPING_UNSPLIT 3
38 /* Stack frame offsets for kvmppc_hv_entry */
40 #define STACK_SLOT_TRAP (SFS-4)
41 #define STACK_SLOT_TID (SFS-16)
42 #define STACK_SLOT_PSSCR (SFS-24)
43 #define STACK_SLOT_PID (SFS-32)
44 #define STACK_SLOT_IAMR (SFS-40)
45 #define STACK_SLOT_CIABR (SFS-48)
46 #define STACK_SLOT_DAWR0 (SFS-56)
47 #define STACK_SLOT_DAWRX0 (SFS-64)
48 #define STACK_SLOT_HFSCR (SFS-72)
49 #define STACK_SLOT_AMR (SFS-80)
50 #define STACK_SLOT_UAMOR (SFS-88)
51 #define STACK_SLOT_FSCR (SFS-96)
54 * Call kvmppc_hv_entry in real mode.
55 * Must be called with interrupts hard-disabled.
59 * LR = return address to continue at after eventually re-enabling MMU
61 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
63 std r0, PPC_LR_STKOFF(r1)
66 std r10, HSTATE_HOST_MSR(r13)
67 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
72 mtmsrd r0,1 /* clear RI in MSR */
78 ld r4, HSTATE_KVM_VCPU(r13)
81 /* Back from guest - restore host state and return to caller */
84 /* Restore host DABR and DABRX */
85 ld r5,HSTATE_DABR(r13)
89 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
92 ld r3,PACA_SPRG_VDSO(r13)
93 mtspr SPRN_SPRG_VDSO_WRITE,r3
95 /* Reload the host's PMU registers */
96 bl kvmhv_load_host_pmu
99 * Reload DEC. HDEC interrupts were disabled when
100 * we reloaded the host's LPCR value.
102 ld r3, HSTATE_DECEXP(r13)
107 /* hwthread_req may have got set by cede or no vcpu, so clear it */
109 stb r0, HSTATE_HWTHREAD_REQ(r13)
112 * For external interrupts we need to call the Linux
113 * handler to process the interrupt. We do that by jumping
114 * to absolute address 0x500 for external interrupts.
115 * The [h]rfid at the end of the handler will return to
116 * the book3s_hv_interrupts.S code. For other interrupts
117 * we do the rfid to get back to the book3s_hv_interrupts.S
120 ld r8, 112+PPC_LR_STKOFF(r1)
122 ld r7, HSTATE_HOST_MSR(r13)
124 /* Return the trap number on this thread as the return value */
127 /* RFI into the highmem handler */
131 mtmsrd r6, 1 /* Clear RI in MSR */
136 kvmppc_primary_no_guest:
137 /* We handle this much like a ceded vcpu */
138 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
139 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
140 /* HDEC value came from DEC in the first place, it will fit */
144 * Make sure the primary has finished the MMU switch.
145 * We should never get here on a secondary thread, but
146 * check it for robustness' sake.
148 ld r5, HSTATE_KVM_VCORE(r13)
149 65: lbz r0, VCORE_IN_GUEST(r5)
156 /* set our bit in napping_threads */
157 ld r5, HSTATE_KVM_VCORE(r13)
158 lbz r7, HSTATE_PTID(r13)
161 addi r6, r5, VCORE_NAPPING_THREADS
166 /* order napping_threads update vs testing entry_exit_map */
169 lwz r7, VCORE_ENTRY_EXIT(r5)
171 bge kvm_novcpu_exit /* another thread already exiting */
172 li r3, NAPPING_NOVCPU
173 stb r3, HSTATE_NAPPING(r13)
175 li r3, 0 /* Don't wake on privileged (OS) doorbell */
180 * Entered from kvm_start_guest if kvm_hstate.napping is set
186 ld r1, HSTATE_HOST_R1(r13)
187 ld r5, HSTATE_KVM_VCORE(r13)
189 stb r0, HSTATE_NAPPING(r13)
191 /* check the wake reason */
192 bl kvmppc_check_wake_reason
195 * Restore volatile registers since we could have called
196 * a C routine in kvmppc_check_wake_reason.
199 ld r5, HSTATE_KVM_VCORE(r13)
201 /* see if any other thread is already exiting */
202 lwz r0, VCORE_ENTRY_EXIT(r5)
206 /* clear our bit in napping_threads */
207 lbz r7, HSTATE_PTID(r13)
210 addi r6, r5, VCORE_NAPPING_THREADS
216 /* See if the wake reason means we need to exit */
220 /* See if our timeslice has expired (HDEC is negative) */
223 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
227 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
228 ld r4, HSTATE_KVM_VCPU(r13)
230 beq kvmppc_primary_no_guest
232 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
233 addi r3, r4, VCPU_TB_RMENTRY
234 bl kvmhv_start_timing
239 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
240 ld r4, HSTATE_KVM_VCPU(r13)
243 addi r3, r4, VCPU_TB_RMEXIT
244 bl kvmhv_accumulate_time
247 stw r12, STACK_SLOT_TRAP(r1)
248 bl kvmhv_commence_exit
250 b kvmhv_switch_to_host
253 * We come in here when wakened from Linux offline idle code.
255 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
257 _GLOBAL(idle_kvm_start_guest)
260 std r5, 8(r1) // Save CR in caller's frame
261 std r0, 16(r1) // Save LR in caller's frame
262 // Create frame on emergency stack
263 ld r4, PACAEMERGSP(r13)
264 stdu r1, -SWITCH_FRAME_SIZE(r4)
265 // Switch to new frame on emergency stack
267 std r3, 32(r1) // Save SRR1 wakeup value
271 * Could avoid this and pass it through in r3. For now,
272 * code expects it to be in SRR1.
277 stb r0,PACA_FTRACE_ENABLED(r13)
279 li r0,KVM_HWTHREAD_IN_KVM
280 stb r0,HSTATE_HWTHREAD_STATE(r13)
282 /* kvm cede / napping does not come through here */
283 lbz r0,HSTATE_NAPPING(r13)
290 stb r0, HSTATE_NAPPING(r13)
295 * We weren't napping due to cede, so this must be a secondary
296 * thread being woken up to run a guest, or being woken up due
297 * to a stray IPI. (Or due to some machine check or hypervisor
298 * maintenance interrupt while the core is in KVM.)
301 /* Check the wake reason in SRR1 to see why we got here */
302 bl kvmppc_check_wake_reason
304 * kvmppc_check_wake_reason could invoke a C routine, but we
305 * have no volatile registers to restore when we return.
311 /* get vcore pointer, NULL if we have nothing to run */
312 ld r5,HSTATE_KVM_VCORE(r13)
314 /* if we have no vcore to run, go back to sleep */
317 kvm_secondary_got_guest:
319 // About to go to guest, clear saved SRR1
323 /* Set HSTATE_DSCR(r13) to something sensible */
324 ld r6, PACA_DSCR_DEFAULT(r13)
325 std r6, HSTATE_DSCR(r13)
327 /* On thread 0 of a subcore, set HDEC to max */
328 lbz r4, HSTATE_PTID(r13)
331 lis r6,0x7fff /* MAX_INT@h */
333 /* and set per-LPAR registers, if doing dynamic micro-threading */
334 ld r6, HSTATE_SPLIT_MODE(r13)
337 ld r0, KVM_SPLIT_RPR(r6)
339 ld r0, KVM_SPLIT_PMMAR(r6)
341 ld r0, KVM_SPLIT_LDBAR(r6)
345 /* Order load of vcpu after load of vcore */
347 ld r4, HSTATE_KVM_VCPU(r13)
350 /* Back from the guest, go back to nap */
351 /* Clear our vcpu and vcore pointers so we don't come back in early */
353 std r0, HSTATE_KVM_VCPU(r13)
355 * Once we clear HSTATE_KVM_VCORE(r13), the code in
356 * kvmppc_run_core() is going to assume that all our vcpu
357 * state is visible in memory. This lwsync makes sure
361 std r0, HSTATE_KVM_VCORE(r13)
364 * All secondaries exiting guest will fall through this path.
365 * Before proceeding, just check for HMI interrupt and
366 * invoke opal hmi handler. By now we are sure that the
367 * primary thread on this core/subcore has already made partition
368 * switch/TB resync and we are good to call opal hmi handler.
370 cmpwi r12, BOOK3S_INTERRUPT_HMI
373 li r3,0 /* NULL argument */
374 bl hmi_exception_realmode
376 * At this point we have finished executing in the guest.
377 * We need to wait for hwthread_req to become zero, since
378 * we may not turn on the MMU while hwthread_req is non-zero.
379 * While waiting we also need to check if we get given a vcpu to run.
382 lbz r3, HSTATE_HWTHREAD_REQ(r13)
386 li r0, KVM_HWTHREAD_IN_KERNEL
387 stb r0, HSTATE_HWTHREAD_STATE(r13)
388 /* need to recheck hwthread_req after a barrier, to avoid race */
390 lbz r3, HSTATE_HWTHREAD_REQ(r13)
395 * Jump to idle_return_gpr_loss, which returns to the
396 * idle_kvm_start_guest caller.
400 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
402 // Return SRR1 wakeup value, or 0 if we went into the guest
405 ld r1, 0(r1) // Switch back to caller stack
406 ld r0, 16(r1) // Reload LR
407 ld r5, 8(r1) // Reload CR
414 ld r5, HSTATE_KVM_VCORE(r13)
417 ld r3, HSTATE_SPLIT_MODE(r13)
420 lbz r0, KVM_SPLIT_DO_NAP(r3)
426 b kvm_secondary_got_guest
428 54: li r0, KVM_HWTHREAD_IN_KVM
429 stb r0, HSTATE_HWTHREAD_STATE(r13)
433 * Here the primary thread is trying to return the core to
434 * whole-core mode, so we need to nap.
438 * When secondaries are napping in kvm_unsplit_nap() with
439 * hwthread_req = 1, HMI goes ignored even though subcores are
440 * already exited the guest. Hence HMI keeps waking up secondaries
441 * from nap in a loop and secondaries always go back to nap since
442 * no vcore is assigned to them. This makes impossible for primary
443 * thread to get hold of secondary threads resulting into a soft
444 * lockup in KVM path.
446 * Let us check if HMI is pending and handle it before we go to nap.
448 cmpwi r12, BOOK3S_INTERRUPT_HMI
450 li r3, 0 /* NULL argument */
451 bl hmi_exception_realmode
454 * Ensure that secondary doesn't nap when it has
455 * its vcore pointer set.
457 sync /* matches smp_mb() before setting split_info.do_nap */
458 ld r0, HSTATE_KVM_VCORE(r13)
461 /* clear any pending message */
463 lis r6, (PPC_DBELL_SERVER << (63-36))@h
465 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
466 /* Set kvm_split_mode.napped[tid] = 1 */
467 ld r3, HSTATE_SPLIT_MODE(r13)
469 lhz r4, PACAPACAINDEX(r13)
470 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
471 addi r4, r4, KVM_SPLIT_NAPPED
473 /* Check the do_nap flag again after setting napped[] */
475 lbz r0, KVM_SPLIT_DO_NAP(r3)
478 li r3, NAPPING_UNSPLIT
479 stb r3, HSTATE_NAPPING(r13)
480 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
482 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
489 /******************************************************************************
493 *****************************************************************************/
495 .global kvmppc_hv_entry
500 * R4 = vcpu pointer (or NULL)
505 * all other volatile GPRS = free
506 * Does not preserve non-volatile GPRs or CR fields
509 std r0, PPC_LR_STKOFF(r1)
512 /* Save R1 in the PACA */
513 std r1, HSTATE_HOST_R1(r13)
515 li r6, KVM_GUEST_MODE_HOST_HV
516 stb r6, HSTATE_IN_GUEST(r13)
518 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
519 /* Store initial timestamp */
522 addi r3, r4, VCPU_TB_RMENTRY
523 bl kvmhv_start_timing
527 ld r5, HSTATE_KVM_VCORE(r13)
528 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
531 * POWER7/POWER8 host -> guest partition switch code.
532 * We don't have to lock against concurrent tlbies,
533 * but we do have to coordinate across hardware threads.
535 /* Set bit in entry map iff exit map is zero. */
537 lbz r6, HSTATE_PTID(r13)
539 addi r8, r5, VCORE_ENTRY_EXIT
541 cmpwi r3, 0x100 /* any threads starting to exit? */
542 bge secondary_too_late /* if so we're too late to the party */
547 /* Primary thread switches to guest partition. */
553 li r0,LPID_RSVD /* switch to reserved LPID */
556 mtspr SPRN_SDR1,r6 /* switch to partition page table */
560 /* See if we need to flush the TLB. */
561 mr r3, r9 /* kvm pointer */
562 lhz r4, PACAPACAINDEX(r13) /* physical cpu number */
563 li r5, 0 /* nested vcpu pointer */
564 bl kvmppc_check_need_tlb_flush
566 ld r5, HSTATE_KVM_VCORE(r13)
568 /* Add timebase offset onto timebase */
569 22: ld r8,VCORE_TB_OFFSET(r5)
572 std r8, VCORE_TB_OFFSET_APPL(r5)
573 mftb r6 /* current host timebase */
575 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
576 mftb r7 /* check if lower 24 bits overflowed */
581 addis r8,r8,0x100 /* if so, increment upper 40 bits */
584 /* Load guest PCR value to select appropriate compat mode */
585 37: ld r7, VCORE_PCR(r5)
586 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
594 /* DPDES and VTB are shared between threads */
595 ld r8, VCORE_DPDES(r5)
599 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
601 /* Mark the subcore state as inside guest */
602 bl kvmppc_subcore_enter_guest
604 ld r5, HSTATE_KVM_VCORE(r13)
605 ld r4, HSTATE_KVM_VCPU(r13)
607 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
609 /* Do we have a guest vcpu to run? */
611 beq kvmppc_primary_no_guest
613 /* Increment yield count if they have a VPA */
617 li r6, LPPACA_YIELDCOUNT
622 stb r6, VCPU_VPA_DIRTY(r4)
625 /* Save purr/spurr */
628 std r5,HSTATE_PURR(r13)
629 std r6,HSTATE_SPURR(r13)
635 /* Save host values of some registers */
639 mfspr r7, SPRN_DAWRX0
641 std r5, STACK_SLOT_CIABR(r1)
642 std r6, STACK_SLOT_DAWR0(r1)
643 std r7, STACK_SLOT_DAWRX0(r1)
644 std r8, STACK_SLOT_IAMR(r1)
646 std r5, STACK_SLOT_FSCR(r1)
647 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
650 std r5, STACK_SLOT_AMR(r1)
652 std r6, STACK_SLOT_UAMOR(r1)
655 /* Set partition DABR */
656 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
657 lwz r5,VCPU_DABRX(r4)
662 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
664 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
667 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
669 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
673 li r5, 0 /* don't preserve non-vol regs */
674 bl kvmppc_restore_tm_hv
676 ld r4, HSTATE_KVM_VCPU(r13)
680 /* Load guest PMU registers; r4 = vcpu pointer here */
682 bl kvmhv_load_guest_pmu
684 /* Load up FP, VMX and VSX registers */
685 ld r4, HSTATE_KVM_VCPU(r13)
688 ld r14, VCPU_GPR(R14)(r4)
689 ld r15, VCPU_GPR(R15)(r4)
690 ld r16, VCPU_GPR(R16)(r4)
691 ld r17, VCPU_GPR(R17)(r4)
692 ld r18, VCPU_GPR(R18)(r4)
693 ld r19, VCPU_GPR(R19)(r4)
694 ld r20, VCPU_GPR(R20)(r4)
695 ld r21, VCPU_GPR(R21)(r4)
696 ld r22, VCPU_GPR(R22)(r4)
697 ld r23, VCPU_GPR(R23)(r4)
698 ld r24, VCPU_GPR(R24)(r4)
699 ld r25, VCPU_GPR(R25)(r4)
700 ld r26, VCPU_GPR(R26)(r4)
701 ld r27, VCPU_GPR(R27)(r4)
702 ld r28, VCPU_GPR(R28)(r4)
703 ld r29, VCPU_GPR(R29)(r4)
704 ld r30, VCPU_GPR(R30)(r4)
705 ld r31, VCPU_GPR(R31)(r4)
707 /* Switch DSCR to guest value */
712 /* Skip next section on POWER7 */
714 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
715 /* Load up POWER8-specific registers */
717 lwz r6, VCPU_PSPB(r4)
723 * Handle broken DAWR case by not writing it. This means we
724 * can still store the DAWR register for migration.
726 LOAD_REG_ADDR(r5, dawr_force_enable)
730 ld r5, VCPU_DAWR0(r4)
731 ld r6, VCPU_DAWRX0(r4)
733 mtspr SPRN_DAWRX0, r6
735 ld r7, VCPU_CIABR(r4)
740 ld r8, VCPU_EBBHR(r4)
743 ld r5, VCPU_EBBRR(r4)
744 ld r6, VCPU_BESCR(r4)
745 lwz r7, VCPU_GUEST_PID(r4)
751 /* POWER8-only registers */
752 ld r5, VCPU_TCSCR(r4)
754 ld r7, VCPU_CSIGR(r4)
763 ld r5, VCPU_SPRG0(r4)
764 ld r6, VCPU_SPRG1(r4)
765 ld r7, VCPU_SPRG2(r4)
766 ld r8, VCPU_SPRG3(r4)
772 /* Load up DAR and DSISR */
774 lwz r6, VCPU_DSISR(r4)
778 /* Restore AMR and UAMOR, set AMOR to all 1s */
786 /* Restore state of CTRL run bit; assume 1 on entry */
794 /* Secondary threads wait for primary to have done partition switch */
795 ld r5, HSTATE_KVM_VCORE(r13)
796 lbz r6, HSTATE_PTID(r13)
799 lbz r0, VCORE_IN_GUEST(r5)
803 20: lwz r3, VCORE_ENTRY_EXIT(r5)
806 lbz r0, VCORE_IN_GUEST(r5)
817 * Set the decrementer to the guest decrementer.
819 ld r8,VCPU_DEC_EXPIRES(r4)
820 /* r8 is a host timebase value here, convert to guest TB */
821 ld r5,HSTATE_KVM_VCORE(r13)
822 ld r6,VCORE_TB_OFFSET_APPL(r5)
828 /* Check if HDEC expires soon */
831 cmpdi r3, 512 /* 1 microsecond */
834 /* Clear out and reload the SLB */
840 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
841 lwz r5,VCPU_SLB_MAX(r4)
846 1: ld r8,VCPU_SLB_E(r6)
849 addi r6,r6,VCPU_SLB_SIZE
853 deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
854 /* Check if we can deliver an external or decrementer interrupt now */
855 ld r0, VCPU_PENDING_EXC(r4)
859 bl kvmppc_guest_entry_inject_int
860 ld r4, HSTATE_KVM_VCPU(r13)
869 /* r11 = vcpu->arch.msr & ~MSR_HV */
870 rldicl r11, r11, 63 - MSR_HV_LG, 1
871 rotldi r11, r11, 1 + MSR_HV_LG
882 * R10: value for HSRR0
883 * R11: value for HSRR1
888 stb r0,VCPU_CEDED(r4) /* cancel cede */
892 /* Activate guest mode, so faults get handled by KVM */
893 li r9, KVM_GUEST_MODE_GUEST_HV
894 stb r9, HSTATE_IN_GUEST(r13)
896 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
897 /* Accumulate timing */
898 addi r3, r4, VCPU_TB_GUEST
899 bl kvmhv_accumulate_time
907 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
910 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
915 ld r1, VCPU_GPR(R1)(r4)
916 ld r5, VCPU_GPR(R5)(r4)
917 ld r8, VCPU_GPR(R8)(r4)
918 ld r9, VCPU_GPR(R9)(r4)
919 ld r10, VCPU_GPR(R10)(r4)
920 ld r11, VCPU_GPR(R11)(r4)
921 ld r12, VCPU_GPR(R12)(r4)
922 ld r13, VCPU_GPR(R13)(r4)
926 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
928 ld r6, VCPU_GPR(R6)(r4)
929 ld r7, VCPU_GPR(R7)(r4)
934 ld r0, VCPU_GPR(R0)(r4)
935 ld r2, VCPU_GPR(R2)(r4)
936 ld r3, VCPU_GPR(R3)(r4)
937 ld r4, VCPU_GPR(R4)(r4)
943 stw r12, STACK_SLOT_TRAP(r1)
946 stw r12, VCPU_TRAP(r4)
947 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
948 addi r3, r4, VCPU_TB_RMEXIT
949 bl kvmhv_accumulate_time
951 11: b kvmhv_switch_to_host
958 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
959 12: stw r12, VCPU_TRAP(r4)
961 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
962 addi r3, r4, VCPU_TB_RMEXIT
963 bl kvmhv_accumulate_time
967 /******************************************************************************
971 *****************************************************************************/
974 * We come here from the first-level interrupt handlers.
976 .globl kvmppc_interrupt_hv
980 * R9 = HSTATE_IN_GUEST
981 * R12 = (guest CR << 32) | interrupt vector
983 * guest R12 saved in shadow VCPU SCRATCH0
984 * guest R13 saved in SPRN_SCRATCH0
985 * guest R9 saved in HSTATE_SCRATCH2
987 /* We're now back in the host but in guest MMU context */
988 cmpwi r9,KVM_GUEST_MODE_HOST_HV
989 beq kvmppc_bad_host_intr
990 li r9, KVM_GUEST_MODE_HOST_HV
991 stb r9, HSTATE_IN_GUEST(r13)
993 ld r9, HSTATE_KVM_VCPU(r13)
997 std r0, VCPU_GPR(R0)(r9)
998 std r1, VCPU_GPR(R1)(r9)
999 std r2, VCPU_GPR(R2)(r9)
1000 std r3, VCPU_GPR(R3)(r9)
1001 std r4, VCPU_GPR(R4)(r9)
1002 std r5, VCPU_GPR(R5)(r9)
1003 std r6, VCPU_GPR(R6)(r9)
1004 std r7, VCPU_GPR(R7)(r9)
1005 std r8, VCPU_GPR(R8)(r9)
1006 ld r0, HSTATE_SCRATCH2(r13)
1007 std r0, VCPU_GPR(R9)(r9)
1008 std r10, VCPU_GPR(R10)(r9)
1009 std r11, VCPU_GPR(R11)(r9)
1010 ld r3, HSTATE_SCRATCH0(r13)
1011 std r3, VCPU_GPR(R12)(r9)
1012 /* CR is in the high half of r12 */
1016 ld r3, HSTATE_CFAR(r13)
1017 std r3, VCPU_CFAR(r9)
1018 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1020 ld r4, HSTATE_PPR(r13)
1021 std r4, VCPU_PPR(r9)
1022 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1024 /* Restore R1/R2 so we can handle faults */
1025 ld r1, HSTATE_HOST_R1(r13)
1028 mfspr r10, SPRN_SRR0
1029 mfspr r11, SPRN_SRR1
1030 std r10, VCPU_SRR0(r9)
1031 std r11, VCPU_SRR1(r9)
1032 /* trap is in the low half of r12, clear CR from the high half */
1034 andi. r0, r12, 2 /* need to read HSRR0/1? */
1036 mfspr r10, SPRN_HSRR0
1037 mfspr r11, SPRN_HSRR1
1039 1: std r10, VCPU_PC(r9)
1040 std r11, VCPU_MSR(r9)
1044 std r3, VCPU_GPR(R13)(r9)
1047 stw r12,VCPU_TRAP(r9)
1050 * Now that we have saved away SRR0/1 and HSRR0/1,
1051 * interrupts are recoverable in principle, so set MSR_RI.
1052 * This becomes important for relocation-on interrupts from
1053 * the guest, which we can get in radix mode on POWER9.
1058 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1059 addi r3, r9, VCPU_TB_RMINTR
1061 bl kvmhv_accumulate_time
1062 ld r5, VCPU_GPR(R5)(r9)
1063 ld r6, VCPU_GPR(R6)(r9)
1064 ld r7, VCPU_GPR(R7)(r9)
1065 ld r8, VCPU_GPR(R8)(r9)
1068 /* Save HEIR (HV emulation assist reg) in emul_inst
1069 if this is an HEI (HV emulation interrupt, e40) */
1070 li r3,KVM_INST_FETCH_FAILED
1071 stw r3,VCPU_LAST_INST(r9)
1072 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1075 11: stw r3,VCPU_HEIR(r9)
1077 /* these are volatile across C function calls */
1080 std r3, VCPU_CTR(r9)
1081 std r4, VCPU_XER(r9)
1083 /* Save more register state */
1086 std r3, VCPU_DAR(r9)
1087 stw r4, VCPU_DSISR(r9)
1089 /* If this is a page table miss then see if it's theirs or ours */
1090 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1092 std r3, VCPU_FAULT_DAR(r9)
1093 stw r4, VCPU_FAULT_DSISR(r9)
1094 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1097 /* See if this is a leftover HDEC interrupt */
1098 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1104 bge fast_guest_return
1106 /* See if this is an hcall we can handle in real mode */
1107 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1108 beq hcall_try_real_mode
1110 /* Hypervisor doorbell - exit only if host IPI flag set */
1111 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1113 lbz r0, HSTATE_HOST_IPI(r13)
1115 beq maybe_reenter_guest
1118 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1119 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1121 mfspr r3, SPRN_HFSCR
1122 std r3, VCPU_HFSCR(r9)
1125 /* External interrupt ? */
1126 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1127 beq kvmppc_guest_external
1128 /* See if it is a machine check */
1129 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1130 beq machine_check_realmode
1131 /* Or a hypervisor maintenance interrupt */
1132 cmpwi r12, BOOK3S_INTERRUPT_HMI
1135 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1137 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1138 addi r3, r9, VCPU_TB_RMEXIT
1140 bl kvmhv_accumulate_time
1144 * Possibly flush the link stack here, before we do a blr in
1145 * kvmhv_switch_to_host.
1148 patch_site 1b patch__call_kvm_flush_link_stack
1150 /* For hash guest, read the guest SLB and save it away */
1152 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1157 andis. r0,r8,SLB_ESID_V@h
1159 add r8,r8,r6 /* put index in */
1161 std r8,VCPU_SLB_E(r7)
1162 std r3,VCPU_SLB_V(r7)
1163 addi r7,r7,VCPU_SLB_SIZE
1167 /* Finally clear out the SLB */
1172 stw r5,VCPU_SLB_MAX(r9)
1174 /* load host SLB entries */
1175 ld r8,PACA_SLBSHADOWPTR(r13)
1177 .rept SLB_NUM_BOLTED
1178 li r3, SLBSHADOW_SAVEAREA
1182 andis. r7,r5,SLB_ESID_V@h
1189 stw r12, STACK_SLOT_TRAP(r1)
1192 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1193 ld r3, HSTATE_KVM_VCORE(r13)
1198 /* r5 is a guest timebase value here, convert to host TB */
1199 ld r4,VCORE_TB_OFFSET_APPL(r3)
1201 std r5,VCPU_DEC_EXPIRES(r9)
1203 /* Increment exit count, poke other threads to exit */
1205 bl kvmhv_commence_exit
1207 ld r9, HSTATE_KVM_VCPU(r13)
1209 /* Stop others sending VCPU interrupts to this physical CPU */
1211 stw r0, VCPU_CPU(r9)
1212 stw r0, VCPU_THREAD_CPU(r9)
1214 /* Save guest CTRL register, set runlatch to 1 */
1216 stw r6,VCPU_CTRL(r9)
1223 * Save the guest PURR/SPURR
1228 ld r8,VCPU_SPURR(r9)
1229 std r5,VCPU_PURR(r9)
1230 std r6,VCPU_SPURR(r9)
1235 * Restore host PURR/SPURR and add guest times
1236 * so that the time in the guest gets accounted.
1238 ld r3,HSTATE_PURR(r13)
1239 ld r4,HSTATE_SPURR(r13)
1247 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1248 /* Save POWER8-specific registers */
1252 std r5, VCPU_IAMR(r9)
1253 stw r6, VCPU_PSPB(r9)
1254 std r7, VCPU_FSCR(r9)
1258 std r7, VCPU_TAR(r9)
1259 mfspr r8, SPRN_EBBHR
1260 std r8, VCPU_EBBHR(r9)
1261 mfspr r5, SPRN_EBBRR
1262 mfspr r6, SPRN_BESCR
1265 std r5, VCPU_EBBRR(r9)
1266 std r6, VCPU_BESCR(r9)
1267 stw r7, VCPU_GUEST_PID(r9)
1268 std r8, VCPU_WORT(r9)
1269 mfspr r5, SPRN_TCSCR
1271 mfspr r7, SPRN_CSIGR
1273 std r5, VCPU_TCSCR(r9)
1274 std r6, VCPU_ACOP(r9)
1275 std r7, VCPU_CSIGR(r9)
1276 std r8, VCPU_TACR(r9)
1278 ld r5, STACK_SLOT_FSCR(r1)
1280 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1282 * Restore various registers to 0, where non-zero values
1283 * set by the guest could disrupt the host.
1288 mtspr SPRN_TCSCR, r0
1289 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1292 mtspr SPRN_MMCRS, r0
1294 /* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
1295 ld r8, STACK_SLOT_IAMR(r1)
1298 8: /* Power7 jumps back in here */
1302 std r6,VCPU_UAMOR(r9)
1303 ld r5,STACK_SLOT_AMR(r1)
1304 ld r6,STACK_SLOT_UAMOR(r1)
1306 mtspr SPRN_UAMOR, r6
1308 /* Switch DSCR back to host value */
1310 ld r7, HSTATE_DSCR(r13)
1311 std r8, VCPU_DSCR(r9)
1314 /* Save non-volatile GPRs */
1315 std r14, VCPU_GPR(R14)(r9)
1316 std r15, VCPU_GPR(R15)(r9)
1317 std r16, VCPU_GPR(R16)(r9)
1318 std r17, VCPU_GPR(R17)(r9)
1319 std r18, VCPU_GPR(R18)(r9)
1320 std r19, VCPU_GPR(R19)(r9)
1321 std r20, VCPU_GPR(R20)(r9)
1322 std r21, VCPU_GPR(R21)(r9)
1323 std r22, VCPU_GPR(R22)(r9)
1324 std r23, VCPU_GPR(R23)(r9)
1325 std r24, VCPU_GPR(R24)(r9)
1326 std r25, VCPU_GPR(R25)(r9)
1327 std r26, VCPU_GPR(R26)(r9)
1328 std r27, VCPU_GPR(R27)(r9)
1329 std r28, VCPU_GPR(R28)(r9)
1330 std r29, VCPU_GPR(R29)(r9)
1331 std r30, VCPU_GPR(R30)(r9)
1332 std r31, VCPU_GPR(R31)(r9)
1335 mfspr r3, SPRN_SPRG0
1336 mfspr r4, SPRN_SPRG1
1337 mfspr r5, SPRN_SPRG2
1338 mfspr r6, SPRN_SPRG3
1339 std r3, VCPU_SPRG0(r9)
1340 std r4, VCPU_SPRG1(r9)
1341 std r5, VCPU_SPRG2(r9)
1342 std r6, VCPU_SPRG3(r9)
1348 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1351 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1353 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
1357 li r5, 0 /* don't preserve non-vol regs */
1358 bl kvmppc_save_tm_hv
1360 ld r9, HSTATE_KVM_VCPU(r13)
1364 /* Increment yield count if they have a VPA */
1365 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1368 li r4, LPPACA_YIELDCOUNT
1373 stb r3, VCPU_VPA_DIRTY(r9)
1375 /* Save PMU registers if requested */
1376 /* r8 and cr0.eq are live here */
1379 beq 21f /* if no VPA, save PMU stuff anyway */
1380 lbz r4, LPPACA_PMCINUSE(r8)
1381 21: bl kvmhv_save_guest_pmu
1382 ld r9, HSTATE_KVM_VCPU(r13)
1384 /* Restore host values of some registers */
1386 ld r5, STACK_SLOT_CIABR(r1)
1387 ld r6, STACK_SLOT_DAWR0(r1)
1388 ld r7, STACK_SLOT_DAWRX0(r1)
1389 mtspr SPRN_CIABR, r5
1391 * If the DAWR doesn't work, it's ok to write these here as
1392 * this value should always be zero
1394 mtspr SPRN_DAWR0, r6
1395 mtspr SPRN_DAWRX0, r7
1396 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1399 * POWER7/POWER8 guest -> host partition switch code.
1400 * We don't have to lock against tlbies but we do
1401 * have to coordinate the hardware threads.
1402 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1404 kvmhv_switch_to_host:
1405 /* Secondary threads wait for primary to do partition switch */
1406 ld r5,HSTATE_KVM_VCORE(r13)
1407 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1408 lbz r3,HSTATE_PTID(r13)
1412 13: lbz r3,VCORE_IN_GUEST(r5)
1418 /* Primary thread waits for all the secondaries to exit guest */
1419 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1420 rlwinm r0,r3,32-8,0xff
1426 /* Did we actually switch to the guest at all? */
1427 lbz r6, VCORE_IN_GUEST(r5)
1431 /* Primary thread switches back to host partition */
1432 lwz r7,KVM_HOST_LPID(r4)
1433 ld r6,KVM_HOST_SDR1(r4)
1434 li r8,LPID_RSVD /* switch to reserved LPID */
1437 mtspr SPRN_SDR1,r6 /* switch to host page table */
1442 /* DPDES and VTB are shared between threads */
1443 mfspr r7, SPRN_DPDES
1445 std r7, VCORE_DPDES(r5)
1446 std r8, VCORE_VTB(r5)
1447 /* clear DPDES so we don't get guest doorbells in the host */
1449 mtspr SPRN_DPDES, r8
1450 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1452 /* Subtract timebase offset from timebase */
1453 ld r8, VCORE_TB_OFFSET_APPL(r5)
1457 std r0, VCORE_TB_OFFSET_APPL(r5)
1458 mftb r6 /* current guest timebase */
1460 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1461 mftb r7 /* check if lower 24 bits overflowed */
1466 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1471 * If this is an HMI, we called kvmppc_realmode_hmi_handler
1472 * above, which may or may not have already called
1473 * kvmppc_subcore_exit_guest. Fortunately, all that
1474 * kvmppc_subcore_exit_guest does is clear a flag, so calling
1475 * it again here is benign even if kvmppc_realmode_hmi_handler
1476 * has already called it.
1478 bl kvmppc_subcore_exit_guest
1480 30: ld r5,HSTATE_KVM_VCORE(r13)
1481 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1484 ld r0, VCORE_PCR(r5)
1485 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
1490 /* Signal secondary CPUs to continue */
1492 stb r0,VCORE_IN_GUEST(r5)
1493 19: lis r8,0x7fff /* MAX_INT@h */
1496 16: ld r8,KVM_HOST_LPCR(r4)
1500 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1501 /* Finish timing, if we have a vcpu */
1502 ld r4, HSTATE_KVM_VCPU(r13)
1506 bl kvmhv_accumulate_time
1509 /* Unset guest mode */
1510 li r0, KVM_GUEST_MODE_NONE
1511 stb r0, HSTATE_IN_GUEST(r13)
1513 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1514 ld r0, SFS+PPC_LR_STKOFF(r1)
1520 .global kvm_flush_link_stack
1521 kvm_flush_link_stack:
1522 /* Save LR into r0 */
1525 /* Flush the link stack. On Power8 it's up to 32 entries in size. */
1530 /* And on Power9 it's up to 64. */
1535 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1541 kvmppc_guest_external:
1542 /* External interrupt, first check for host_ipi. If this is
1543 * set, we know the host wants us out so let's do it now
1548 * Restore the active volatile registers after returning from
1551 ld r9, HSTATE_KVM_VCPU(r13)
1552 li r12, BOOK3S_INTERRUPT_EXTERNAL
1555 * kvmppc_read_intr return codes:
1557 * Exit to host (r3 > 0)
1558 * 1 An interrupt is pending that needs to be handled by the host
1559 * Exit guest and return to host by branching to guest_exit_cont
1561 * 2 Passthrough that needs completion in the host
1562 * Exit guest and return to host by branching to guest_exit_cont
1563 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1564 * to indicate to the host to complete handling the interrupt
1566 * Before returning to guest, we check if any CPU is heading out
1567 * to the host and if so, we head out also. If no CPUs are heading
1568 * check return values <= 0.
1570 * Return to guest (r3 <= 0)
1571 * 0 No external interrupt is pending
1572 * -1 A guest wakeup IPI (which has now been cleared)
1573 * In either case, we return to guest to deliver any pending
1576 * -2 A PCI passthrough external interrupt was handled
1577 * (interrupt was delivered directly to guest)
1578 * Return to guest to deliver any pending guest interrupts.
1584 /* Return code = 2 */
1585 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1586 stw r12, VCPU_TRAP(r9)
1589 1: /* Return code <= 1 */
1593 /* Return code <= 0 */
1594 maybe_reenter_guest:
1595 ld r5, HSTATE_KVM_VCORE(r13)
1596 lwz r0, VCORE_ENTRY_EXIT(r5)
1599 blt deliver_guest_interrupt
1603 * Check whether an HDSI is an HPTE not found fault or something else.
1604 * If it is an HPTE not found fault that is due to the guest accessing
1605 * a page that they have mapped but which we have paged out, then
1606 * we continue on with the guest exit path. In all other cases,
1607 * reflect the HDSI to the guest as a DSI.
1611 mfspr r6, SPRN_HDSISR
1612 /* HPTE not found fault or protection fault? */
1613 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1614 beq 1f /* if not, send it to the guest */
1615 andi. r0, r11, MSR_DR /* data relocation enabled? */
1618 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1619 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1620 bne 7f /* if no SLB entry found */
1621 4: std r4, VCPU_FAULT_DAR(r9)
1622 stw r6, VCPU_FAULT_DSISR(r9)
1624 /* Search the hash table. */
1625 mr r3, r9 /* vcpu pointer */
1626 li r7, 1 /* data fault */
1627 bl kvmppc_hpte_hv_fault
1628 ld r9, HSTATE_KVM_VCPU(r13)
1630 ld r11, VCPU_MSR(r9)
1631 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1632 cmpdi r3, 0 /* retry the instruction */
1634 cmpdi r3, -1 /* handle in kernel mode */
1636 cmpdi r3, -2 /* MMIO emulation; need instr word */
1639 /* Synthesize a DSI (or DSegI) for the guest */
1640 ld r4, VCPU_FAULT_DAR(r9)
1642 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1643 mtspr SPRN_DSISR, r6
1644 7: mtspr SPRN_DAR, r4
1645 mtspr SPRN_SRR0, r10
1646 mtspr SPRN_SRR1, r11
1648 bl kvmppc_msr_interrupt
1649 fast_interrupt_c_return:
1650 6: ld r7, VCPU_CTR(r9)
1657 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1658 ld r5, KVM_VRMA_SLB_V(r5)
1661 /* If this is for emulated MMIO, load the instruction word */
1662 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1664 /* Set guest mode to 'jump over instruction' so if lwz faults
1665 * we'll just continue at the next IP. */
1666 li r0, KVM_GUEST_MODE_SKIP
1667 stb r0, HSTATE_IN_GUEST(r13)
1669 /* Do the access with MSR:DR enabled */
1671 ori r4, r3, MSR_DR /* Enable paging for data */
1676 /* Store the result */
1677 stw r8, VCPU_LAST_INST(r9)
1679 /* Unset guest mode. */
1680 li r0, KVM_GUEST_MODE_HOST_HV
1681 stb r0, HSTATE_IN_GUEST(r13)
1685 * Similarly for an HISI, reflect it to the guest as an ISI unless
1686 * it is an HPTE not found fault for a page that we have paged out.
1689 andis. r0, r11, SRR1_ISI_NOPT@h
1691 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1694 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1695 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1696 bne 7f /* if no SLB entry found */
1698 /* Search the hash table. */
1699 mr r3, r9 /* vcpu pointer */
1702 li r7, 0 /* instruction fault */
1703 bl kvmppc_hpte_hv_fault
1704 ld r9, HSTATE_KVM_VCPU(r13)
1706 ld r11, VCPU_MSR(r9)
1707 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1708 cmpdi r3, 0 /* retry the instruction */
1709 beq fast_interrupt_c_return
1710 cmpdi r3, -1 /* handle in kernel mode */
1713 /* Synthesize an ISI (or ISegI) for the guest */
1715 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
1716 7: mtspr SPRN_SRR0, r10
1717 mtspr SPRN_SRR1, r11
1719 bl kvmppc_msr_interrupt
1720 b fast_interrupt_c_return
1722 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1723 ld r5, KVM_VRMA_SLB_V(r6)
1727 * Try to handle an hcall in real mode.
1728 * Returns to the guest if we handle it, or continues on up to
1729 * the kernel if we can't (i.e. if we don't have a handler for
1730 * it, or if the handler returns H_TOO_HARD).
1732 * r5 - r8 contain hcall args,
1733 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1735 hcall_try_real_mode:
1736 ld r3,VCPU_GPR(R3)(r9)
1738 /* sc 1 from userspace - reflect to guest syscall */
1739 bne sc_1_fast_return
1741 cmpldi r3,hcall_real_table_end - hcall_real_table
1743 /* See if this hcall is enabled for in-kernel handling */
1745 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1746 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1748 ld r0, KVM_ENABLED_HCALLS(r4)
1749 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1753 /* Get pointer to handler, if any, and call it */
1754 LOAD_REG_ADDR(r4, hcall_real_table)
1760 mr r3,r9 /* get vcpu pointer */
1761 ld r4,VCPU_GPR(R4)(r9)
1764 beq hcall_real_fallback
1765 ld r4,HSTATE_KVM_VCPU(r13)
1766 std r3,VCPU_GPR(R3)(r4)
1774 li r10, BOOK3S_INTERRUPT_SYSCALL
1775 bl kvmppc_msr_interrupt
1779 /* We've attempted a real mode hcall, but it's punted it back
1780 * to userspace. We need to restore some clobbered volatiles
1781 * before resuming the pass-it-to-qemu path */
1782 hcall_real_fallback:
1783 li r12,BOOK3S_INTERRUPT_SYSCALL
1784 ld r9, HSTATE_KVM_VCPU(r13)
1788 .globl hcall_real_table
1790 .long 0 /* 0 - unused */
1791 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1792 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1793 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1794 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
1795 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
1796 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1797 #ifdef CONFIG_SPAPR_TCE_IOMMU
1798 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1799 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
1804 .long 0 /* 0x24 - H_SET_SPRG0 */
1805 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1806 .long DOTSYM(kvmppc_rm_h_page_init) - hcall_real_table
1820 #ifdef CONFIG_KVM_XICS
1821 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1822 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1823 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1824 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
1825 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1827 .long 0 /* 0x64 - H_EOI */
1828 .long 0 /* 0x68 - H_CPPR */
1829 .long 0 /* 0x6c - H_IPI */
1830 .long 0 /* 0x70 - H_IPOLL */
1831 .long 0 /* 0x74 - H_XIRR */
1859 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1860 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
1876 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1880 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
1881 #ifdef CONFIG_SPAPR_TCE_IOMMU
1882 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
1883 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
1999 #ifdef CONFIG_KVM_XICS
2000 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2002 .long 0 /* 0x2fc - H_XIRR_X*/
2004 .long DOTSYM(kvmppc_rm_h_random) - hcall_real_table
2005 .globl hcall_real_table_end
2006 hcall_real_table_end:
2008 _GLOBAL(kvmppc_h_set_xdabr)
2009 EXPORT_SYMBOL_GPL(kvmppc_h_set_xdabr)
2010 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2012 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2015 6: li r3, H_PARAMETER
2018 _GLOBAL(kvmppc_h_set_dabr)
2019 EXPORT_SYMBOL_GPL(kvmppc_h_set_dabr)
2020 li r5, DABRX_USER | DABRX_KERNEL
2024 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2025 std r4,VCPU_DABR(r3)
2026 stw r5, VCPU_DABRX(r3)
2027 mtspr SPRN_DABRX, r5
2028 /* Work around P7 bug where DABR can get corrupted on mtspr */
2029 1: mtspr SPRN_DABR,r4
2038 LOAD_REG_ADDR(r11, dawr_force_enable)
2045 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2046 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2047 rlwimi r5, r4, 2, DAWRX_WT
2049 std r4, VCPU_DAWR0(r3)
2050 std r5, VCPU_DAWRX0(r3)
2052 * If came in through the real mode hcall handler then it is necessary
2053 * to write the registers since the return path won't. Otherwise it is
2054 * sufficient to store then in the vcpu struct as they will be loaded
2055 * next time the vcpu is run.
2058 andi. r6, r6, MSR_DR /* in real mode? */
2060 mtspr SPRN_DAWR0, r4
2061 mtspr SPRN_DAWRX0, r5
2065 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2067 std r11,VCPU_MSR(r3)
2069 stb r0,VCPU_CEDED(r3)
2070 sync /* order setting ceded vs. testing prodded */
2071 lbz r5,VCPU_PRODDED(r3)
2073 bne kvm_cede_prodded
2074 li r12,0 /* set trap to 0 to say hcall is handled */
2075 stw r12,VCPU_TRAP(r3)
2077 std r0,VCPU_GPR(R3)(r3)
2080 * Set our bit in the bitmask of napping threads unless all the
2081 * other threads are already napping, in which case we send this
2084 ld r5,HSTATE_KVM_VCORE(r13)
2085 lbz r6,HSTATE_PTID(r13)
2086 lwz r8,VCORE_ENTRY_EXIT(r5)
2090 addi r6,r5,VCORE_NAPPING_THREADS
2097 /* order napping_threads update vs testing entry_exit_map */
2100 stb r0,HSTATE_NAPPING(r13)
2101 lwz r7,VCORE_ENTRY_EXIT(r5)
2103 bge 33f /* another thread already exiting */
2106 * Although not specifically required by the architecture, POWER7
2107 * preserves the following registers in nap mode, even if an SMT mode
2108 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2109 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2111 /* Save non-volatile GPRs */
2112 std r14, VCPU_GPR(R14)(r3)
2113 std r15, VCPU_GPR(R15)(r3)
2114 std r16, VCPU_GPR(R16)(r3)
2115 std r17, VCPU_GPR(R17)(r3)
2116 std r18, VCPU_GPR(R18)(r3)
2117 std r19, VCPU_GPR(R19)(r3)
2118 std r20, VCPU_GPR(R20)(r3)
2119 std r21, VCPU_GPR(R21)(r3)
2120 std r22, VCPU_GPR(R22)(r3)
2121 std r23, VCPU_GPR(R23)(r3)
2122 std r24, VCPU_GPR(R24)(r3)
2123 std r25, VCPU_GPR(R25)(r3)
2124 std r26, VCPU_GPR(R26)(r3)
2125 std r27, VCPU_GPR(R27)(r3)
2126 std r28, VCPU_GPR(R28)(r3)
2127 std r29, VCPU_GPR(R29)(r3)
2128 std r30, VCPU_GPR(R30)(r3)
2129 std r31, VCPU_GPR(R31)(r3)
2134 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2137 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
2139 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2141 ld r3, HSTATE_KVM_VCPU(r13)
2143 li r5, 0 /* don't preserve non-vol regs */
2144 bl kvmppc_save_tm_hv
2150 * Set DEC to the smaller of DEC and HDEC, so that we wake
2151 * no later than the end of our timeslice (HDEC interrupts
2152 * don't wake us from nap).
2163 /* save expiry time of guest decrementer */
2165 ld r4, HSTATE_KVM_VCPU(r13)
2166 ld r5, HSTATE_KVM_VCORE(r13)
2167 ld r6, VCORE_TB_OFFSET_APPL(r5)
2168 subf r3, r6, r3 /* convert to host TB value */
2169 std r3, VCPU_DEC_EXPIRES(r4)
2171 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2172 ld r4, HSTATE_KVM_VCPU(r13)
2173 addi r3, r4, VCPU_TB_CEDE
2174 bl kvmhv_accumulate_time
2177 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2179 /* Go back to host stack */
2180 ld r1, HSTATE_HOST_R1(r13)
2183 * Take a nap until a decrementer or external or doobell interrupt
2184 * occurs, with PECE1 and PECE0 set in LPCR.
2185 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2186 * Also clear the runlatch bit before napping.
2189 mfspr r0, SPRN_CTRLF
2191 mtspr SPRN_CTRLT, r0
2194 stb r0,HSTATE_HWTHREAD_REQ(r13)
2196 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2198 ori r5, r5, LPCR_PECEDH
2199 rlwimi r5, r3, 0, LPCR_PECEDP
2200 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2202 kvm_nap_sequence: /* desired LPCR value in r5 */
2203 li r3, PNV_THREAD_NAP
2207 bl isa206_idle_insn_mayloss
2209 mfspr r0, SPRN_CTRLF
2211 mtspr SPRN_CTRLT, r0
2216 stb r0, PACA_FTRACE_ENABLED(r13)
2218 li r0, KVM_HWTHREAD_IN_KVM
2219 stb r0, HSTATE_HWTHREAD_STATE(r13)
2221 lbz r0, HSTATE_NAPPING(r13)
2222 cmpwi r0, NAPPING_CEDE
2224 cmpwi r0, NAPPING_NOVCPU
2225 beq kvm_novcpu_wakeup
2226 cmpwi r0, NAPPING_UNSPLIT
2227 beq kvm_unsplit_wakeup
2228 twi 31,0,0 /* Nap state must not be zero */
2236 /* Woken by external or decrementer interrupt */
2238 /* get vcpu pointer */
2239 ld r4, HSTATE_KVM_VCPU(r13)
2241 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2242 addi r3, r4, VCPU_TB_RMINTR
2243 bl kvmhv_accumulate_time
2246 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2249 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
2251 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2255 li r5, 0 /* don't preserve non-vol regs */
2256 bl kvmppc_restore_tm_hv
2258 ld r4, HSTATE_KVM_VCPU(r13)
2262 /* load up FP state */
2265 /* Restore guest decrementer */
2266 ld r3, VCPU_DEC_EXPIRES(r4)
2267 ld r5, HSTATE_KVM_VCORE(r13)
2268 ld r6, VCORE_TB_OFFSET_APPL(r5)
2269 add r3, r3, r6 /* convert host TB to guest TB value */
2275 ld r14, VCPU_GPR(R14)(r4)
2276 ld r15, VCPU_GPR(R15)(r4)
2277 ld r16, VCPU_GPR(R16)(r4)
2278 ld r17, VCPU_GPR(R17)(r4)
2279 ld r18, VCPU_GPR(R18)(r4)
2280 ld r19, VCPU_GPR(R19)(r4)
2281 ld r20, VCPU_GPR(R20)(r4)
2282 ld r21, VCPU_GPR(R21)(r4)
2283 ld r22, VCPU_GPR(R22)(r4)
2284 ld r23, VCPU_GPR(R23)(r4)
2285 ld r24, VCPU_GPR(R24)(r4)
2286 ld r25, VCPU_GPR(R25)(r4)
2287 ld r26, VCPU_GPR(R26)(r4)
2288 ld r27, VCPU_GPR(R27)(r4)
2289 ld r28, VCPU_GPR(R28)(r4)
2290 ld r29, VCPU_GPR(R29)(r4)
2291 ld r30, VCPU_GPR(R30)(r4)
2292 ld r31, VCPU_GPR(R31)(r4)
2294 /* Check the wake reason in SRR1 to see why we got here */
2295 bl kvmppc_check_wake_reason
2298 * Restore volatile registers since we could have called a
2299 * C routine in kvmppc_check_wake_reason
2301 * r3 tells us whether we need to return to host or not
2302 * WARNING: it gets checked further down:
2303 * should not modify r3 until this check is done.
2305 ld r4, HSTATE_KVM_VCPU(r13)
2307 /* clear our bit in vcore->napping_threads */
2308 34: ld r5,HSTATE_KVM_VCORE(r13)
2309 lbz r7,HSTATE_PTID(r13)
2312 addi r6,r5,VCORE_NAPPING_THREADS
2318 stb r0,HSTATE_NAPPING(r13)
2320 /* See if the wake reason saved in r3 means we need to exit */
2321 stw r12, VCPU_TRAP(r4)
2325 b maybe_reenter_guest
2327 /* cede when already previously prodded case */
2330 stb r0,VCPU_PRODDED(r3)
2331 sync /* order testing prodded vs. clearing ceded */
2332 stb r0,VCPU_CEDED(r3)
2336 /* we've ceded but we want to give control to the host */
2338 ld r9, HSTATE_KVM_VCPU(r13)
2341 /* Try to do machine check recovery in real mode */
2342 machine_check_realmode:
2343 mr r3, r9 /* get vcpu pointer */
2344 bl kvmppc_realmode_machine_check
2346 /* all machine checks go to virtual mode for further handling */
2347 ld r9, HSTATE_KVM_VCPU(r13)
2348 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2352 * Call C code to handle a HMI in real mode.
2353 * Only the primary thread does the call, secondary threads are handled
2354 * by calling hmi_exception_realmode() after kvmppc_hv_entry returns.
2355 * r9 points to the vcpu on entry
2358 lbz r0, HSTATE_PTID(r13)
2361 bl kvmppc_realmode_hmi_handler
2362 ld r9, HSTATE_KVM_VCPU(r13)
2363 li r12, BOOK3S_INTERRUPT_HMI
2367 * Check the reason we woke from nap, and take appropriate action.
2369 * 0 if nothing needs to be done
2370 * 1 if something happened that needs to be handled by the host
2371 * -1 if there was a guest wakeup (IPI or msgsnd)
2372 * -2 if we handled a PCI passthrough interrupt (returned by
2373 * kvmppc_read_intr only)
2375 * Also sets r12 to the interrupt vector for any interrupt that needs
2376 * to be handled now by the host (0x500 for external interrupt), or zero.
2377 * Modifies all volatile registers (since it may call a C function).
2378 * This routine calls kvmppc_read_intr, a C function, if an external
2379 * interrupt is pending.
2381 kvmppc_check_wake_reason:
2384 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2386 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2387 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2388 cmpwi r6, 8 /* was it an external interrupt? */
2389 beq 7f /* if so, see what it was */
2392 cmpwi r6, 6 /* was it the decrementer? */
2395 cmpwi r6, 5 /* privileged doorbell? */
2397 cmpwi r6, 3 /* hypervisor doorbell? */
2399 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2400 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2402 li r3, 1 /* anything else, return 1 */
2405 /* hypervisor doorbell */
2406 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2409 * Clear the doorbell as we will invoke the handler
2410 * explicitly in the guest exit path.
2412 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2414 /* see if it's a host IPI */
2416 lbz r0, HSTATE_HOST_IPI(r13)
2419 /* if not, return -1 */
2423 /* Woken up due to Hypervisor maintenance interrupt */
2424 4: li r12, BOOK3S_INTERRUPT_HMI
2428 /* external interrupt - create a stack frame so we can call C */
2430 std r0, PPC_LR_STKOFF(r1)
2431 stdu r1, -PPC_MIN_STKFRM(r1)
2434 li r12, BOOK3S_INTERRUPT_EXTERNAL
2439 * Return code of 2 means PCI passthrough interrupt, but
2440 * we need to return back to host to complete handling the
2441 * interrupt. Trap reason is expected in r12 by guest
2444 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2446 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2447 addi r1, r1, PPC_MIN_STKFRM
2452 * Save away FP, VMX and VSX registers.
2454 * N.B. r30 and r31 are volatile across this function,
2455 * thus it is not callable from C.
2462 #ifdef CONFIG_ALTIVEC
2464 oris r8,r8,MSR_VEC@h
2465 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2469 oris r8,r8,MSR_VSX@h
2470 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2473 addi r3,r3,VCPU_FPRS
2475 #ifdef CONFIG_ALTIVEC
2477 addi r3,r31,VCPU_VRS
2479 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2481 mfspr r6,SPRN_VRSAVE
2482 stw r6,VCPU_VRSAVE(r31)
2487 * Load up FP, VMX and VSX registers
2489 * N.B. r30 and r31 are volatile across this function,
2490 * thus it is not callable from C.
2497 #ifdef CONFIG_ALTIVEC
2499 oris r8,r8,MSR_VEC@h
2500 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2504 oris r8,r8,MSR_VSX@h
2505 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2508 addi r3,r4,VCPU_FPRS
2510 #ifdef CONFIG_ALTIVEC
2512 addi r3,r31,VCPU_VRS
2514 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2516 lwz r7,VCPU_VRSAVE(r31)
2517 mtspr SPRN_VRSAVE,r7
2522 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2524 * Save transactional state and TM-related registers.
2525 * Called with r3 pointing to the vcpu struct and r4 containing
2526 * the guest MSR value.
2527 * r5 is non-zero iff non-volatile register state needs to be maintained.
2528 * If r5 == 0, this can modify all checkpointed registers, but
2529 * restores r1 and r2 before exit.
2531 _GLOBAL_TOC(kvmppc_save_tm_hv)
2532 EXPORT_SYMBOL_GPL(kvmppc_save_tm_hv)
2533 /* See if we need to handle fake suspend mode */
2536 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
2538 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
2540 beq __kvmppc_save_tm
2542 /* The following code handles the fake_suspend = 1 case */
2544 std r0, PPC_LR_STKOFF(r1)
2545 stdu r1, -TM_FRAME_SIZE(r1)
2550 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2553 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
2556 bl pnv_power9_force_smt4_catch
2557 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
2561 * It's possible that treclaim. may modify registers, if we have lost
2562 * track of fake-suspend state in the guest due to it using rfscv.
2563 * Save and restore registers in case this occurs.
2568 /* SPRN_TAR would need to be saved here if the kernel ever used it */
2576 std r1, HSTATE_HOST_R1(r13)
2578 /* We have to treclaim here because that's the only way to do S->N */
2579 li r3, TM_CAUSE_KVM_RESCHED
2583 ld r1, HSTATE_HOST_R1(r13)
2597 * We were in fake suspend, so we are not going to save the
2598 * register state as the guest checkpointed state (since
2599 * we already have it), therefore we can now use any volatile GPR.
2600 * In fact treclaim in fake suspend state doesn't modify
2605 bl pnv_power9_force_smt4_release
2606 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
2610 mfspr r3, SPRN_PSSCR
2611 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
2612 li r0, PSSCR_FAKE_SUSPEND
2614 mtspr SPRN_PSSCR, r3
2616 /* Don't save TEXASR, use value from last exit in real suspend state */
2617 ld r9, HSTATE_KVM_VCPU(r13)
2618 mfspr r5, SPRN_TFHAR
2619 mfspr r6, SPRN_TFIAR
2620 std r5, VCPU_TFHAR(r9)
2621 std r6, VCPU_TFIAR(r9)
2623 addi r1, r1, TM_FRAME_SIZE
2624 ld r0, PPC_LR_STKOFF(r1)
2629 * Restore transactional state and TM-related registers.
2630 * Called with r3 pointing to the vcpu struct
2631 * and r4 containing the guest MSR value.
2632 * r5 is non-zero iff non-volatile register state needs to be maintained.
2633 * This potentially modifies all checkpointed registers.
2634 * It restores r1 and r2 from the PACA.
2636 _GLOBAL_TOC(kvmppc_restore_tm_hv)
2637 EXPORT_SYMBOL_GPL(kvmppc_restore_tm_hv)
2639 * If we are doing TM emulation for the guest on a POWER9 DD2,
2640 * then we don't actually do a trechkpt -- we either set up
2641 * fake-suspend mode, or emulate a TM rollback.
2644 b __kvmppc_restore_tm
2645 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
2647 std r0, PPC_LR_STKOFF(r1)
2650 stb r0, HSTATE_FAKE_SUSPEND(r13)
2652 /* Turn on TM so we can restore TM SPRs */
2655 rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
2659 * The user may change these outside of a transaction, so they must
2660 * always be context switched.
2662 ld r5, VCPU_TFHAR(r3)
2663 ld r6, VCPU_TFIAR(r3)
2664 ld r7, VCPU_TEXASR(r3)
2665 mtspr SPRN_TFHAR, r5
2666 mtspr SPRN_TFIAR, r6
2667 mtspr SPRN_TEXASR, r7
2669 rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
2670 beqlr /* TM not active in guest */
2672 /* Make sure the failure summary is set */
2673 oris r7, r7, (TEXASR_FS)@h
2674 mtspr SPRN_TEXASR, r7
2676 cmpwi r5, 1 /* check for suspended state */
2678 stb r5, HSTATE_FAKE_SUSPEND(r13)
2679 b 9f /* and return */
2680 10: stdu r1, -PPC_MIN_STKFRM(r1)
2681 /* guest is in transactional state, so simulate rollback */
2682 bl kvmhv_emulate_tm_rollback
2684 addi r1, r1, PPC_MIN_STKFRM
2685 9: ld r0, PPC_LR_STKOFF(r1)
2688 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2691 * We come here if we get any exception or interrupt while we are
2692 * executing host real mode code while in guest MMU context.
2693 * r12 is (CR << 32) | vector
2694 * r13 points to our PACA
2695 * r12 is saved in HSTATE_SCRATCH0(r13)
2696 * r9 is saved in HSTATE_SCRATCH2(r13)
2697 * r13 is saved in HSPRG1
2698 * cfar is saved in HSTATE_CFAR(r13)
2699 * ppr is saved in HSTATE_PPR(r13)
2701 kvmppc_bad_host_intr:
2703 * Switch to the emergency stack, but start half-way down in
2704 * case we were already on it.
2708 ld r1, PACAEMERGSP(r13)
2709 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
2722 mfspr r3, SPRN_HSRR0
2723 mfspr r4, SPRN_HSRR1
2725 mfspr r6, SPRN_HDSISR
2727 1: mfspr r3, SPRN_SRR0
2730 mfspr r6, SPRN_DSISR
2735 ld r9, HSTATE_SCRATCH2(r13)
2736 ld r12, HSTATE_SCRATCH0(r13)
2741 ld r5, HSTATE_CFAR(r13)
2742 std r5, ORIG_GPR3(r1)
2746 lbz r6, PACAIRQSOFTMASK(r13)
2752 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
2753 std r3, STACK_FRAME_OVERHEAD-16(r1)
2756 * XXX On POWER7 and POWER8, we just spin here since we don't
2757 * know what the other threads are doing (and we don't want to
2758 * coordinate with them) - but at least we now have register state
2759 * in memory that we might be able to look at from another CPU.
2764 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2765 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2766 * r11 has the guest MSR value (in/out)
2767 * r9 has a vcpu pointer (in)
2768 * r0 is used as a scratch register
2770 kvmppc_msr_interrupt:
2771 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2772 cmpwi r0, 2 /* Check if we are in transactional state.. */
2773 ld r11, VCPU_INTR_MSR(r9)
2775 /* ... if transactional, change to suspended */
2777 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2781 * Load up guest PMU state. R3 points to the vcpu struct.
2783 _GLOBAL(kvmhv_load_guest_pmu)
2784 EXPORT_SYMBOL_GPL(kvmhv_load_guest_pmu)
2788 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
2789 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
2792 ld r3, VCPU_MMCR(r4)
2793 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
2794 cmpwi r5, MMCR0_PMAO
2795 beql kvmppc_fix_pmao
2796 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
2797 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
2798 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
2799 lwz r6, VCPU_PMC + 8(r4)
2800 lwz r7, VCPU_PMC + 12(r4)
2801 lwz r8, VCPU_PMC + 16(r4)
2802 lwz r9, VCPU_PMC + 20(r4)
2809 ld r3, VCPU_MMCR(r4)
2810 ld r5, VCPU_MMCR + 8(r4)
2811 ld r6, VCPU_MMCRA(r4)
2812 ld r7, VCPU_SIAR(r4)
2813 ld r8, VCPU_SDAR(r4)
2814 mtspr SPRN_MMCR1, r5
2815 mtspr SPRN_MMCRA, r6
2819 ld r5, VCPU_MMCR + 24(r4)
2820 ld r6, VCPU_SIER + 8(r4)
2821 ld r7, VCPU_SIER + 16(r4)
2822 mtspr SPRN_MMCR3, r5
2823 mtspr SPRN_SIER2, r6
2824 mtspr SPRN_SIER3, r7
2825 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
2827 ld r5, VCPU_MMCR + 16(r4)
2828 ld r6, VCPU_SIER(r4)
2829 mtspr SPRN_MMCR2, r5
2831 BEGIN_FTR_SECTION_NESTED(96)
2832 lwz r7, VCPU_PMC + 24(r4)
2833 lwz r8, VCPU_PMC + 28(r4)
2834 ld r9, VCPU_MMCRS(r4)
2835 mtspr SPRN_SPMC1, r7
2836 mtspr SPRN_SPMC2, r8
2837 mtspr SPRN_MMCRS, r9
2838 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
2839 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2840 mtspr SPRN_MMCR0, r3
2846 * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
2848 _GLOBAL(kvmhv_load_host_pmu)
2849 EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
2851 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
2853 beq 23f /* skip if not */
2855 ld r3, HSTATE_MMCR0(r13)
2856 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
2857 cmpwi r4, MMCR0_PMAO
2858 beql kvmppc_fix_pmao
2859 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
2860 lwz r3, HSTATE_PMC1(r13)
2861 lwz r4, HSTATE_PMC2(r13)
2862 lwz r5, HSTATE_PMC3(r13)
2863 lwz r6, HSTATE_PMC4(r13)
2864 lwz r8, HSTATE_PMC5(r13)
2865 lwz r9, HSTATE_PMC6(r13)
2872 ld r3, HSTATE_MMCR0(r13)
2873 ld r4, HSTATE_MMCR1(r13)
2874 ld r5, HSTATE_MMCRA(r13)
2875 ld r6, HSTATE_SIAR(r13)
2876 ld r7, HSTATE_SDAR(r13)
2877 mtspr SPRN_MMCR1, r4
2878 mtspr SPRN_MMCRA, r5
2882 ld r8, HSTATE_MMCR2(r13)
2883 ld r9, HSTATE_SIER(r13)
2884 mtspr SPRN_MMCR2, r8
2886 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2888 ld r5, HSTATE_MMCR3(r13)
2889 ld r6, HSTATE_SIER2(r13)
2890 ld r7, HSTATE_SIER3(r13)
2891 mtspr SPRN_MMCR3, r5
2892 mtspr SPRN_SIER2, r6
2893 mtspr SPRN_SIER3, r7
2894 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
2895 mtspr SPRN_MMCR0, r3
2901 * Save guest PMU state into the vcpu struct.
2902 * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
2904 _GLOBAL(kvmhv_save_guest_pmu)
2905 EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
2910 * POWER8 seems to have a hardware bug where setting
2911 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
2912 * when some counters are already negative doesn't seem
2913 * to cause a performance monitor alert (and hence interrupt).
2914 * The effect of this is that when saving the PMU state,
2915 * if there is no PMU alert pending when we read MMCR0
2916 * before freezing the counters, but one becomes pending
2917 * before we read the counters, we lose it.
2918 * To work around this, we need a way to freeze the counters
2919 * before reading MMCR0. Normally, freezing the counters
2920 * is done by writing MMCR0 (to set MMCR0[FC]) which
2921 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
2922 * we can also freeze the counters using MMCR2, by writing
2923 * 1s to all the counter freeze condition bits (there are
2924 * 9 bits each for 6 counters).
2926 li r3, -1 /* set all freeze bits */
2928 mfspr r10, SPRN_MMCR2
2929 mtspr SPRN_MMCR2, r3
2931 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2933 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
2934 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
2935 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
2936 mfspr r6, SPRN_MMCRA
2937 /* Clear MMCRA in order to disable SDAR updates */
2939 mtspr SPRN_MMCRA, r7
2941 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
2943 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
2945 21: mfspr r5, SPRN_MMCR1
2948 std r4, VCPU_MMCR(r9)
2949 std r5, VCPU_MMCR + 8(r9)
2950 std r6, VCPU_MMCRA(r9)
2952 std r10, VCPU_MMCR + 16(r9)
2953 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2955 mfspr r5, SPRN_MMCR3
2956 mfspr r6, SPRN_SIER2
2957 mfspr r7, SPRN_SIER3
2958 std r5, VCPU_MMCR + 24(r9)
2959 std r6, VCPU_SIER + 8(r9)
2960 std r7, VCPU_SIER + 16(r9)
2961 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
2962 std r7, VCPU_SIAR(r9)
2963 std r8, VCPU_SDAR(r9)
2970 stw r3, VCPU_PMC(r9)
2971 stw r4, VCPU_PMC + 4(r9)
2972 stw r5, VCPU_PMC + 8(r9)
2973 stw r6, VCPU_PMC + 12(r9)
2974 stw r7, VCPU_PMC + 16(r9)
2975 stw r8, VCPU_PMC + 20(r9)
2978 std r5, VCPU_SIER(r9)
2979 BEGIN_FTR_SECTION_NESTED(96)
2980 mfspr r6, SPRN_SPMC1
2981 mfspr r7, SPRN_SPMC2
2982 mfspr r8, SPRN_MMCRS
2983 stw r6, VCPU_PMC + 24(r9)
2984 stw r7, VCPU_PMC + 28(r9)
2985 std r8, VCPU_MMCRS(r9)
2987 mtspr SPRN_MMCRS, r4
2988 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
2989 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2993 * This works around a hardware bug on POWER8E processors, where
2994 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2995 * performance monitor interrupt. Instead, when we need to have
2996 * an interrupt pending, we have to arrange for a counter to overflow.
3000 mtspr SPRN_MMCR2, r3
3001 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3002 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3003 mtspr SPRN_MMCR0, r3
3010 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3012 * Start timing an activity
3013 * r3 = pointer to time accumulation struct, r4 = vcpu
3016 ld r5, HSTATE_KVM_VCORE(r13)
3017 ld r6, VCORE_TB_OFFSET_APPL(r5)
3019 subf r5, r6, r5 /* subtract current timebase offset */
3020 std r3, VCPU_CUR_ACTIVITY(r4)
3021 std r5, VCPU_ACTIVITY_START(r4)
3025 * Accumulate time to one activity and start another.
3026 * r3 = pointer to new time accumulation struct, r4 = vcpu
3028 kvmhv_accumulate_time:
3029 ld r5, HSTATE_KVM_VCORE(r13)
3030 ld r8, VCORE_TB_OFFSET_APPL(r5)
3031 ld r5, VCPU_CUR_ACTIVITY(r4)
3032 ld r6, VCPU_ACTIVITY_START(r4)
3033 std r3, VCPU_CUR_ACTIVITY(r4)
3035 subf r7, r8, r7 /* subtract current timebase offset */
3036 std r7, VCPU_ACTIVITY_START(r4)
3040 ld r8, TAS_SEQCOUNT(r5)
3043 std r8, TAS_SEQCOUNT(r5)
3045 ld r7, TAS_TOTAL(r5)
3047 std r7, TAS_TOTAL(r5)
3053 3: std r3, TAS_MIN(r5)
3059 std r8, TAS_SEQCOUNT(r5)