2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
37 * Call kvmppc_hv_entry in real mode.
38 * Must be called with interrupts hard-disabled.
42 * LR = return address to continue at after eventually re-enabling MMU
44 _GLOBAL(kvmppc_hv_entry_trampoline)
46 std r0, PPC_LR_STKOFF(r1)
49 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
54 mtmsrd r0,1 /* clear RI in MSR */
62 /* Back from guest - restore host state and return to caller */
64 /* Restore host DABR and DABRX */
65 ld r5,HSTATE_DABR(r13)
75 * Reload DEC. HDEC interrupts were disabled when
76 * we reloaded the host's LPCR value.
78 ld r3, HSTATE_DECEXP(r13)
83 /* Reload the host's PMU registers */
84 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
85 lbz r4, LPPACA_PMCINUSE(r3)
87 beq 23f /* skip if not */
88 lwz r3, HSTATE_PMC(r13)
89 lwz r4, HSTATE_PMC + 4(r13)
90 lwz r5, HSTATE_PMC + 8(r13)
91 lwz r6, HSTATE_PMC + 12(r13)
92 lwz r8, HSTATE_PMC + 16(r13)
93 lwz r9, HSTATE_PMC + 20(r13)
95 lwz r10, HSTATE_PMC + 24(r13)
96 lwz r11, HSTATE_PMC + 28(r13)
97 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
107 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
108 ld r3, HSTATE_MMCR(r13)
109 ld r4, HSTATE_MMCR + 8(r13)
110 ld r5, HSTATE_MMCR + 16(r13)
118 * For external and machine check interrupts, we need
119 * to call the Linux handler to process the interrupt.
120 * We do that by jumping to absolute address 0x500 for
121 * external interrupts, or the machine_check_fwnmi label
122 * for machine checks (since firmware might have patched
123 * the vector area at 0x200). The [h]rfid at the end of the
124 * handler will return to the book3s_hv_interrupts.S code.
125 * For other interrupts we do the rfid to get back
126 * to the book3s_hv_interrupts.S code here.
128 ld r8, 112+PPC_LR_STKOFF(r1)
130 ld r7, HSTATE_HOST_MSR(r13)
132 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
133 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
136 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
138 /* RFI into the highmem handler, or branch to interrupt handler */
142 mtmsrd r6, 1 /* Clear RI in MSR */
145 beqa 0x500 /* external interrupt (PPC970) */
146 beq cr1, 13f /* machine check */
149 /* On POWER7, we have external interrupts set to use HSRR0/1 */
150 11: mtspr SPRN_HSRR0, r8
154 13: b machine_check_fwnmi
157 * We come in here when wakened from nap mode on a secondary hw thread.
158 * Relocation is off and most register values are lost.
159 * r13 points to the PACA.
161 .globl kvm_start_guest
163 ld r1,PACAEMERGSP(r13)
164 subi r1,r1,STACK_FRAME_OVERHEAD
167 li r0,KVM_HWTHREAD_IN_KVM
168 stb r0,HSTATE_HWTHREAD_STATE(r13)
170 /* NV GPR values from power7_idle() will no longer be valid */
172 stb r0,PACA_NAPSTATELOST(r13)
174 /* were we napping due to cede? */
175 lbz r0,HSTATE_NAPPING(r13)
180 * We weren't napping due to cede, so this must be a secondary
181 * thread being woken up to run a guest, or being woken up due
182 * to a stray IPI. (Or due to some machine check or hypervisor
183 * maintenance interrupt while the core is in KVM.)
186 /* Check the wake reason in SRR1 to see why we got here */
188 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
189 cmpwi r3,4 /* was it an external interrupt? */
191 ld r5,HSTATE_XICS_PHYS(r13)
192 li r7,XICS_XIRR /* if it was an external interrupt, */
193 lwzcix r8,r5,r7 /* get and ack the interrupt */
195 clrldi. r9,r8,40 /* get interrupt source ID. */
196 beq 28f /* none there? */
197 cmpwi r9,XICS_IPI /* was it an IPI? */
201 stbcix r0,r5,r6 /* clear IPI */
202 stwcix r8,r5,r7 /* EOI the interrupt */
203 sync /* order loading of vcpu after that */
205 /* get vcpu pointer, NULL if we have no vcpu to run */
206 ld r4,HSTATE_KVM_VCPU(r13)
208 /* if we have no vcpu to run, go back to sleep */
212 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
214 28: /* SRR1 said external but ICP said nope?? */
216 29: /* External non-IPI interrupt to offline secondary thread? help?? */
217 stw r8,HSTATE_SAVED_XIRR(r13)
220 30: bl kvmppc_hv_entry
222 /* Back from the guest, go back to nap */
223 /* Clear our vcpu pointer so we don't come back in early */
225 std r0, HSTATE_KVM_VCPU(r13)
227 * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
228 * the nap_count, because once the increment to nap_count is
229 * visible we could be given another vcpu.
232 /* Clear any pending IPI - we're an offline thread */
233 ld r5, HSTATE_XICS_PHYS(r13)
235 lwzcix r3, r5, r7 /* ack any pending interrupt */
236 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
241 stbcix r0, r5, r6 /* clear the IPI */
242 stwcix r3, r5, r7 /* EOI it */
245 /* increment the nap count and then go to nap mode */
246 ld r4, HSTATE_KVM_VCORE(r13)
247 addi r4, r4, VCORE_NAP_COUNT
254 li r0, KVM_HWTHREAD_IN_NAP
255 stb r0, HSTATE_HWTHREAD_STATE(r13)
258 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
261 std r0, HSTATE_SCRATCH0(r13)
263 ld r0, HSTATE_SCRATCH0(r13)
269 /******************************************************************************
273 *****************************************************************************/
275 .global kvmppc_hv_entry
284 * all other volatile GPRS = free
287 std r0, PPC_LR_STKOFF(r1)
290 /* Set partition DABR */
291 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
298 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
300 /* Load guest PMU registers */
301 /* R4 is live here (vcpu pointer) */
303 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
304 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
306 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
307 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
308 lwz r6, VCPU_PMC + 8(r4)
309 lwz r7, VCPU_PMC + 12(r4)
310 lwz r8, VCPU_PMC + 16(r4)
311 lwz r9, VCPU_PMC + 20(r4)
313 lwz r10, VCPU_PMC + 24(r4)
314 lwz r11, VCPU_PMC + 28(r4)
315 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
325 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
327 ld r5, VCPU_MMCR + 8(r4)
328 ld r6, VCPU_MMCR + 16(r4)
338 /* Load up FP, VMX and VSX registers */
341 ld r14, VCPU_GPR(R14)(r4)
342 ld r15, VCPU_GPR(R15)(r4)
343 ld r16, VCPU_GPR(R16)(r4)
344 ld r17, VCPU_GPR(R17)(r4)
345 ld r18, VCPU_GPR(R18)(r4)
346 ld r19, VCPU_GPR(R19)(r4)
347 ld r20, VCPU_GPR(R20)(r4)
348 ld r21, VCPU_GPR(R21)(r4)
349 ld r22, VCPU_GPR(R22)(r4)
350 ld r23, VCPU_GPR(R23)(r4)
351 ld r24, VCPU_GPR(R24)(r4)
352 ld r25, VCPU_GPR(R25)(r4)
353 ld r26, VCPU_GPR(R26)(r4)
354 ld r27, VCPU_GPR(R27)(r4)
355 ld r28, VCPU_GPR(R28)(r4)
356 ld r29, VCPU_GPR(R29)(r4)
357 ld r30, VCPU_GPR(R30)(r4)
358 ld r31, VCPU_GPR(R31)(r4)
361 /* Switch DSCR to guest value */
364 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
367 * Set the decrementer to the guest decrementer.
369 ld r8,VCPU_DEC_EXPIRES(r4)
375 ld r5, VCPU_SPRG0(r4)
376 ld r6, VCPU_SPRG1(r4)
377 ld r7, VCPU_SPRG2(r4)
378 ld r8, VCPU_SPRG3(r4)
384 /* Save R1 in the PACA */
385 std r1, HSTATE_HOST_R1(r13)
387 /* Load up DAR and DSISR */
389 lwz r6, VCPU_DSISR(r4)
393 li r6, KVM_GUEST_MODE_HOST_HV
394 stb r6, HSTATE_IN_GUEST(r13)
397 /* Restore AMR and UAMOR, set AMOR to all 1s */
404 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
414 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
416 * POWER7 host -> guest partition switch code.
417 * We don't have to lock against concurrent tlbies,
418 * but we do have to coordinate across hardware threads.
420 /* Increment entry count iff exit count is zero. */
421 ld r5,HSTATE_KVM_VCORE(r13)
422 addi r9,r5,VCORE_ENTRY_EXIT
424 cmpwi r3,0x100 /* any threads starting to exit? */
425 bge secondary_too_late /* if so we're too late to the party */
430 /* Primary thread switches to guest partition. */
431 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
437 li r0,LPID_RSVD /* switch to reserved LPID */
440 mtspr SPRN_SDR1,r6 /* switch to partition page table */
444 /* See if we need to flush the TLB */
445 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
446 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
447 srdi r6,r6,6 /* doubleword number */
448 sldi r6,r6,3 /* address offset */
450 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
456 23: ldarx r7,0,r6 /* if set, clear the bit */
460 li r6,128 /* and flush the TLB */
462 li r7,0x800 /* IS field = 0b10 */
469 /* Add timebase offset onto timebase */
470 22: ld r8,VCORE_TB_OFFSET(r5)
473 mftb r6 /* current host timebase */
475 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
476 mftb r7 /* check if lower 24 bits overflowed */
481 addis r8,r8,0x100 /* if so, increment upper 40 bits */
484 /* Load guest PCR value to select appropriate compat mode */
485 37: ld r7, VCORE_PCR(r5)
491 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
494 /* Secondary threads wait for primary to have done partition switch */
495 20: lbz r0,VCORE_IN_GUEST(r5)
499 /* Set LPCR and RMOR. */
500 10: ld r8,VCORE_LPCR(r5)
506 /* Increment yield count if they have a VPA */
510 lwz r5, LPPACA_YIELDCOUNT(r3)
512 stw r5, LPPACA_YIELDCOUNT(r3)
514 stb r6, VCPU_VPA_DIRTY(r4)
516 /* Check if HDEC expires soon */
519 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
523 /* Save purr/spurr */
526 std r5,HSTATE_PURR(r13)
527 std r6,HSTATE_SPURR(r13)
535 * PPC970 host -> guest partition switch code.
536 * We have to lock against concurrent tlbies,
537 * using native_tlbie_lock to lock against host tlbies
538 * and kvm->arch.tlbie_lock to lock against guest tlbies.
539 * We also have to invalidate the TLB since its
540 * entries aren't tagged with the LPID.
542 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
544 /* first take native_tlbie_lock */
547 .tc native_tlbie_lock[TC],native_tlbie_lock
549 ld r3,toc_tlbie_lock@toc(2)
550 #ifdef __BIG_ENDIAN__
551 lwz r8,PACA_LOCK_TOKEN(r13)
553 lwz r8,PACAPACAINDEX(r13)
562 ld r5,HSTATE_KVM_VCORE(r13)
563 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
565 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
569 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
572 stw r0,0(r3) /* drop native_tlbie_lock */
574 /* invalidate the whole TLB */
583 /* Take the guest's tlbie_lock */
584 addi r3,r9,KVM_TLBIE_LOCK
592 mtspr SPRN_SDR1,r6 /* switch to partition page table */
594 /* Set up HID4 with the guest's LPID etc. */
599 /* drop the guest's tlbie_lock */
603 /* Check if HDEC expires soon */
606 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
610 /* Enable HDEC interrupts */
613 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
623 /* Load up guest SLB entries */
624 31: lwz r5,VCPU_SLB_MAX(r4)
629 1: ld r8,VCPU_SLB_E(r6)
632 addi r6,r6,VCPU_SLB_SIZE
636 /* Restore state of CTRL run bit; assume 1 on entry */
652 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
656 /* r11 = vcpu->arch.msr & ~MSR_HV */
657 rldicl r11, r11, 63 - MSR_HV_LG, 1
658 rotldi r11, r11, 1 + MSR_HV_LG
661 /* Check if we can deliver an external or decrementer interrupt now */
662 ld r0,VCPU_PENDING_EXC(r4)
663 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
673 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
675 li r0,BOOK3S_INTERRUPT_EXTERNAL
679 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
685 li r0,BOOK3S_INTERRUPT_DECREMENTER
688 /* Move SRR0 and SRR1 into the respective regs */
689 5: mtspr SPRN_SRR0, r6
694 stb r0,VCPU_CEDED(r4) /* cancel cede */
698 /* Activate guest mode, so faults get handled by KVM */
699 li r9, KVM_GUEST_MODE_GUEST_HV
700 stb r9, HSTATE_IN_GUEST(r13)
707 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
710 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
717 ld r1, VCPU_GPR(R1)(r4)
718 ld r2, VCPU_GPR(R2)(r4)
719 ld r3, VCPU_GPR(R3)(r4)
720 ld r5, VCPU_GPR(R5)(r4)
721 ld r6, VCPU_GPR(R6)(r4)
722 ld r7, VCPU_GPR(R7)(r4)
723 ld r8, VCPU_GPR(R8)(r4)
724 ld r9, VCPU_GPR(R9)(r4)
725 ld r10, VCPU_GPR(R10)(r4)
726 ld r11, VCPU_GPR(R11)(r4)
727 ld r12, VCPU_GPR(R12)(r4)
728 ld r13, VCPU_GPR(R13)(r4)
732 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
733 ld r0, VCPU_GPR(R0)(r4)
734 ld r4, VCPU_GPR(R4)(r4)
739 /******************************************************************************
743 *****************************************************************************/
746 * We come here from the first-level interrupt handlers.
748 .globl kvmppc_interrupt_hv
752 * R12 = interrupt vector
754 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
755 * guest R13 saved in SPRN_SCRATCH0
757 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
758 std r9, HSTATE_HOST_R2(r13)
760 lbz r9, HSTATE_IN_GUEST(r13)
761 cmpwi r9, KVM_GUEST_MODE_HOST_HV
762 beq kvmppc_bad_host_intr
763 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
764 cmpwi r9, KVM_GUEST_MODE_GUEST
765 ld r9, HSTATE_HOST_R2(r13)
766 beq kvmppc_interrupt_pr
768 /* We're now back in the host but in guest MMU context */
769 li r9, KVM_GUEST_MODE_HOST_HV
770 stb r9, HSTATE_IN_GUEST(r13)
772 ld r9, HSTATE_KVM_VCPU(r13)
776 std r0, VCPU_GPR(R0)(r9)
777 std r1, VCPU_GPR(R1)(r9)
778 std r2, VCPU_GPR(R2)(r9)
779 std r3, VCPU_GPR(R3)(r9)
780 std r4, VCPU_GPR(R4)(r9)
781 std r5, VCPU_GPR(R5)(r9)
782 std r6, VCPU_GPR(R6)(r9)
783 std r7, VCPU_GPR(R7)(r9)
784 std r8, VCPU_GPR(R8)(r9)
785 ld r0, HSTATE_HOST_R2(r13)
786 std r0, VCPU_GPR(R9)(r9)
787 std r10, VCPU_GPR(R10)(r9)
788 std r11, VCPU_GPR(R11)(r9)
789 ld r3, HSTATE_SCRATCH0(r13)
790 lwz r4, HSTATE_SCRATCH1(r13)
791 std r3, VCPU_GPR(R12)(r9)
794 ld r3, HSTATE_CFAR(r13)
795 std r3, VCPU_CFAR(r9)
796 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
798 ld r4, HSTATE_PPR(r13)
800 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
802 /* Restore R1/R2 so we can handle faults */
803 ld r1, HSTATE_HOST_R1(r13)
808 std r10, VCPU_SRR0(r9)
809 std r11, VCPU_SRR1(r9)
810 andi. r0, r12, 2 /* need to read HSRR0/1? */
812 mfspr r10, SPRN_HSRR0
813 mfspr r11, SPRN_HSRR1
815 1: std r10, VCPU_PC(r9)
816 std r11, VCPU_MSR(r9)
820 std r3, VCPU_GPR(R13)(r9)
823 stw r12,VCPU_TRAP(r9)
825 /* Save HEIR (HV emulation assist reg) in last_inst
826 if this is an HEI (HV emulation interrupt, e40) */
827 li r3,KVM_INST_FETCH_FAILED
829 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
832 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
833 11: stw r3,VCPU_LAST_INST(r9)
835 /* these are volatile across C function calls */
842 /* If this is a page table miss then see if it's theirs or ours */
843 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
845 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
847 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
849 /* See if this is a leftover HDEC interrupt */
850 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
856 /* See if this is an hcall we can handle in real mode */
857 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
858 beq hcall_try_real_mode
860 /* Only handle external interrupts here on arch 206 and later */
862 b ext_interrupt_to_host
863 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
865 /* External interrupt ? */
866 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
867 bne+ ext_interrupt_to_host
869 /* External interrupt, first check for host_ipi. If this is
870 * set, we know the host wants us out so let's do it now
875 bgt ext_interrupt_to_host
877 /* Allright, looks like an IPI for the guest, we need to set MER */
878 /* Check if any CPU is heading out to the host, if so head out too */
879 ld r5, HSTATE_KVM_VCORE(r13)
880 lwz r0, VCORE_ENTRY_EXIT(r5)
882 bge ext_interrupt_to_host
884 /* See if there is a pending interrupt for the guest */
886 ld r0, VCPU_PENDING_EXC(r9)
887 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
888 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
889 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
892 /* And if the guest EE is set, we can deliver immediately, else
893 * we return to the guest with MER set
895 andi. r0, r11, MSR_EE
899 li r10, BOOK3S_INTERRUPT_EXTERNAL
900 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
906 ext_interrupt_to_host:
908 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
909 /* Save more register state */
913 stw r7, VCPU_DSISR(r9)
915 /* don't overwrite fault_dar/fault_dsisr if HDSI */
916 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
918 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
919 std r6, VCPU_FAULT_DAR(r9)
920 stw r7, VCPU_FAULT_DSISR(r9)
922 /* See if it is a machine check */
923 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
924 beq machine_check_realmode
927 /* Save guest CTRL register, set runlatch to 1 */
928 6: mfspr r6,SPRN_CTRLF
935 /* Read the guest SLB and save it away */
936 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
942 andis. r0,r8,SLB_ESID_V@h
944 add r8,r8,r6 /* put index in */
946 std r8,VCPU_SLB_E(r7)
947 std r3,VCPU_SLB_V(r7)
948 addi r7,r7,VCPU_SLB_SIZE
952 stw r5,VCPU_SLB_MAX(r9)
955 * Save the guest PURR/SPURR
963 std r6,VCPU_SPURR(r9)
968 * Restore host PURR/SPURR and add guest times
969 * so that the time in the guest gets accounted.
971 ld r3,HSTATE_PURR(r13)
972 ld r4,HSTATE_SPURR(r13)
977 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
985 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
988 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
990 * POWER7 guest -> host partition switch code.
991 * We don't have to lock against tlbies but we do
992 * have to coordinate the hardware threads.
994 /* Increment the threads-exiting-guest count in the 0xff00
995 bits of vcore->entry_exit_count */
996 ld r5,HSTATE_KVM_VCORE(r13)
997 addi r6,r5,VCORE_ENTRY_EXIT
1002 isync /* order stwcx. vs. reading napping_threads */
1005 * At this point we have an interrupt that we have to pass
1006 * up to the kernel or qemu; we can't handle it in real mode.
1007 * Thus we have to do a partition switch, so we have to
1008 * collect the other threads, if we are the first thread
1009 * to take an interrupt. To do this, we set the HDEC to 0,
1010 * which causes an HDEC interrupt in all threads within 2ns
1011 * because the HDEC register is shared between all 4 threads.
1012 * However, we don't need to bother if this is an HDEC
1013 * interrupt, since the other threads will already be on their
1014 * way here in that case.
1016 cmpwi r3,0x100 /* Are we the first here? */
1018 cmpwi r3,1 /* Are any other threads in the guest? */
1020 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1026 * Send an IPI to any napping threads, since an HDEC interrupt
1027 * doesn't wake CPUs up from nap.
1029 lwz r3,VCORE_NAPPING_THREADS(r5)
1030 lwz r4,VCPU_PTID(r9)
1033 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1035 /* Order entry/exit update vs. IPIs */
1037 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1041 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1044 stbcix r0,r7,r8 /* trigger the IPI */
1046 addi r6,r6,PACA_SIZE
1049 /* Secondary threads wait for primary to do partition switch */
1050 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1051 ld r5,HSTATE_KVM_VCORE(r13)
1052 lwz r3,VCPU_PTID(r9)
1056 13: lbz r3,VCORE_IN_GUEST(r5)
1062 /* Primary thread waits for all the secondaries to exit guest */
1063 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1070 /* Primary thread switches back to host partition */
1071 ld r6,KVM_HOST_SDR1(r4)
1072 lwz r7,KVM_HOST_LPID(r4)
1073 li r8,LPID_RSVD /* switch to reserved LPID */
1076 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1080 /* Subtract timebase offset from timebase */
1081 ld r8,VCORE_TB_OFFSET(r5)
1084 mftb r6 /* current host timebase */
1086 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1087 mftb r7 /* check if lower 24 bits overflowed */
1092 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1096 17: ld r0, VCORE_PCR(r5)
1102 /* Signal secondary CPUs to continue */
1103 stb r0,VCORE_IN_GUEST(r5)
1104 lis r8,0x7fff /* MAX_INT@h */
1107 16: ld r8,KVM_HOST_LPCR(r4)
1113 * PPC970 guest -> host partition switch code.
1114 * We have to lock against concurrent tlbies, and
1115 * we have to flush the whole TLB.
1117 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1119 /* Take the guest's tlbie_lock */
1120 #ifdef __BIG_ENDIAN__
1121 lwz r8,PACA_LOCK_TOKEN(r13)
1123 lwz r8,PACAPACAINDEX(r13)
1125 addi r3,r4,KVM_TLBIE_LOCK
1133 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1135 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1139 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1142 stw r0,0(r3) /* drop guest tlbie_lock */
1144 /* invalidate the whole TLB */
1153 /* take native_tlbie_lock */
1154 ld r3,toc_tlbie_lock@toc(2)
1162 ld r6,KVM_HOST_SDR1(r4)
1163 mtspr SPRN_SDR1,r6 /* switch to host page table */
1165 /* Set up host HID4 value */
1170 stw r0,0(r3) /* drop native_tlbie_lock */
1172 lis r8,0x7fff /* MAX_INT@h */
1175 /* Disable HDEC interrupts */
1178 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1188 /* load host SLB entries */
1189 33: ld r8,PACA_SLBSHADOWPTR(r13)
1191 .rept SLB_NUM_BOLTED
1192 ld r5,SLBSHADOW_SAVEAREA(r8)
1193 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1194 andis. r7,r5,SLB_ESID_V@h
1205 std r5,VCPU_DEC_EXPIRES(r9)
1207 /* Save and reset AMR and UAMOR before turning on the MMU */
1212 std r6,VCPU_UAMOR(r9)
1215 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1217 /* Unset guest mode */
1218 li r0, KVM_GUEST_MODE_NONE
1219 stb r0, HSTATE_IN_GUEST(r13)
1221 /* Switch DSCR back to host value */
1224 ld r7, HSTATE_DSCR(r13)
1225 std r8, VCPU_DSCR(r9)
1227 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1229 /* Save non-volatile GPRs */
1230 std r14, VCPU_GPR(R14)(r9)
1231 std r15, VCPU_GPR(R15)(r9)
1232 std r16, VCPU_GPR(R16)(r9)
1233 std r17, VCPU_GPR(R17)(r9)
1234 std r18, VCPU_GPR(R18)(r9)
1235 std r19, VCPU_GPR(R19)(r9)
1236 std r20, VCPU_GPR(R20)(r9)
1237 std r21, VCPU_GPR(R21)(r9)
1238 std r22, VCPU_GPR(R22)(r9)
1239 std r23, VCPU_GPR(R23)(r9)
1240 std r24, VCPU_GPR(R24)(r9)
1241 std r25, VCPU_GPR(R25)(r9)
1242 std r26, VCPU_GPR(R26)(r9)
1243 std r27, VCPU_GPR(R27)(r9)
1244 std r28, VCPU_GPR(R28)(r9)
1245 std r29, VCPU_GPR(R29)(r9)
1246 std r30, VCPU_GPR(R30)(r9)
1247 std r31, VCPU_GPR(R31)(r9)
1250 mfspr r3, SPRN_SPRG0
1251 mfspr r4, SPRN_SPRG1
1252 mfspr r5, SPRN_SPRG2
1253 mfspr r6, SPRN_SPRG3
1254 std r3, VCPU_SPRG0(r9)
1255 std r4, VCPU_SPRG1(r9)
1256 std r5, VCPU_SPRG2(r9)
1257 std r6, VCPU_SPRG3(r9)
1263 /* Increment yield count if they have a VPA */
1264 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1267 lwz r3, LPPACA_YIELDCOUNT(r8)
1269 stw r3, LPPACA_YIELDCOUNT(r8)
1271 stb r3, VCPU_VPA_DIRTY(r9)
1273 /* Save PMU registers if requested */
1274 /* r8 and cr0.eq are live here */
1276 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1277 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1278 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1279 mfspr r6, SPRN_MMCRA
1281 /* On P7, clear MMCRA in order to disable SDAR updates */
1283 mtspr SPRN_MMCRA, r7
1284 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1286 beq 21f /* if no VPA, save PMU stuff anyway */
1287 lbz r7, LPPACA_PMCINUSE(r8)
1288 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1290 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1292 21: mfspr r5, SPRN_MMCR1
1295 std r4, VCPU_MMCR(r9)
1296 std r5, VCPU_MMCR + 8(r9)
1297 std r6, VCPU_MMCR + 16(r9)
1298 std r7, VCPU_SIAR(r9)
1299 std r8, VCPU_SDAR(r9)
1307 mfspr r10, SPRN_PMC7
1308 mfspr r11, SPRN_PMC8
1309 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1310 stw r3, VCPU_PMC(r9)
1311 stw r4, VCPU_PMC + 4(r9)
1312 stw r5, VCPU_PMC + 8(r9)
1313 stw r6, VCPU_PMC + 12(r9)
1314 stw r7, VCPU_PMC + 16(r9)
1315 stw r8, VCPU_PMC + 20(r9)
1317 stw r10, VCPU_PMC + 24(r9)
1318 stw r11, VCPU_PMC + 28(r9)
1319 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1321 ld r0, 112+PPC_LR_STKOFF(r1)
1326 ld r5,HSTATE_KVM_VCORE(r13)
1328 13: lbz r3,VCORE_IN_GUEST(r5)
1332 li r0, KVM_GUEST_MODE_NONE
1333 stb r0, HSTATE_IN_GUEST(r13)
1334 ld r11,PACA_SLBSHADOWPTR(r13)
1336 .rept SLB_NUM_BOLTED
1337 ld r5,SLBSHADOW_SAVEAREA(r11)
1338 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1339 andis. r7,r5,SLB_ESID_V@h
1347 * Check whether an HDSI is an HPTE not found fault or something else.
1348 * If it is an HPTE not found fault that is due to the guest accessing
1349 * a page that they have mapped but which we have paged out, then
1350 * we continue on with the guest exit path. In all other cases,
1351 * reflect the HDSI to the guest as a DSI.
1355 mfspr r6, SPRN_HDSISR
1356 /* HPTE not found fault or protection fault? */
1357 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1358 beq 1f /* if not, send it to the guest */
1359 andi. r0, r11, MSR_DR /* data relocation enabled? */
1362 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1363 bne 1f /* if no SLB entry found */
1364 4: std r4, VCPU_FAULT_DAR(r9)
1365 stw r6, VCPU_FAULT_DSISR(r9)
1367 /* Search the hash table. */
1368 mr r3, r9 /* vcpu pointer */
1369 li r7, 1 /* data fault */
1370 bl .kvmppc_hpte_hv_fault
1371 ld r9, HSTATE_KVM_VCPU(r13)
1373 ld r11, VCPU_MSR(r9)
1374 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1375 cmpdi r3, 0 /* retry the instruction */
1377 cmpdi r3, -1 /* handle in kernel mode */
1379 cmpdi r3, -2 /* MMIO emulation; need instr word */
1382 /* Synthesize a DSI for the guest */
1383 ld r4, VCPU_FAULT_DAR(r9)
1385 1: mtspr SPRN_DAR, r4
1386 mtspr SPRN_DSISR, r6
1387 mtspr SPRN_SRR0, r10
1388 mtspr SPRN_SRR1, r11
1389 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1390 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1392 fast_interrupt_c_return:
1393 6: ld r7, VCPU_CTR(r9)
1394 lwz r8, VCPU_XER(r9)
1400 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1401 ld r5, KVM_VRMA_SLB_V(r5)
1404 /* If this is for emulated MMIO, load the instruction word */
1405 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1407 /* Set guest mode to 'jump over instruction' so if lwz faults
1408 * we'll just continue at the next IP. */
1409 li r0, KVM_GUEST_MODE_SKIP
1410 stb r0, HSTATE_IN_GUEST(r13)
1412 /* Do the access with MSR:DR enabled */
1414 ori r4, r3, MSR_DR /* Enable paging for data */
1419 /* Store the result */
1420 stw r8, VCPU_LAST_INST(r9)
1422 /* Unset guest mode. */
1423 li r0, KVM_GUEST_MODE_HOST_HV
1424 stb r0, HSTATE_IN_GUEST(r13)
1428 * Similarly for an HISI, reflect it to the guest as an ISI unless
1429 * it is an HPTE not found fault for a page that we have paged out.
1432 andis. r0, r11, SRR1_ISI_NOPT@h
1434 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1437 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1438 bne 1f /* if no SLB entry found */
1440 /* Search the hash table. */
1441 mr r3, r9 /* vcpu pointer */
1444 li r7, 0 /* instruction fault */
1445 bl .kvmppc_hpte_hv_fault
1446 ld r9, HSTATE_KVM_VCPU(r13)
1448 ld r11, VCPU_MSR(r9)
1449 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1450 cmpdi r3, 0 /* retry the instruction */
1451 beq fast_interrupt_c_return
1452 cmpdi r3, -1 /* handle in kernel mode */
1455 /* Synthesize an ISI for the guest */
1457 1: mtspr SPRN_SRR0, r10
1458 mtspr SPRN_SRR1, r11
1459 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1460 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1462 b fast_interrupt_c_return
1464 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1465 ld r5, KVM_VRMA_SLB_V(r6)
1469 * Try to handle an hcall in real mode.
1470 * Returns to the guest if we handle it, or continues on up to
1471 * the kernel if we can't (i.e. if we don't have a handler for
1472 * it, or if the handler returns H_TOO_HARD).
1474 .globl hcall_try_real_mode
1475 hcall_try_real_mode:
1476 ld r3,VCPU_GPR(R3)(r9)
1480 cmpldi r3,hcall_real_table_end - hcall_real_table
1482 LOAD_REG_ADDR(r4, hcall_real_table)
1488 mr r3,r9 /* get vcpu pointer */
1489 ld r4,VCPU_GPR(R4)(r9)
1492 beq hcall_real_fallback
1493 ld r4,HSTATE_KVM_VCPU(r13)
1494 std r3,VCPU_GPR(R3)(r4)
1499 /* We've attempted a real mode hcall, but it's punted it back
1500 * to userspace. We need to restore some clobbered volatiles
1501 * before resuming the pass-it-to-qemu path */
1502 hcall_real_fallback:
1503 li r12,BOOK3S_INTERRUPT_SYSCALL
1504 ld r9, HSTATE_KVM_VCPU(r13)
1508 .globl hcall_real_table
1510 .long 0 /* 0 - unused */
1511 .long .kvmppc_h_remove - hcall_real_table
1512 .long .kvmppc_h_enter - hcall_real_table
1513 .long .kvmppc_h_read - hcall_real_table
1514 .long 0 /* 0x10 - H_CLEAR_MOD */
1515 .long 0 /* 0x14 - H_CLEAR_REF */
1516 .long .kvmppc_h_protect - hcall_real_table
1517 .long 0 /* 0x1c - H_GET_TCE */
1518 .long .kvmppc_h_put_tce - hcall_real_table
1519 .long 0 /* 0x24 - H_SET_SPRG0 */
1520 .long .kvmppc_h_set_dabr - hcall_real_table
1535 #ifdef CONFIG_KVM_XICS
1536 .long .kvmppc_rm_h_eoi - hcall_real_table
1537 .long .kvmppc_rm_h_cppr - hcall_real_table
1538 .long .kvmppc_rm_h_ipi - hcall_real_table
1539 .long 0 /* 0x70 - H_IPOLL */
1540 .long .kvmppc_rm_h_xirr - hcall_real_table
1542 .long 0 /* 0x64 - H_EOI */
1543 .long 0 /* 0x68 - H_CPPR */
1544 .long 0 /* 0x6c - H_IPI */
1545 .long 0 /* 0x70 - H_IPOLL */
1546 .long 0 /* 0x74 - H_XIRR */
1574 .long .kvmppc_h_cede - hcall_real_table
1591 .long .kvmppc_h_bulk_remove - hcall_real_table
1592 hcall_real_table_end:
1598 _GLOBAL(kvmppc_h_set_dabr)
1599 std r4,VCPU_DABR(r3)
1600 /* Work around P7 bug where DABR can get corrupted on mtspr */
1601 1: mtspr SPRN_DABR,r4
1609 _GLOBAL(kvmppc_h_cede)
1611 std r11,VCPU_MSR(r3)
1613 stb r0,VCPU_CEDED(r3)
1614 sync /* order setting ceded vs. testing prodded */
1615 lbz r5,VCPU_PRODDED(r3)
1617 bne kvm_cede_prodded
1618 li r0,0 /* set trap to 0 to say hcall is handled */
1619 stw r0,VCPU_TRAP(r3)
1621 std r0,VCPU_GPR(R3)(r3)
1623 b kvm_cede_exit /* just send it up to host on 970 */
1624 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1627 * Set our bit in the bitmask of napping threads unless all the
1628 * other threads are already napping, in which case we send this
1631 ld r5,HSTATE_KVM_VCORE(r13)
1632 lwz r6,VCPU_PTID(r3)
1633 lwz r8,VCORE_ENTRY_EXIT(r5)
1637 addi r6,r5,VCORE_NAPPING_THREADS
1645 /* order napping_threads update vs testing entry_exit_count */
1648 stb r0,HSTATE_NAPPING(r13)
1650 lwz r7,VCORE_ENTRY_EXIT(r5)
1652 bge 33f /* another thread already exiting */
1655 * Although not specifically required by the architecture, POWER7
1656 * preserves the following registers in nap mode, even if an SMT mode
1657 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1658 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1660 /* Save non-volatile GPRs */
1661 std r14, VCPU_GPR(R14)(r3)
1662 std r15, VCPU_GPR(R15)(r3)
1663 std r16, VCPU_GPR(R16)(r3)
1664 std r17, VCPU_GPR(R17)(r3)
1665 std r18, VCPU_GPR(R18)(r3)
1666 std r19, VCPU_GPR(R19)(r3)
1667 std r20, VCPU_GPR(R20)(r3)
1668 std r21, VCPU_GPR(R21)(r3)
1669 std r22, VCPU_GPR(R22)(r3)
1670 std r23, VCPU_GPR(R23)(r3)
1671 std r24, VCPU_GPR(R24)(r3)
1672 std r25, VCPU_GPR(R25)(r3)
1673 std r26, VCPU_GPR(R26)(r3)
1674 std r27, VCPU_GPR(R27)(r3)
1675 std r28, VCPU_GPR(R28)(r3)
1676 std r29, VCPU_GPR(R29)(r3)
1677 std r30, VCPU_GPR(R30)(r3)
1678 std r31, VCPU_GPR(R31)(r3)
1684 * Take a nap until a decrementer or external interrupt occurs,
1685 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1688 stb r0,HSTATE_HWTHREAD_REQ(r13)
1690 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1694 std r0, HSTATE_SCRATCH0(r13)
1696 ld r0, HSTATE_SCRATCH0(r13)
1703 /* get vcpu pointer */
1704 ld r4, HSTATE_KVM_VCPU(r13)
1706 /* Woken by external or decrementer interrupt */
1707 ld r1, HSTATE_HOST_R1(r13)
1709 /* load up FP state */
1713 ld r14, VCPU_GPR(R14)(r4)
1714 ld r15, VCPU_GPR(R15)(r4)
1715 ld r16, VCPU_GPR(R16)(r4)
1716 ld r17, VCPU_GPR(R17)(r4)
1717 ld r18, VCPU_GPR(R18)(r4)
1718 ld r19, VCPU_GPR(R19)(r4)
1719 ld r20, VCPU_GPR(R20)(r4)
1720 ld r21, VCPU_GPR(R21)(r4)
1721 ld r22, VCPU_GPR(R22)(r4)
1722 ld r23, VCPU_GPR(R23)(r4)
1723 ld r24, VCPU_GPR(R24)(r4)
1724 ld r25, VCPU_GPR(R25)(r4)
1725 ld r26, VCPU_GPR(R26)(r4)
1726 ld r27, VCPU_GPR(R27)(r4)
1727 ld r28, VCPU_GPR(R28)(r4)
1728 ld r29, VCPU_GPR(R29)(r4)
1729 ld r30, VCPU_GPR(R30)(r4)
1730 ld r31, VCPU_GPR(R31)(r4)
1732 /* clear our bit in vcore->napping_threads */
1733 33: ld r5,HSTATE_KVM_VCORE(r13)
1734 lwz r3,VCPU_PTID(r4)
1737 addi r6,r5,VCORE_NAPPING_THREADS
1743 stb r0,HSTATE_NAPPING(r13)
1745 /* Check the wake reason in SRR1 to see why we got here */
1747 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1748 cmpwi r3, 4 /* was it an external interrupt? */
1749 li r12, BOOK3S_INTERRUPT_EXTERNAL
1752 ld r11, VCPU_MSR(r9)
1753 beq do_ext_interrupt /* if so */
1755 /* see if any other thread is already exiting */
1756 lwz r0,VCORE_ENTRY_EXIT(r5)
1758 blt kvmppc_cede_reentry /* if not go back to guest */
1760 /* some threads are exiting, so go to the guest exit path */
1761 b hcall_real_fallback
1763 /* cede when already previously prodded case */
1766 stb r0,VCPU_PRODDED(r3)
1767 sync /* order testing prodded vs. clearing ceded */
1768 stb r0,VCPU_CEDED(r3)
1772 /* we've ceded but we want to give control to the host */
1774 b hcall_real_fallback
1776 /* Try to handle a machine check in real mode */
1777 machine_check_realmode:
1778 mr r3, r9 /* get vcpu pointer */
1779 bl .kvmppc_realmode_machine_check
1781 cmpdi r3, 0 /* continue exiting from guest? */
1782 ld r9, HSTATE_KVM_VCPU(r13)
1783 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1785 /* If not, deliver a machine check. SRR0/1 are already set */
1786 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
1787 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1789 b fast_interrupt_c_return
1792 * Determine what sort of external interrupt is pending (if any).
1794 * 0 if no interrupt is pending
1795 * 1 if an interrupt is pending that needs to be handled by the host
1796 * -1 if there was a guest wakeup IPI (which has now been cleared)
1799 /* see if a host IPI is pending */
1801 lbz r0, HSTATE_HOST_IPI(r13)
1805 /* Now read the interrupt from the ICP */
1806 ld r6, HSTATE_XICS_PHYS(r13)
1811 rlwinm. r3, r0, 0, 0xffffff
1813 beq 1f /* if nothing pending in the ICP */
1815 /* We found something in the ICP...
1817 * If it's not an IPI, stash it in the PACA and return to
1818 * the host, we don't (yet) handle directing real external
1819 * interrupts directly to the guest
1821 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
1825 /* It's an IPI, clear the MFRR and EOI it */
1828 stbcix r3, r6, r8 /* clear the IPI */
1829 stwcix r0, r6, r7 /* EOI it */
1832 /* We need to re-check host IPI now in case it got set in the
1833 * meantime. If it's clear, we bounce the interrupt to the
1836 lbz r0, HSTATE_HOST_IPI(r13)
1840 /* OK, it's an IPI for us */
1844 42: /* It's not an IPI and it's for the host, stash it in the PACA
1845 * before exit, it will be picked up by the host ICP driver
1847 stw r0, HSTATE_SAVED_XIRR(r13)
1850 43: /* We raced with the host, we need to resend that IPI, bummer */
1852 stbcix r0, r6, r8 /* set the IPI */
1857 * Save away FP, VMX and VSX registers.
1860 _GLOBAL(kvmppc_save_fp)
1863 #ifdef CONFIG_ALTIVEC
1865 oris r8,r8,MSR_VEC@h
1866 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1870 oris r8,r8,MSR_VSX@h
1871 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1879 li r6,reg*16+VCPU_VSRS
1887 stfd reg,reg*8+VCPU_FPRS(r3)
1891 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1894 stfd fr0,VCPU_FPSCR(r3)
1896 #ifdef CONFIG_ALTIVEC
1900 li r6,reg*16+VCPU_VRS
1907 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1909 mfspr r6,SPRN_VRSAVE
1910 stw r6,VCPU_VRSAVE(r3)
1916 * Load up FP, VMX and VSX registers
1919 .globl kvmppc_load_fp
1923 #ifdef CONFIG_ALTIVEC
1925 oris r8,r8,MSR_VEC@h
1926 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1930 oris r8,r8,MSR_VSX@h
1931 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1935 lfd fr0,VCPU_FPSCR(r4)
1941 li r7,reg*16+VCPU_VSRS
1949 lfd reg,reg*8+VCPU_FPRS(r4)
1953 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1956 #ifdef CONFIG_ALTIVEC
1963 li r7,reg*16+VCPU_VRS
1967 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1969 lwz r7,VCPU_VRSAVE(r4)
1970 mtspr SPRN_VRSAVE,r7
1974 * We come here if we get any exception or interrupt while we are
1975 * executing host real mode code while in guest MMU context.
1976 * For now just spin, but we should do something better.
1978 kvmppc_bad_host_intr: