1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
6 * Derived from book3s_rmhandlers.S and other files, which are:
8 * Copyright SUSE Linux Products GmbH 2009
10 * Authors: Alexander Graf <agraf@suse.de>
13 #include <asm/ppc_asm.h>
14 #include <asm/code-patching-asm.h>
15 #include <asm/kvm_asm.h>
19 #include <asm/ptrace.h>
20 #include <asm/hvcall.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/exception-64s.h>
23 #include <asm/kvm_book3s_asm.h>
24 #include <asm/book3s/64/mmu-hash.h>
25 #include <asm/export.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-compat.h>
30 #include <asm/feature-fixups.h>
31 #include <asm/cpuidle.h>
33 /* Values in HSTATE_NAPPING(r13) */
34 #define NAPPING_CEDE 1
35 #define NAPPING_NOVCPU 2
36 #define NAPPING_UNSPLIT 3
38 /* Stack frame offsets for kvmppc_hv_entry */
40 #define STACK_SLOT_TRAP (SFS-4)
41 #define STACK_SLOT_TID (SFS-16)
42 #define STACK_SLOT_PSSCR (SFS-24)
43 #define STACK_SLOT_PID (SFS-32)
44 #define STACK_SLOT_IAMR (SFS-40)
45 #define STACK_SLOT_CIABR (SFS-48)
46 #define STACK_SLOT_DAWR0 (SFS-56)
47 #define STACK_SLOT_DAWRX0 (SFS-64)
48 #define STACK_SLOT_HFSCR (SFS-72)
49 #define STACK_SLOT_AMR (SFS-80)
50 #define STACK_SLOT_UAMOR (SFS-88)
51 #define STACK_SLOT_FSCR (SFS-96)
54 * Call kvmppc_hv_entry in real mode.
55 * Must be called with interrupts hard-disabled.
59 * LR = return address to continue at after eventually re-enabling MMU
61 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
63 std r0, PPC_LR_STKOFF(r1)
66 std r10, HSTATE_HOST_MSR(r13)
67 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
72 mtmsrd r0,1 /* clear RI in MSR */
78 ld r4, HSTATE_KVM_VCPU(r13)
81 /* Back from guest - restore host state and return to caller */
84 /* Restore host DABR and DABRX */
85 ld r5,HSTATE_DABR(r13)
89 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
92 ld r3,PACA_SPRG_VDSO(r13)
93 mtspr SPRN_SPRG_VDSO_WRITE,r3
95 /* Reload the host's PMU registers */
96 bl kvmhv_load_host_pmu
99 * Reload DEC. HDEC interrupts were disabled when
100 * we reloaded the host's LPCR value.
102 ld r3, HSTATE_DECEXP(r13)
107 /* hwthread_req may have got set by cede or no vcpu, so clear it */
109 stb r0, HSTATE_HWTHREAD_REQ(r13)
112 * For external interrupts we need to call the Linux
113 * handler to process the interrupt. We do that by jumping
114 * to absolute address 0x500 for external interrupts.
115 * The [h]rfid at the end of the handler will return to
116 * the book3s_hv_interrupts.S code. For other interrupts
117 * we do the rfid to get back to the book3s_hv_interrupts.S
120 ld r8, 112+PPC_LR_STKOFF(r1)
122 ld r7, HSTATE_HOST_MSR(r13)
124 /* Return the trap number on this thread as the return value */
127 /* RFI into the highmem handler */
131 mtmsrd r6, 1 /* Clear RI in MSR */
136 kvmppc_primary_no_guest:
137 /* We handle this much like a ceded vcpu */
138 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
139 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
140 /* HDEC value came from DEC in the first place, it will fit */
144 * Make sure the primary has finished the MMU switch.
145 * We should never get here on a secondary thread, but
146 * check it for robustness' sake.
148 ld r5, HSTATE_KVM_VCORE(r13)
149 65: lbz r0, VCORE_IN_GUEST(r5)
156 /* set our bit in napping_threads */
157 ld r5, HSTATE_KVM_VCORE(r13)
158 lbz r7, HSTATE_PTID(r13)
161 addi r6, r5, VCORE_NAPPING_THREADS
166 /* order napping_threads update vs testing entry_exit_map */
169 lwz r7, VCORE_ENTRY_EXIT(r5)
171 bge kvm_novcpu_exit /* another thread already exiting */
172 li r3, NAPPING_NOVCPU
173 stb r3, HSTATE_NAPPING(r13)
175 li r3, 0 /* Don't wake on privileged (OS) doorbell */
180 * Entered from kvm_start_guest if kvm_hstate.napping is set
186 ld r1, HSTATE_HOST_R1(r13)
187 ld r5, HSTATE_KVM_VCORE(r13)
189 stb r0, HSTATE_NAPPING(r13)
191 /* check the wake reason */
192 bl kvmppc_check_wake_reason
195 * Restore volatile registers since we could have called
196 * a C routine in kvmppc_check_wake_reason.
199 ld r5, HSTATE_KVM_VCORE(r13)
201 /* see if any other thread is already exiting */
202 lwz r0, VCORE_ENTRY_EXIT(r5)
206 /* clear our bit in napping_threads */
207 lbz r7, HSTATE_PTID(r13)
210 addi r6, r5, VCORE_NAPPING_THREADS
216 /* See if the wake reason means we need to exit */
220 /* See if our timeslice has expired (HDEC is negative) */
223 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
227 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
228 ld r4, HSTATE_KVM_VCPU(r13)
230 beq kvmppc_primary_no_guest
232 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
233 addi r3, r4, VCPU_TB_RMENTRY
234 bl kvmhv_start_timing
239 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
240 ld r4, HSTATE_KVM_VCPU(r13)
243 addi r3, r4, VCPU_TB_RMEXIT
244 bl kvmhv_accumulate_time
247 stw r12, STACK_SLOT_TRAP(r1)
248 bl kvmhv_commence_exit
250 b kvmhv_switch_to_host
253 * We come in here when wakened from Linux offline idle code.
255 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
257 _GLOBAL(idle_kvm_start_guest)
258 ld r4,PACAEMERGSP(r13)
264 subi r1,r4,STACK_FRAME_OVERHEAD
268 * Could avoid this and pass it through in r3. For now,
269 * code expects it to be in SRR1.
274 stb r0,PACA_FTRACE_ENABLED(r13)
276 li r0,KVM_HWTHREAD_IN_KVM
277 stb r0,HSTATE_HWTHREAD_STATE(r13)
279 /* kvm cede / napping does not come through here */
280 lbz r0,HSTATE_NAPPING(r13)
287 stb r0, HSTATE_NAPPING(r13)
292 * We weren't napping due to cede, so this must be a secondary
293 * thread being woken up to run a guest, or being woken up due
294 * to a stray IPI. (Or due to some machine check or hypervisor
295 * maintenance interrupt while the core is in KVM.)
298 /* Check the wake reason in SRR1 to see why we got here */
299 bl kvmppc_check_wake_reason
301 * kvmppc_check_wake_reason could invoke a C routine, but we
302 * have no volatile registers to restore when we return.
308 /* get vcore pointer, NULL if we have nothing to run */
309 ld r5,HSTATE_KVM_VCORE(r13)
311 /* if we have no vcore to run, go back to sleep */
314 kvm_secondary_got_guest:
316 /* Set HSTATE_DSCR(r13) to something sensible */
317 ld r6, PACA_DSCR_DEFAULT(r13)
318 std r6, HSTATE_DSCR(r13)
320 /* On thread 0 of a subcore, set HDEC to max */
321 lbz r4, HSTATE_PTID(r13)
324 lis r6,0x7fff /* MAX_INT@h */
326 /* and set per-LPAR registers, if doing dynamic micro-threading */
327 ld r6, HSTATE_SPLIT_MODE(r13)
330 ld r0, KVM_SPLIT_RPR(r6)
332 ld r0, KVM_SPLIT_PMMAR(r6)
334 ld r0, KVM_SPLIT_LDBAR(r6)
338 /* Order load of vcpu after load of vcore */
340 ld r4, HSTATE_KVM_VCPU(r13)
343 /* Back from the guest, go back to nap */
344 /* Clear our vcpu and vcore pointers so we don't come back in early */
346 std r0, HSTATE_KVM_VCPU(r13)
348 * Once we clear HSTATE_KVM_VCORE(r13), the code in
349 * kvmppc_run_core() is going to assume that all our vcpu
350 * state is visible in memory. This lwsync makes sure
354 std r0, HSTATE_KVM_VCORE(r13)
357 * All secondaries exiting guest will fall through this path.
358 * Before proceeding, just check for HMI interrupt and
359 * invoke opal hmi handler. By now we are sure that the
360 * primary thread on this core/subcore has already made partition
361 * switch/TB resync and we are good to call opal hmi handler.
363 cmpwi r12, BOOK3S_INTERRUPT_HMI
366 li r3,0 /* NULL argument */
367 bl hmi_exception_realmode
369 * At this point we have finished executing in the guest.
370 * We need to wait for hwthread_req to become zero, since
371 * we may not turn on the MMU while hwthread_req is non-zero.
372 * While waiting we also need to check if we get given a vcpu to run.
375 lbz r3, HSTATE_HWTHREAD_REQ(r13)
379 li r0, KVM_HWTHREAD_IN_KERNEL
380 stb r0, HSTATE_HWTHREAD_STATE(r13)
381 /* need to recheck hwthread_req after a barrier, to avoid race */
383 lbz r3, HSTATE_HWTHREAD_REQ(r13)
388 * Jump to idle_return_gpr_loss, which returns to the
389 * idle_kvm_start_guest caller.
393 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
395 /* set up r3 for return */
398 addi r1, r1, STACK_FRAME_OVERHEAD
408 ld r5, HSTATE_KVM_VCORE(r13)
411 ld r3, HSTATE_SPLIT_MODE(r13)
414 lbz r0, KVM_SPLIT_DO_NAP(r3)
420 b kvm_secondary_got_guest
422 54: li r0, KVM_HWTHREAD_IN_KVM
423 stb r0, HSTATE_HWTHREAD_STATE(r13)
427 * Here the primary thread is trying to return the core to
428 * whole-core mode, so we need to nap.
432 * When secondaries are napping in kvm_unsplit_nap() with
433 * hwthread_req = 1, HMI goes ignored even though subcores are
434 * already exited the guest. Hence HMI keeps waking up secondaries
435 * from nap in a loop and secondaries always go back to nap since
436 * no vcore is assigned to them. This makes impossible for primary
437 * thread to get hold of secondary threads resulting into a soft
438 * lockup in KVM path.
440 * Let us check if HMI is pending and handle it before we go to nap.
442 cmpwi r12, BOOK3S_INTERRUPT_HMI
444 li r3, 0 /* NULL argument */
445 bl hmi_exception_realmode
448 * Ensure that secondary doesn't nap when it has
449 * its vcore pointer set.
451 sync /* matches smp_mb() before setting split_info.do_nap */
452 ld r0, HSTATE_KVM_VCORE(r13)
455 /* clear any pending message */
457 lis r6, (PPC_DBELL_SERVER << (63-36))@h
459 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
460 /* Set kvm_split_mode.napped[tid] = 1 */
461 ld r3, HSTATE_SPLIT_MODE(r13)
463 lhz r4, PACAPACAINDEX(r13)
464 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
465 addi r4, r4, KVM_SPLIT_NAPPED
467 /* Check the do_nap flag again after setting napped[] */
469 lbz r0, KVM_SPLIT_DO_NAP(r3)
472 li r3, NAPPING_UNSPLIT
473 stb r3, HSTATE_NAPPING(r13)
474 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
476 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
483 /******************************************************************************
487 *****************************************************************************/
489 .global kvmppc_hv_entry
494 * R4 = vcpu pointer (or NULL)
499 * all other volatile GPRS = free
500 * Does not preserve non-volatile GPRs or CR fields
503 std r0, PPC_LR_STKOFF(r1)
506 /* Save R1 in the PACA */
507 std r1, HSTATE_HOST_R1(r13)
509 li r6, KVM_GUEST_MODE_HOST_HV
510 stb r6, HSTATE_IN_GUEST(r13)
512 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
513 /* Store initial timestamp */
516 addi r3, r4, VCPU_TB_RMENTRY
517 bl kvmhv_start_timing
521 ld r5, HSTATE_KVM_VCORE(r13)
522 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
525 * POWER7/POWER8 host -> guest partition switch code.
526 * We don't have to lock against concurrent tlbies,
527 * but we do have to coordinate across hardware threads.
529 /* Set bit in entry map iff exit map is zero. */
531 lbz r6, HSTATE_PTID(r13)
533 addi r8, r5, VCORE_ENTRY_EXIT
535 cmpwi r3, 0x100 /* any threads starting to exit? */
536 bge secondary_too_late /* if so we're too late to the party */
541 /* Primary thread switches to guest partition. */
547 li r0,LPID_RSVD /* switch to reserved LPID */
550 mtspr SPRN_SDR1,r6 /* switch to partition page table */
554 /* See if we need to flush the TLB. */
555 mr r3, r9 /* kvm pointer */
556 lhz r4, PACAPACAINDEX(r13) /* physical cpu number */
557 li r5, 0 /* nested vcpu pointer */
558 bl kvmppc_check_need_tlb_flush
560 ld r5, HSTATE_KVM_VCORE(r13)
562 /* Add timebase offset onto timebase */
563 22: ld r8,VCORE_TB_OFFSET(r5)
566 std r8, VCORE_TB_OFFSET_APPL(r5)
567 mftb r6 /* current host timebase */
569 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
570 mftb r7 /* check if lower 24 bits overflowed */
575 addis r8,r8,0x100 /* if so, increment upper 40 bits */
578 /* Load guest PCR value to select appropriate compat mode */
579 37: ld r7, VCORE_PCR(r5)
580 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
588 /* DPDES and VTB are shared between threads */
589 ld r8, VCORE_DPDES(r5)
593 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
595 /* Mark the subcore state as inside guest */
596 bl kvmppc_subcore_enter_guest
598 ld r5, HSTATE_KVM_VCORE(r13)
599 ld r4, HSTATE_KVM_VCPU(r13)
601 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
603 /* Do we have a guest vcpu to run? */
605 beq kvmppc_primary_no_guest
607 /* Increment yield count if they have a VPA */
611 li r6, LPPACA_YIELDCOUNT
616 stb r6, VCPU_VPA_DIRTY(r4)
619 /* Save purr/spurr */
622 std r5,HSTATE_PURR(r13)
623 std r6,HSTATE_SPURR(r13)
629 /* Save host values of some registers */
633 mfspr r7, SPRN_DAWRX0
635 std r5, STACK_SLOT_CIABR(r1)
636 std r6, STACK_SLOT_DAWR0(r1)
637 std r7, STACK_SLOT_DAWRX0(r1)
638 std r8, STACK_SLOT_IAMR(r1)
640 std r5, STACK_SLOT_FSCR(r1)
641 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
644 std r5, STACK_SLOT_AMR(r1)
646 std r6, STACK_SLOT_UAMOR(r1)
649 /* Set partition DABR */
650 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
651 lwz r5,VCPU_DABRX(r4)
656 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
658 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
661 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
663 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
667 li r5, 0 /* don't preserve non-vol regs */
668 bl kvmppc_restore_tm_hv
670 ld r4, HSTATE_KVM_VCPU(r13)
674 /* Load guest PMU registers; r4 = vcpu pointer here */
676 bl kvmhv_load_guest_pmu
678 /* Load up FP, VMX and VSX registers */
679 ld r4, HSTATE_KVM_VCPU(r13)
682 ld r14, VCPU_GPR(R14)(r4)
683 ld r15, VCPU_GPR(R15)(r4)
684 ld r16, VCPU_GPR(R16)(r4)
685 ld r17, VCPU_GPR(R17)(r4)
686 ld r18, VCPU_GPR(R18)(r4)
687 ld r19, VCPU_GPR(R19)(r4)
688 ld r20, VCPU_GPR(R20)(r4)
689 ld r21, VCPU_GPR(R21)(r4)
690 ld r22, VCPU_GPR(R22)(r4)
691 ld r23, VCPU_GPR(R23)(r4)
692 ld r24, VCPU_GPR(R24)(r4)
693 ld r25, VCPU_GPR(R25)(r4)
694 ld r26, VCPU_GPR(R26)(r4)
695 ld r27, VCPU_GPR(R27)(r4)
696 ld r28, VCPU_GPR(R28)(r4)
697 ld r29, VCPU_GPR(R29)(r4)
698 ld r30, VCPU_GPR(R30)(r4)
699 ld r31, VCPU_GPR(R31)(r4)
701 /* Switch DSCR to guest value */
706 /* Skip next section on POWER7 */
708 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
709 /* Load up POWER8-specific registers */
711 lwz r6, VCPU_PSPB(r4)
717 * Handle broken DAWR case by not writing it. This means we
718 * can still store the DAWR register for migration.
720 LOAD_REG_ADDR(r5, dawr_force_enable)
724 ld r5, VCPU_DAWR0(r4)
725 ld r6, VCPU_DAWRX0(r4)
727 mtspr SPRN_DAWRX0, r6
729 ld r7, VCPU_CIABR(r4)
734 ld r8, VCPU_EBBHR(r4)
737 ld r5, VCPU_EBBRR(r4)
738 ld r6, VCPU_BESCR(r4)
739 lwz r7, VCPU_GUEST_PID(r4)
745 /* POWER8-only registers */
746 ld r5, VCPU_TCSCR(r4)
748 ld r7, VCPU_CSIGR(r4)
757 ld r5, VCPU_SPRG0(r4)
758 ld r6, VCPU_SPRG1(r4)
759 ld r7, VCPU_SPRG2(r4)
760 ld r8, VCPU_SPRG3(r4)
766 /* Load up DAR and DSISR */
768 lwz r6, VCPU_DSISR(r4)
772 /* Restore AMR and UAMOR, set AMOR to all 1s */
780 /* Restore state of CTRL run bit; assume 1 on entry */
788 /* Secondary threads wait for primary to have done partition switch */
789 ld r5, HSTATE_KVM_VCORE(r13)
790 lbz r6, HSTATE_PTID(r13)
793 lbz r0, VCORE_IN_GUEST(r5)
797 20: lwz r3, VCORE_ENTRY_EXIT(r5)
800 lbz r0, VCORE_IN_GUEST(r5)
811 * Set the decrementer to the guest decrementer.
813 ld r8,VCPU_DEC_EXPIRES(r4)
814 /* r8 is a host timebase value here, convert to guest TB */
815 ld r5,HSTATE_KVM_VCORE(r13)
816 ld r6,VCORE_TB_OFFSET_APPL(r5)
822 /* Check if HDEC expires soon */
825 cmpdi r3, 512 /* 1 microsecond */
828 /* Clear out and reload the SLB */
834 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
835 lwz r5,VCPU_SLB_MAX(r4)
840 1: ld r8,VCPU_SLB_E(r6)
843 addi r6,r6,VCPU_SLB_SIZE
847 deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
848 /* Check if we can deliver an external or decrementer interrupt now */
849 ld r0, VCPU_PENDING_EXC(r4)
853 bl kvmppc_guest_entry_inject_int
854 ld r4, HSTATE_KVM_VCPU(r13)
863 /* r11 = vcpu->arch.msr & ~MSR_HV */
864 rldicl r11, r11, 63 - MSR_HV_LG, 1
865 rotldi r11, r11, 1 + MSR_HV_LG
876 * R10: value for HSRR0
877 * R11: value for HSRR1
882 stb r0,VCPU_CEDED(r4) /* cancel cede */
886 /* Activate guest mode, so faults get handled by KVM */
887 li r9, KVM_GUEST_MODE_GUEST_HV
888 stb r9, HSTATE_IN_GUEST(r13)
890 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
891 /* Accumulate timing */
892 addi r3, r4, VCPU_TB_GUEST
893 bl kvmhv_accumulate_time
901 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
904 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
909 ld r1, VCPU_GPR(R1)(r4)
910 ld r5, VCPU_GPR(R5)(r4)
911 ld r8, VCPU_GPR(R8)(r4)
912 ld r9, VCPU_GPR(R9)(r4)
913 ld r10, VCPU_GPR(R10)(r4)
914 ld r11, VCPU_GPR(R11)(r4)
915 ld r12, VCPU_GPR(R12)(r4)
916 ld r13, VCPU_GPR(R13)(r4)
920 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
922 ld r6, VCPU_GPR(R6)(r4)
923 ld r7, VCPU_GPR(R7)(r4)
928 ld r0, VCPU_GPR(R0)(r4)
929 ld r2, VCPU_GPR(R2)(r4)
930 ld r3, VCPU_GPR(R3)(r4)
931 ld r4, VCPU_GPR(R4)(r4)
937 stw r12, STACK_SLOT_TRAP(r1)
940 stw r12, VCPU_TRAP(r4)
941 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
942 addi r3, r4, VCPU_TB_RMEXIT
943 bl kvmhv_accumulate_time
945 11: b kvmhv_switch_to_host
952 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
953 12: stw r12, VCPU_TRAP(r4)
955 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
956 addi r3, r4, VCPU_TB_RMEXIT
957 bl kvmhv_accumulate_time
961 /******************************************************************************
965 *****************************************************************************/
968 * We come here from the first-level interrupt handlers.
970 .globl kvmppc_interrupt_hv
974 * R9 = HSTATE_IN_GUEST
975 * R12 = (guest CR << 32) | interrupt vector
977 * guest R12 saved in shadow VCPU SCRATCH0
978 * guest R13 saved in SPRN_SCRATCH0
979 * guest R9 saved in HSTATE_SCRATCH2
981 /* We're now back in the host but in guest MMU context */
982 cmpwi r9,KVM_GUEST_MODE_HOST_HV
983 beq kvmppc_bad_host_intr
984 li r9, KVM_GUEST_MODE_HOST_HV
985 stb r9, HSTATE_IN_GUEST(r13)
987 ld r9, HSTATE_KVM_VCPU(r13)
991 std r0, VCPU_GPR(R0)(r9)
992 std r1, VCPU_GPR(R1)(r9)
993 std r2, VCPU_GPR(R2)(r9)
994 std r3, VCPU_GPR(R3)(r9)
995 std r4, VCPU_GPR(R4)(r9)
996 std r5, VCPU_GPR(R5)(r9)
997 std r6, VCPU_GPR(R6)(r9)
998 std r7, VCPU_GPR(R7)(r9)
999 std r8, VCPU_GPR(R8)(r9)
1000 ld r0, HSTATE_SCRATCH2(r13)
1001 std r0, VCPU_GPR(R9)(r9)
1002 std r10, VCPU_GPR(R10)(r9)
1003 std r11, VCPU_GPR(R11)(r9)
1004 ld r3, HSTATE_SCRATCH0(r13)
1005 std r3, VCPU_GPR(R12)(r9)
1006 /* CR is in the high half of r12 */
1010 ld r3, HSTATE_CFAR(r13)
1011 std r3, VCPU_CFAR(r9)
1012 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1014 ld r4, HSTATE_PPR(r13)
1015 std r4, VCPU_PPR(r9)
1016 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1018 /* Restore R1/R2 so we can handle faults */
1019 ld r1, HSTATE_HOST_R1(r13)
1022 mfspr r10, SPRN_SRR0
1023 mfspr r11, SPRN_SRR1
1024 std r10, VCPU_SRR0(r9)
1025 std r11, VCPU_SRR1(r9)
1026 /* trap is in the low half of r12, clear CR from the high half */
1028 andi. r0, r12, 2 /* need to read HSRR0/1? */
1030 mfspr r10, SPRN_HSRR0
1031 mfspr r11, SPRN_HSRR1
1033 1: std r10, VCPU_PC(r9)
1034 std r11, VCPU_MSR(r9)
1038 std r3, VCPU_GPR(R13)(r9)
1041 stw r12,VCPU_TRAP(r9)
1044 * Now that we have saved away SRR0/1 and HSRR0/1,
1045 * interrupts are recoverable in principle, so set MSR_RI.
1046 * This becomes important for relocation-on interrupts from
1047 * the guest, which we can get in radix mode on POWER9.
1052 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1053 addi r3, r9, VCPU_TB_RMINTR
1055 bl kvmhv_accumulate_time
1056 ld r5, VCPU_GPR(R5)(r9)
1057 ld r6, VCPU_GPR(R6)(r9)
1058 ld r7, VCPU_GPR(R7)(r9)
1059 ld r8, VCPU_GPR(R8)(r9)
1062 /* Save HEIR (HV emulation assist reg) in emul_inst
1063 if this is an HEI (HV emulation interrupt, e40) */
1064 li r3,KVM_INST_FETCH_FAILED
1065 stw r3,VCPU_LAST_INST(r9)
1066 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1069 11: stw r3,VCPU_HEIR(r9)
1071 /* these are volatile across C function calls */
1074 std r3, VCPU_CTR(r9)
1075 std r4, VCPU_XER(r9)
1077 /* Save more register state */
1080 std r3, VCPU_DAR(r9)
1081 stw r4, VCPU_DSISR(r9)
1083 /* If this is a page table miss then see if it's theirs or ours */
1084 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1086 std r3, VCPU_FAULT_DAR(r9)
1087 stw r4, VCPU_FAULT_DSISR(r9)
1088 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1091 /* See if this is a leftover HDEC interrupt */
1092 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1098 bge fast_guest_return
1100 /* See if this is an hcall we can handle in real mode */
1101 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1102 beq hcall_try_real_mode
1104 /* Hypervisor doorbell - exit only if host IPI flag set */
1105 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1107 lbz r0, HSTATE_HOST_IPI(r13)
1109 beq maybe_reenter_guest
1112 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1113 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1115 mfspr r3, SPRN_HFSCR
1116 std r3, VCPU_HFSCR(r9)
1119 /* External interrupt ? */
1120 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1121 beq kvmppc_guest_external
1122 /* See if it is a machine check */
1123 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1124 beq machine_check_realmode
1125 /* Or a hypervisor maintenance interrupt */
1126 cmpwi r12, BOOK3S_INTERRUPT_HMI
1129 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1131 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1132 addi r3, r9, VCPU_TB_RMEXIT
1134 bl kvmhv_accumulate_time
1138 * Possibly flush the link stack here, before we do a blr in
1139 * kvmhv_switch_to_host.
1142 patch_site 1b patch__call_kvm_flush_link_stack
1144 /* For hash guest, read the guest SLB and save it away */
1146 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1151 andis. r0,r8,SLB_ESID_V@h
1153 add r8,r8,r6 /* put index in */
1155 std r8,VCPU_SLB_E(r7)
1156 std r3,VCPU_SLB_V(r7)
1157 addi r7,r7,VCPU_SLB_SIZE
1161 /* Finally clear out the SLB */
1166 stw r5,VCPU_SLB_MAX(r9)
1168 /* load host SLB entries */
1169 ld r8,PACA_SLBSHADOWPTR(r13)
1171 .rept SLB_NUM_BOLTED
1172 li r3, SLBSHADOW_SAVEAREA
1176 andis. r7,r5,SLB_ESID_V@h
1183 stw r12, STACK_SLOT_TRAP(r1)
1186 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1187 ld r3, HSTATE_KVM_VCORE(r13)
1192 /* r5 is a guest timebase value here, convert to host TB */
1193 ld r4,VCORE_TB_OFFSET_APPL(r3)
1195 std r5,VCPU_DEC_EXPIRES(r9)
1197 /* Increment exit count, poke other threads to exit */
1199 bl kvmhv_commence_exit
1201 ld r9, HSTATE_KVM_VCPU(r13)
1203 /* Stop others sending VCPU interrupts to this physical CPU */
1205 stw r0, VCPU_CPU(r9)
1206 stw r0, VCPU_THREAD_CPU(r9)
1208 /* Save guest CTRL register, set runlatch to 1 */
1210 stw r6,VCPU_CTRL(r9)
1217 * Save the guest PURR/SPURR
1222 ld r8,VCPU_SPURR(r9)
1223 std r5,VCPU_PURR(r9)
1224 std r6,VCPU_SPURR(r9)
1229 * Restore host PURR/SPURR and add guest times
1230 * so that the time in the guest gets accounted.
1232 ld r3,HSTATE_PURR(r13)
1233 ld r4,HSTATE_SPURR(r13)
1241 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1242 /* Save POWER8-specific registers */
1246 std r5, VCPU_IAMR(r9)
1247 stw r6, VCPU_PSPB(r9)
1248 std r7, VCPU_FSCR(r9)
1252 std r7, VCPU_TAR(r9)
1253 mfspr r8, SPRN_EBBHR
1254 std r8, VCPU_EBBHR(r9)
1255 mfspr r5, SPRN_EBBRR
1256 mfspr r6, SPRN_BESCR
1259 std r5, VCPU_EBBRR(r9)
1260 std r6, VCPU_BESCR(r9)
1261 stw r7, VCPU_GUEST_PID(r9)
1262 std r8, VCPU_WORT(r9)
1263 mfspr r5, SPRN_TCSCR
1265 mfspr r7, SPRN_CSIGR
1267 std r5, VCPU_TCSCR(r9)
1268 std r6, VCPU_ACOP(r9)
1269 std r7, VCPU_CSIGR(r9)
1270 std r8, VCPU_TACR(r9)
1272 ld r5, STACK_SLOT_FSCR(r1)
1274 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1276 * Restore various registers to 0, where non-zero values
1277 * set by the guest could disrupt the host.
1282 mtspr SPRN_TCSCR, r0
1283 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1286 mtspr SPRN_MMCRS, r0
1288 /* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
1289 ld r8, STACK_SLOT_IAMR(r1)
1292 8: /* Power7 jumps back in here */
1296 std r6,VCPU_UAMOR(r9)
1297 ld r5,STACK_SLOT_AMR(r1)
1298 ld r6,STACK_SLOT_UAMOR(r1)
1300 mtspr SPRN_UAMOR, r6
1302 /* Switch DSCR back to host value */
1304 ld r7, HSTATE_DSCR(r13)
1305 std r8, VCPU_DSCR(r9)
1308 /* Save non-volatile GPRs */
1309 std r14, VCPU_GPR(R14)(r9)
1310 std r15, VCPU_GPR(R15)(r9)
1311 std r16, VCPU_GPR(R16)(r9)
1312 std r17, VCPU_GPR(R17)(r9)
1313 std r18, VCPU_GPR(R18)(r9)
1314 std r19, VCPU_GPR(R19)(r9)
1315 std r20, VCPU_GPR(R20)(r9)
1316 std r21, VCPU_GPR(R21)(r9)
1317 std r22, VCPU_GPR(R22)(r9)
1318 std r23, VCPU_GPR(R23)(r9)
1319 std r24, VCPU_GPR(R24)(r9)
1320 std r25, VCPU_GPR(R25)(r9)
1321 std r26, VCPU_GPR(R26)(r9)
1322 std r27, VCPU_GPR(R27)(r9)
1323 std r28, VCPU_GPR(R28)(r9)
1324 std r29, VCPU_GPR(R29)(r9)
1325 std r30, VCPU_GPR(R30)(r9)
1326 std r31, VCPU_GPR(R31)(r9)
1329 mfspr r3, SPRN_SPRG0
1330 mfspr r4, SPRN_SPRG1
1331 mfspr r5, SPRN_SPRG2
1332 mfspr r6, SPRN_SPRG3
1333 std r3, VCPU_SPRG0(r9)
1334 std r4, VCPU_SPRG1(r9)
1335 std r5, VCPU_SPRG2(r9)
1336 std r6, VCPU_SPRG3(r9)
1342 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1345 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1347 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
1351 li r5, 0 /* don't preserve non-vol regs */
1352 bl kvmppc_save_tm_hv
1354 ld r9, HSTATE_KVM_VCPU(r13)
1358 /* Increment yield count if they have a VPA */
1359 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1362 li r4, LPPACA_YIELDCOUNT
1367 stb r3, VCPU_VPA_DIRTY(r9)
1369 /* Save PMU registers if requested */
1370 /* r8 and cr0.eq are live here */
1373 beq 21f /* if no VPA, save PMU stuff anyway */
1374 lbz r4, LPPACA_PMCINUSE(r8)
1375 21: bl kvmhv_save_guest_pmu
1376 ld r9, HSTATE_KVM_VCPU(r13)
1378 /* Restore host values of some registers */
1380 ld r5, STACK_SLOT_CIABR(r1)
1381 ld r6, STACK_SLOT_DAWR0(r1)
1382 ld r7, STACK_SLOT_DAWRX0(r1)
1383 mtspr SPRN_CIABR, r5
1385 * If the DAWR doesn't work, it's ok to write these here as
1386 * this value should always be zero
1388 mtspr SPRN_DAWR0, r6
1389 mtspr SPRN_DAWRX0, r7
1390 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1393 * POWER7/POWER8 guest -> host partition switch code.
1394 * We don't have to lock against tlbies but we do
1395 * have to coordinate the hardware threads.
1396 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1398 kvmhv_switch_to_host:
1399 /* Secondary threads wait for primary to do partition switch */
1400 ld r5,HSTATE_KVM_VCORE(r13)
1401 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1402 lbz r3,HSTATE_PTID(r13)
1406 13: lbz r3,VCORE_IN_GUEST(r5)
1412 /* Primary thread waits for all the secondaries to exit guest */
1413 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1414 rlwinm r0,r3,32-8,0xff
1420 /* Did we actually switch to the guest at all? */
1421 lbz r6, VCORE_IN_GUEST(r5)
1425 /* Primary thread switches back to host partition */
1426 lwz r7,KVM_HOST_LPID(r4)
1427 ld r6,KVM_HOST_SDR1(r4)
1428 li r8,LPID_RSVD /* switch to reserved LPID */
1431 mtspr SPRN_SDR1,r6 /* switch to host page table */
1436 /* DPDES and VTB are shared between threads */
1437 mfspr r7, SPRN_DPDES
1439 std r7, VCORE_DPDES(r5)
1440 std r8, VCORE_VTB(r5)
1441 /* clear DPDES so we don't get guest doorbells in the host */
1443 mtspr SPRN_DPDES, r8
1444 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1446 /* Subtract timebase offset from timebase */
1447 ld r8, VCORE_TB_OFFSET_APPL(r5)
1451 std r0, VCORE_TB_OFFSET_APPL(r5)
1452 mftb r6 /* current guest timebase */
1454 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1455 mftb r7 /* check if lower 24 bits overflowed */
1460 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1465 * If this is an HMI, we called kvmppc_realmode_hmi_handler
1466 * above, which may or may not have already called
1467 * kvmppc_subcore_exit_guest. Fortunately, all that
1468 * kvmppc_subcore_exit_guest does is clear a flag, so calling
1469 * it again here is benign even if kvmppc_realmode_hmi_handler
1470 * has already called it.
1472 bl kvmppc_subcore_exit_guest
1474 30: ld r5,HSTATE_KVM_VCORE(r13)
1475 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1478 ld r0, VCORE_PCR(r5)
1479 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
1484 /* Signal secondary CPUs to continue */
1486 stb r0,VCORE_IN_GUEST(r5)
1487 19: lis r8,0x7fff /* MAX_INT@h */
1490 16: ld r8,KVM_HOST_LPCR(r4)
1494 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1495 /* Finish timing, if we have a vcpu */
1496 ld r4, HSTATE_KVM_VCPU(r13)
1500 bl kvmhv_accumulate_time
1503 /* Unset guest mode */
1504 li r0, KVM_GUEST_MODE_NONE
1505 stb r0, HSTATE_IN_GUEST(r13)
1507 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1508 ld r0, SFS+PPC_LR_STKOFF(r1)
1514 .global kvm_flush_link_stack
1515 kvm_flush_link_stack:
1516 /* Save LR into r0 */
1519 /* Flush the link stack. On Power8 it's up to 32 entries in size. */
1524 /* And on Power9 it's up to 64. */
1529 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1535 kvmppc_guest_external:
1536 /* External interrupt, first check for host_ipi. If this is
1537 * set, we know the host wants us out so let's do it now
1542 * Restore the active volatile registers after returning from
1545 ld r9, HSTATE_KVM_VCPU(r13)
1546 li r12, BOOK3S_INTERRUPT_EXTERNAL
1549 * kvmppc_read_intr return codes:
1551 * Exit to host (r3 > 0)
1552 * 1 An interrupt is pending that needs to be handled by the host
1553 * Exit guest and return to host by branching to guest_exit_cont
1555 * 2 Passthrough that needs completion in the host
1556 * Exit guest and return to host by branching to guest_exit_cont
1557 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1558 * to indicate to the host to complete handling the interrupt
1560 * Before returning to guest, we check if any CPU is heading out
1561 * to the host and if so, we head out also. If no CPUs are heading
1562 * check return values <= 0.
1564 * Return to guest (r3 <= 0)
1565 * 0 No external interrupt is pending
1566 * -1 A guest wakeup IPI (which has now been cleared)
1567 * In either case, we return to guest to deliver any pending
1570 * -2 A PCI passthrough external interrupt was handled
1571 * (interrupt was delivered directly to guest)
1572 * Return to guest to deliver any pending guest interrupts.
1578 /* Return code = 2 */
1579 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1580 stw r12, VCPU_TRAP(r9)
1583 1: /* Return code <= 1 */
1587 /* Return code <= 0 */
1588 maybe_reenter_guest:
1589 ld r5, HSTATE_KVM_VCORE(r13)
1590 lwz r0, VCORE_ENTRY_EXIT(r5)
1593 blt deliver_guest_interrupt
1597 * Check whether an HDSI is an HPTE not found fault or something else.
1598 * If it is an HPTE not found fault that is due to the guest accessing
1599 * a page that they have mapped but which we have paged out, then
1600 * we continue on with the guest exit path. In all other cases,
1601 * reflect the HDSI to the guest as a DSI.
1605 mfspr r6, SPRN_HDSISR
1606 /* HPTE not found fault or protection fault? */
1607 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1608 beq 1f /* if not, send it to the guest */
1609 andi. r0, r11, MSR_DR /* data relocation enabled? */
1612 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1613 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1614 bne 7f /* if no SLB entry found */
1615 4: std r4, VCPU_FAULT_DAR(r9)
1616 stw r6, VCPU_FAULT_DSISR(r9)
1618 /* Search the hash table. */
1619 mr r3, r9 /* vcpu pointer */
1620 li r7, 1 /* data fault */
1621 bl kvmppc_hpte_hv_fault
1622 ld r9, HSTATE_KVM_VCPU(r13)
1624 ld r11, VCPU_MSR(r9)
1625 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1626 cmpdi r3, 0 /* retry the instruction */
1628 cmpdi r3, -1 /* handle in kernel mode */
1630 cmpdi r3, -2 /* MMIO emulation; need instr word */
1633 /* Synthesize a DSI (or DSegI) for the guest */
1634 ld r4, VCPU_FAULT_DAR(r9)
1636 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1637 mtspr SPRN_DSISR, r6
1638 7: mtspr SPRN_DAR, r4
1639 mtspr SPRN_SRR0, r10
1640 mtspr SPRN_SRR1, r11
1642 bl kvmppc_msr_interrupt
1643 fast_interrupt_c_return:
1644 6: ld r7, VCPU_CTR(r9)
1651 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1652 ld r5, KVM_VRMA_SLB_V(r5)
1655 /* If this is for emulated MMIO, load the instruction word */
1656 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1658 /* Set guest mode to 'jump over instruction' so if lwz faults
1659 * we'll just continue at the next IP. */
1660 li r0, KVM_GUEST_MODE_SKIP
1661 stb r0, HSTATE_IN_GUEST(r13)
1663 /* Do the access with MSR:DR enabled */
1665 ori r4, r3, MSR_DR /* Enable paging for data */
1670 /* Store the result */
1671 stw r8, VCPU_LAST_INST(r9)
1673 /* Unset guest mode. */
1674 li r0, KVM_GUEST_MODE_HOST_HV
1675 stb r0, HSTATE_IN_GUEST(r13)
1679 * Similarly for an HISI, reflect it to the guest as an ISI unless
1680 * it is an HPTE not found fault for a page that we have paged out.
1683 andis. r0, r11, SRR1_ISI_NOPT@h
1685 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1688 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1689 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1690 bne 7f /* if no SLB entry found */
1692 /* Search the hash table. */
1693 mr r3, r9 /* vcpu pointer */
1696 li r7, 0 /* instruction fault */
1697 bl kvmppc_hpte_hv_fault
1698 ld r9, HSTATE_KVM_VCPU(r13)
1700 ld r11, VCPU_MSR(r9)
1701 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1702 cmpdi r3, 0 /* retry the instruction */
1703 beq fast_interrupt_c_return
1704 cmpdi r3, -1 /* handle in kernel mode */
1707 /* Synthesize an ISI (or ISegI) for the guest */
1709 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
1710 7: mtspr SPRN_SRR0, r10
1711 mtspr SPRN_SRR1, r11
1713 bl kvmppc_msr_interrupt
1714 b fast_interrupt_c_return
1716 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1717 ld r5, KVM_VRMA_SLB_V(r6)
1721 * Try to handle an hcall in real mode.
1722 * Returns to the guest if we handle it, or continues on up to
1723 * the kernel if we can't (i.e. if we don't have a handler for
1724 * it, or if the handler returns H_TOO_HARD).
1726 * r5 - r8 contain hcall args,
1727 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1729 hcall_try_real_mode:
1730 ld r3,VCPU_GPR(R3)(r9)
1732 /* sc 1 from userspace - reflect to guest syscall */
1733 bne sc_1_fast_return
1735 cmpldi r3,hcall_real_table_end - hcall_real_table
1737 /* See if this hcall is enabled for in-kernel handling */
1739 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1740 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1742 ld r0, KVM_ENABLED_HCALLS(r4)
1743 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1747 /* Get pointer to handler, if any, and call it */
1748 LOAD_REG_ADDR(r4, hcall_real_table)
1754 mr r3,r9 /* get vcpu pointer */
1755 ld r4,VCPU_GPR(R4)(r9)
1758 beq hcall_real_fallback
1759 ld r4,HSTATE_KVM_VCPU(r13)
1760 std r3,VCPU_GPR(R3)(r4)
1768 li r10, BOOK3S_INTERRUPT_SYSCALL
1769 bl kvmppc_msr_interrupt
1773 /* We've attempted a real mode hcall, but it's punted it back
1774 * to userspace. We need to restore some clobbered volatiles
1775 * before resuming the pass-it-to-qemu path */
1776 hcall_real_fallback:
1777 li r12,BOOK3S_INTERRUPT_SYSCALL
1778 ld r9, HSTATE_KVM_VCPU(r13)
1782 .globl hcall_real_table
1784 .long 0 /* 0 - unused */
1785 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1786 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1787 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1788 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
1789 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
1790 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1791 #ifdef CONFIG_SPAPR_TCE_IOMMU
1792 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1793 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
1798 .long 0 /* 0x24 - H_SET_SPRG0 */
1799 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1800 .long DOTSYM(kvmppc_rm_h_page_init) - hcall_real_table
1814 #ifdef CONFIG_KVM_XICS
1815 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1816 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1817 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1818 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
1819 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1821 .long 0 /* 0x64 - H_EOI */
1822 .long 0 /* 0x68 - H_CPPR */
1823 .long 0 /* 0x6c - H_IPI */
1824 .long 0 /* 0x70 - H_IPOLL */
1825 .long 0 /* 0x74 - H_XIRR */
1853 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1854 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
1870 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1874 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
1875 #ifdef CONFIG_SPAPR_TCE_IOMMU
1876 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
1877 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
1993 #ifdef CONFIG_KVM_XICS
1994 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
1996 .long 0 /* 0x2fc - H_XIRR_X*/
1998 .long DOTSYM(kvmppc_rm_h_random) - hcall_real_table
1999 .globl hcall_real_table_end
2000 hcall_real_table_end:
2002 _GLOBAL(kvmppc_h_set_xdabr)
2003 EXPORT_SYMBOL_GPL(kvmppc_h_set_xdabr)
2004 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2006 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2009 6: li r3, H_PARAMETER
2012 _GLOBAL(kvmppc_h_set_dabr)
2013 EXPORT_SYMBOL_GPL(kvmppc_h_set_dabr)
2014 li r5, DABRX_USER | DABRX_KERNEL
2018 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2019 std r4,VCPU_DABR(r3)
2020 stw r5, VCPU_DABRX(r3)
2021 mtspr SPRN_DABRX, r5
2022 /* Work around P7 bug where DABR can get corrupted on mtspr */
2023 1: mtspr SPRN_DABR,r4
2032 LOAD_REG_ADDR(r11, dawr_force_enable)
2039 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2040 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2041 rlwimi r5, r4, 2, DAWRX_WT
2043 std r4, VCPU_DAWR0(r3)
2044 std r5, VCPU_DAWRX0(r3)
2046 * If came in through the real mode hcall handler then it is necessary
2047 * to write the registers since the return path won't. Otherwise it is
2048 * sufficient to store then in the vcpu struct as they will be loaded
2049 * next time the vcpu is run.
2052 andi. r6, r6, MSR_DR /* in real mode? */
2054 mtspr SPRN_DAWR0, r4
2055 mtspr SPRN_DAWRX0, r5
2059 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2061 std r11,VCPU_MSR(r3)
2063 stb r0,VCPU_CEDED(r3)
2064 sync /* order setting ceded vs. testing prodded */
2065 lbz r5,VCPU_PRODDED(r3)
2067 bne kvm_cede_prodded
2068 li r12,0 /* set trap to 0 to say hcall is handled */
2069 stw r12,VCPU_TRAP(r3)
2071 std r0,VCPU_GPR(R3)(r3)
2074 * Set our bit in the bitmask of napping threads unless all the
2075 * other threads are already napping, in which case we send this
2078 ld r5,HSTATE_KVM_VCORE(r13)
2079 lbz r6,HSTATE_PTID(r13)
2080 lwz r8,VCORE_ENTRY_EXIT(r5)
2084 addi r6,r5,VCORE_NAPPING_THREADS
2091 /* order napping_threads update vs testing entry_exit_map */
2094 stb r0,HSTATE_NAPPING(r13)
2095 lwz r7,VCORE_ENTRY_EXIT(r5)
2097 bge 33f /* another thread already exiting */
2100 * Although not specifically required by the architecture, POWER7
2101 * preserves the following registers in nap mode, even if an SMT mode
2102 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2103 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2105 /* Save non-volatile GPRs */
2106 std r14, VCPU_GPR(R14)(r3)
2107 std r15, VCPU_GPR(R15)(r3)
2108 std r16, VCPU_GPR(R16)(r3)
2109 std r17, VCPU_GPR(R17)(r3)
2110 std r18, VCPU_GPR(R18)(r3)
2111 std r19, VCPU_GPR(R19)(r3)
2112 std r20, VCPU_GPR(R20)(r3)
2113 std r21, VCPU_GPR(R21)(r3)
2114 std r22, VCPU_GPR(R22)(r3)
2115 std r23, VCPU_GPR(R23)(r3)
2116 std r24, VCPU_GPR(R24)(r3)
2117 std r25, VCPU_GPR(R25)(r3)
2118 std r26, VCPU_GPR(R26)(r3)
2119 std r27, VCPU_GPR(R27)(r3)
2120 std r28, VCPU_GPR(R28)(r3)
2121 std r29, VCPU_GPR(R29)(r3)
2122 std r30, VCPU_GPR(R30)(r3)
2123 std r31, VCPU_GPR(R31)(r3)
2128 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2131 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
2133 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2135 ld r3, HSTATE_KVM_VCPU(r13)
2137 li r5, 0 /* don't preserve non-vol regs */
2138 bl kvmppc_save_tm_hv
2144 * Set DEC to the smaller of DEC and HDEC, so that we wake
2145 * no later than the end of our timeslice (HDEC interrupts
2146 * don't wake us from nap).
2157 /* save expiry time of guest decrementer */
2159 ld r4, HSTATE_KVM_VCPU(r13)
2160 ld r5, HSTATE_KVM_VCORE(r13)
2161 ld r6, VCORE_TB_OFFSET_APPL(r5)
2162 subf r3, r6, r3 /* convert to host TB value */
2163 std r3, VCPU_DEC_EXPIRES(r4)
2165 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2166 ld r4, HSTATE_KVM_VCPU(r13)
2167 addi r3, r4, VCPU_TB_CEDE
2168 bl kvmhv_accumulate_time
2171 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2173 /* Go back to host stack */
2174 ld r1, HSTATE_HOST_R1(r13)
2177 * Take a nap until a decrementer or external or doobell interrupt
2178 * occurs, with PECE1 and PECE0 set in LPCR.
2179 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2180 * Also clear the runlatch bit before napping.
2183 mfspr r0, SPRN_CTRLF
2185 mtspr SPRN_CTRLT, r0
2188 stb r0,HSTATE_HWTHREAD_REQ(r13)
2190 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2192 ori r5, r5, LPCR_PECEDH
2193 rlwimi r5, r3, 0, LPCR_PECEDP
2194 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2196 kvm_nap_sequence: /* desired LPCR value in r5 */
2197 li r3, PNV_THREAD_NAP
2201 bl isa206_idle_insn_mayloss
2203 mfspr r0, SPRN_CTRLF
2205 mtspr SPRN_CTRLT, r0
2210 stb r0, PACA_FTRACE_ENABLED(r13)
2212 li r0, KVM_HWTHREAD_IN_KVM
2213 stb r0, HSTATE_HWTHREAD_STATE(r13)
2215 lbz r0, HSTATE_NAPPING(r13)
2216 cmpwi r0, NAPPING_CEDE
2218 cmpwi r0, NAPPING_NOVCPU
2219 beq kvm_novcpu_wakeup
2220 cmpwi r0, NAPPING_UNSPLIT
2221 beq kvm_unsplit_wakeup
2222 twi 31,0,0 /* Nap state must not be zero */
2230 /* Woken by external or decrementer interrupt */
2232 /* get vcpu pointer */
2233 ld r4, HSTATE_KVM_VCPU(r13)
2235 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2236 addi r3, r4, VCPU_TB_RMINTR
2237 bl kvmhv_accumulate_time
2240 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2243 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
2245 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2249 li r5, 0 /* don't preserve non-vol regs */
2250 bl kvmppc_restore_tm_hv
2252 ld r4, HSTATE_KVM_VCPU(r13)
2256 /* load up FP state */
2259 /* Restore guest decrementer */
2260 ld r3, VCPU_DEC_EXPIRES(r4)
2261 ld r5, HSTATE_KVM_VCORE(r13)
2262 ld r6, VCORE_TB_OFFSET_APPL(r5)
2263 add r3, r3, r6 /* convert host TB to guest TB value */
2269 ld r14, VCPU_GPR(R14)(r4)
2270 ld r15, VCPU_GPR(R15)(r4)
2271 ld r16, VCPU_GPR(R16)(r4)
2272 ld r17, VCPU_GPR(R17)(r4)
2273 ld r18, VCPU_GPR(R18)(r4)
2274 ld r19, VCPU_GPR(R19)(r4)
2275 ld r20, VCPU_GPR(R20)(r4)
2276 ld r21, VCPU_GPR(R21)(r4)
2277 ld r22, VCPU_GPR(R22)(r4)
2278 ld r23, VCPU_GPR(R23)(r4)
2279 ld r24, VCPU_GPR(R24)(r4)
2280 ld r25, VCPU_GPR(R25)(r4)
2281 ld r26, VCPU_GPR(R26)(r4)
2282 ld r27, VCPU_GPR(R27)(r4)
2283 ld r28, VCPU_GPR(R28)(r4)
2284 ld r29, VCPU_GPR(R29)(r4)
2285 ld r30, VCPU_GPR(R30)(r4)
2286 ld r31, VCPU_GPR(R31)(r4)
2288 /* Check the wake reason in SRR1 to see why we got here */
2289 bl kvmppc_check_wake_reason
2292 * Restore volatile registers since we could have called a
2293 * C routine in kvmppc_check_wake_reason
2295 * r3 tells us whether we need to return to host or not
2296 * WARNING: it gets checked further down:
2297 * should not modify r3 until this check is done.
2299 ld r4, HSTATE_KVM_VCPU(r13)
2301 /* clear our bit in vcore->napping_threads */
2302 34: ld r5,HSTATE_KVM_VCORE(r13)
2303 lbz r7,HSTATE_PTID(r13)
2306 addi r6,r5,VCORE_NAPPING_THREADS
2312 stb r0,HSTATE_NAPPING(r13)
2314 /* See if the wake reason saved in r3 means we need to exit */
2315 stw r12, VCPU_TRAP(r4)
2319 b maybe_reenter_guest
2321 /* cede when already previously prodded case */
2324 stb r0,VCPU_PRODDED(r3)
2325 sync /* order testing prodded vs. clearing ceded */
2326 stb r0,VCPU_CEDED(r3)
2330 /* we've ceded but we want to give control to the host */
2332 ld r9, HSTATE_KVM_VCPU(r13)
2335 /* Try to do machine check recovery in real mode */
2336 machine_check_realmode:
2337 mr r3, r9 /* get vcpu pointer */
2338 bl kvmppc_realmode_machine_check
2340 /* all machine checks go to virtual mode for further handling */
2341 ld r9, HSTATE_KVM_VCPU(r13)
2342 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2346 * Call C code to handle a HMI in real mode.
2347 * Only the primary thread does the call, secondary threads are handled
2348 * by calling hmi_exception_realmode() after kvmppc_hv_entry returns.
2349 * r9 points to the vcpu on entry
2352 lbz r0, HSTATE_PTID(r13)
2355 bl kvmppc_realmode_hmi_handler
2356 ld r9, HSTATE_KVM_VCPU(r13)
2357 li r12, BOOK3S_INTERRUPT_HMI
2361 * Check the reason we woke from nap, and take appropriate action.
2363 * 0 if nothing needs to be done
2364 * 1 if something happened that needs to be handled by the host
2365 * -1 if there was a guest wakeup (IPI or msgsnd)
2366 * -2 if we handled a PCI passthrough interrupt (returned by
2367 * kvmppc_read_intr only)
2369 * Also sets r12 to the interrupt vector for any interrupt that needs
2370 * to be handled now by the host (0x500 for external interrupt), or zero.
2371 * Modifies all volatile registers (since it may call a C function).
2372 * This routine calls kvmppc_read_intr, a C function, if an external
2373 * interrupt is pending.
2375 kvmppc_check_wake_reason:
2378 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2380 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2381 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2382 cmpwi r6, 8 /* was it an external interrupt? */
2383 beq 7f /* if so, see what it was */
2386 cmpwi r6, 6 /* was it the decrementer? */
2389 cmpwi r6, 5 /* privileged doorbell? */
2391 cmpwi r6, 3 /* hypervisor doorbell? */
2393 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2394 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2396 li r3, 1 /* anything else, return 1 */
2399 /* hypervisor doorbell */
2400 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2403 * Clear the doorbell as we will invoke the handler
2404 * explicitly in the guest exit path.
2406 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2408 /* see if it's a host IPI */
2410 lbz r0, HSTATE_HOST_IPI(r13)
2413 /* if not, return -1 */
2417 /* Woken up due to Hypervisor maintenance interrupt */
2418 4: li r12, BOOK3S_INTERRUPT_HMI
2422 /* external interrupt - create a stack frame so we can call C */
2424 std r0, PPC_LR_STKOFF(r1)
2425 stdu r1, -PPC_MIN_STKFRM(r1)
2428 li r12, BOOK3S_INTERRUPT_EXTERNAL
2433 * Return code of 2 means PCI passthrough interrupt, but
2434 * we need to return back to host to complete handling the
2435 * interrupt. Trap reason is expected in r12 by guest
2438 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2440 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2441 addi r1, r1, PPC_MIN_STKFRM
2446 * Save away FP, VMX and VSX registers.
2448 * N.B. r30 and r31 are volatile across this function,
2449 * thus it is not callable from C.
2456 #ifdef CONFIG_ALTIVEC
2458 oris r8,r8,MSR_VEC@h
2459 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2463 oris r8,r8,MSR_VSX@h
2464 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2467 addi r3,r3,VCPU_FPRS
2469 #ifdef CONFIG_ALTIVEC
2471 addi r3,r31,VCPU_VRS
2473 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2475 mfspr r6,SPRN_VRSAVE
2476 stw r6,VCPU_VRSAVE(r31)
2481 * Load up FP, VMX and VSX registers
2483 * N.B. r30 and r31 are volatile across this function,
2484 * thus it is not callable from C.
2491 #ifdef CONFIG_ALTIVEC
2493 oris r8,r8,MSR_VEC@h
2494 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2498 oris r8,r8,MSR_VSX@h
2499 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2502 addi r3,r4,VCPU_FPRS
2504 #ifdef CONFIG_ALTIVEC
2506 addi r3,r31,VCPU_VRS
2508 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2510 lwz r7,VCPU_VRSAVE(r31)
2511 mtspr SPRN_VRSAVE,r7
2516 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2518 * Save transactional state and TM-related registers.
2519 * Called with r3 pointing to the vcpu struct and r4 containing
2520 * the guest MSR value.
2521 * r5 is non-zero iff non-volatile register state needs to be maintained.
2522 * If r5 == 0, this can modify all checkpointed registers, but
2523 * restores r1 and r2 before exit.
2525 _GLOBAL_TOC(kvmppc_save_tm_hv)
2526 EXPORT_SYMBOL_GPL(kvmppc_save_tm_hv)
2527 /* See if we need to handle fake suspend mode */
2530 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
2532 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
2534 beq __kvmppc_save_tm
2536 /* The following code handles the fake_suspend = 1 case */
2538 std r0, PPC_LR_STKOFF(r1)
2539 stdu r1, -PPC_MIN_STKFRM(r1)
2544 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2547 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
2550 bl pnv_power9_force_smt4_catch
2551 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
2554 /* We have to treclaim here because that's the only way to do S->N */
2555 li r3, TM_CAUSE_KVM_RESCHED
2559 * We were in fake suspend, so we are not going to save the
2560 * register state as the guest checkpointed state (since
2561 * we already have it), therefore we can now use any volatile GPR.
2562 * In fact treclaim in fake suspend state doesn't modify
2567 bl pnv_power9_force_smt4_release
2568 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
2572 mfspr r3, SPRN_PSSCR
2573 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
2574 li r0, PSSCR_FAKE_SUSPEND
2576 mtspr SPRN_PSSCR, r3
2578 /* Don't save TEXASR, use value from last exit in real suspend state */
2579 ld r9, HSTATE_KVM_VCPU(r13)
2580 mfspr r5, SPRN_TFHAR
2581 mfspr r6, SPRN_TFIAR
2582 std r5, VCPU_TFHAR(r9)
2583 std r6, VCPU_TFIAR(r9)
2585 addi r1, r1, PPC_MIN_STKFRM
2586 ld r0, PPC_LR_STKOFF(r1)
2591 * Restore transactional state and TM-related registers.
2592 * Called with r3 pointing to the vcpu struct
2593 * and r4 containing the guest MSR value.
2594 * r5 is non-zero iff non-volatile register state needs to be maintained.
2595 * This potentially modifies all checkpointed registers.
2596 * It restores r1 and r2 from the PACA.
2598 _GLOBAL_TOC(kvmppc_restore_tm_hv)
2599 EXPORT_SYMBOL_GPL(kvmppc_restore_tm_hv)
2601 * If we are doing TM emulation for the guest on a POWER9 DD2,
2602 * then we don't actually do a trechkpt -- we either set up
2603 * fake-suspend mode, or emulate a TM rollback.
2606 b __kvmppc_restore_tm
2607 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
2609 std r0, PPC_LR_STKOFF(r1)
2612 stb r0, HSTATE_FAKE_SUSPEND(r13)
2614 /* Turn on TM so we can restore TM SPRs */
2617 rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
2621 * The user may change these outside of a transaction, so they must
2622 * always be context switched.
2624 ld r5, VCPU_TFHAR(r3)
2625 ld r6, VCPU_TFIAR(r3)
2626 ld r7, VCPU_TEXASR(r3)
2627 mtspr SPRN_TFHAR, r5
2628 mtspr SPRN_TFIAR, r6
2629 mtspr SPRN_TEXASR, r7
2631 rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
2632 beqlr /* TM not active in guest */
2634 /* Make sure the failure summary is set */
2635 oris r7, r7, (TEXASR_FS)@h
2636 mtspr SPRN_TEXASR, r7
2638 cmpwi r5, 1 /* check for suspended state */
2640 stb r5, HSTATE_FAKE_SUSPEND(r13)
2641 b 9f /* and return */
2642 10: stdu r1, -PPC_MIN_STKFRM(r1)
2643 /* guest is in transactional state, so simulate rollback */
2644 bl kvmhv_emulate_tm_rollback
2646 addi r1, r1, PPC_MIN_STKFRM
2647 9: ld r0, PPC_LR_STKOFF(r1)
2650 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2653 * We come here if we get any exception or interrupt while we are
2654 * executing host real mode code while in guest MMU context.
2655 * r12 is (CR << 32) | vector
2656 * r13 points to our PACA
2657 * r12 is saved in HSTATE_SCRATCH0(r13)
2658 * r9 is saved in HSTATE_SCRATCH2(r13)
2659 * r13 is saved in HSPRG1
2660 * cfar is saved in HSTATE_CFAR(r13)
2661 * ppr is saved in HSTATE_PPR(r13)
2663 kvmppc_bad_host_intr:
2665 * Switch to the emergency stack, but start half-way down in
2666 * case we were already on it.
2670 ld r1, PACAEMERGSP(r13)
2671 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
2684 mfspr r3, SPRN_HSRR0
2685 mfspr r4, SPRN_HSRR1
2687 mfspr r6, SPRN_HDSISR
2689 1: mfspr r3, SPRN_SRR0
2692 mfspr r6, SPRN_DSISR
2697 ld r9, HSTATE_SCRATCH2(r13)
2698 ld r12, HSTATE_SCRATCH0(r13)
2703 ld r5, HSTATE_CFAR(r13)
2704 std r5, ORIG_GPR3(r1)
2708 lbz r6, PACAIRQSOFTMASK(r13)
2714 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
2715 std r3, STACK_FRAME_OVERHEAD-16(r1)
2718 * XXX On POWER7 and POWER8, we just spin here since we don't
2719 * know what the other threads are doing (and we don't want to
2720 * coordinate with them) - but at least we now have register state
2721 * in memory that we might be able to look at from another CPU.
2726 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2727 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2728 * r11 has the guest MSR value (in/out)
2729 * r9 has a vcpu pointer (in)
2730 * r0 is used as a scratch register
2732 kvmppc_msr_interrupt:
2733 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2734 cmpwi r0, 2 /* Check if we are in transactional state.. */
2735 ld r11, VCPU_INTR_MSR(r9)
2737 /* ... if transactional, change to suspended */
2739 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2743 * Load up guest PMU state. R3 points to the vcpu struct.
2745 _GLOBAL(kvmhv_load_guest_pmu)
2746 EXPORT_SYMBOL_GPL(kvmhv_load_guest_pmu)
2750 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
2751 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
2754 ld r3, VCPU_MMCR(r4)
2755 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
2756 cmpwi r5, MMCR0_PMAO
2757 beql kvmppc_fix_pmao
2758 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
2759 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
2760 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
2761 lwz r6, VCPU_PMC + 8(r4)
2762 lwz r7, VCPU_PMC + 12(r4)
2763 lwz r8, VCPU_PMC + 16(r4)
2764 lwz r9, VCPU_PMC + 20(r4)
2771 ld r3, VCPU_MMCR(r4)
2772 ld r5, VCPU_MMCR + 8(r4)
2773 ld r6, VCPU_MMCRA(r4)
2774 ld r7, VCPU_SIAR(r4)
2775 ld r8, VCPU_SDAR(r4)
2776 mtspr SPRN_MMCR1, r5
2777 mtspr SPRN_MMCRA, r6
2781 ld r5, VCPU_MMCR + 24(r4)
2782 ld r6, VCPU_SIER + 8(r4)
2783 ld r7, VCPU_SIER + 16(r4)
2784 mtspr SPRN_MMCR3, r5
2785 mtspr SPRN_SIER2, r6
2786 mtspr SPRN_SIER3, r7
2787 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
2789 ld r5, VCPU_MMCR + 16(r4)
2790 ld r6, VCPU_SIER(r4)
2791 mtspr SPRN_MMCR2, r5
2793 BEGIN_FTR_SECTION_NESTED(96)
2794 lwz r7, VCPU_PMC + 24(r4)
2795 lwz r8, VCPU_PMC + 28(r4)
2796 ld r9, VCPU_MMCRS(r4)
2797 mtspr SPRN_SPMC1, r7
2798 mtspr SPRN_SPMC2, r8
2799 mtspr SPRN_MMCRS, r9
2800 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
2801 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2802 mtspr SPRN_MMCR0, r3
2808 * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
2810 _GLOBAL(kvmhv_load_host_pmu)
2811 EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
2813 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
2815 beq 23f /* skip if not */
2817 ld r3, HSTATE_MMCR0(r13)
2818 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
2819 cmpwi r4, MMCR0_PMAO
2820 beql kvmppc_fix_pmao
2821 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
2822 lwz r3, HSTATE_PMC1(r13)
2823 lwz r4, HSTATE_PMC2(r13)
2824 lwz r5, HSTATE_PMC3(r13)
2825 lwz r6, HSTATE_PMC4(r13)
2826 lwz r8, HSTATE_PMC5(r13)
2827 lwz r9, HSTATE_PMC6(r13)
2834 ld r3, HSTATE_MMCR0(r13)
2835 ld r4, HSTATE_MMCR1(r13)
2836 ld r5, HSTATE_MMCRA(r13)
2837 ld r6, HSTATE_SIAR(r13)
2838 ld r7, HSTATE_SDAR(r13)
2839 mtspr SPRN_MMCR1, r4
2840 mtspr SPRN_MMCRA, r5
2844 ld r8, HSTATE_MMCR2(r13)
2845 ld r9, HSTATE_SIER(r13)
2846 mtspr SPRN_MMCR2, r8
2848 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2850 ld r5, HSTATE_MMCR3(r13)
2851 ld r6, HSTATE_SIER2(r13)
2852 ld r7, HSTATE_SIER3(r13)
2853 mtspr SPRN_MMCR3, r5
2854 mtspr SPRN_SIER2, r6
2855 mtspr SPRN_SIER3, r7
2856 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
2857 mtspr SPRN_MMCR0, r3
2863 * Save guest PMU state into the vcpu struct.
2864 * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
2866 _GLOBAL(kvmhv_save_guest_pmu)
2867 EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
2872 * POWER8 seems to have a hardware bug where setting
2873 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
2874 * when some counters are already negative doesn't seem
2875 * to cause a performance monitor alert (and hence interrupt).
2876 * The effect of this is that when saving the PMU state,
2877 * if there is no PMU alert pending when we read MMCR0
2878 * before freezing the counters, but one becomes pending
2879 * before we read the counters, we lose it.
2880 * To work around this, we need a way to freeze the counters
2881 * before reading MMCR0. Normally, freezing the counters
2882 * is done by writing MMCR0 (to set MMCR0[FC]) which
2883 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
2884 * we can also freeze the counters using MMCR2, by writing
2885 * 1s to all the counter freeze condition bits (there are
2886 * 9 bits each for 6 counters).
2888 li r3, -1 /* set all freeze bits */
2890 mfspr r10, SPRN_MMCR2
2891 mtspr SPRN_MMCR2, r3
2893 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2895 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
2896 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
2897 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
2898 mfspr r6, SPRN_MMCRA
2899 /* Clear MMCRA in order to disable SDAR updates */
2901 mtspr SPRN_MMCRA, r7
2903 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
2905 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
2907 21: mfspr r5, SPRN_MMCR1
2910 std r4, VCPU_MMCR(r9)
2911 std r5, VCPU_MMCR + 8(r9)
2912 std r6, VCPU_MMCRA(r9)
2914 std r10, VCPU_MMCR + 16(r9)
2915 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2917 mfspr r5, SPRN_MMCR3
2918 mfspr r6, SPRN_SIER2
2919 mfspr r7, SPRN_SIER3
2920 std r5, VCPU_MMCR + 24(r9)
2921 std r6, VCPU_SIER + 8(r9)
2922 std r7, VCPU_SIER + 16(r9)
2923 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
2924 std r7, VCPU_SIAR(r9)
2925 std r8, VCPU_SDAR(r9)
2932 stw r3, VCPU_PMC(r9)
2933 stw r4, VCPU_PMC + 4(r9)
2934 stw r5, VCPU_PMC + 8(r9)
2935 stw r6, VCPU_PMC + 12(r9)
2936 stw r7, VCPU_PMC + 16(r9)
2937 stw r8, VCPU_PMC + 20(r9)
2940 std r5, VCPU_SIER(r9)
2941 BEGIN_FTR_SECTION_NESTED(96)
2942 mfspr r6, SPRN_SPMC1
2943 mfspr r7, SPRN_SPMC2
2944 mfspr r8, SPRN_MMCRS
2945 stw r6, VCPU_PMC + 24(r9)
2946 stw r7, VCPU_PMC + 28(r9)
2947 std r8, VCPU_MMCRS(r9)
2949 mtspr SPRN_MMCRS, r4
2950 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
2951 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2955 * This works around a hardware bug on POWER8E processors, where
2956 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2957 * performance monitor interrupt. Instead, when we need to have
2958 * an interrupt pending, we have to arrange for a counter to overflow.
2962 mtspr SPRN_MMCR2, r3
2963 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2964 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2965 mtspr SPRN_MMCR0, r3
2972 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2974 * Start timing an activity
2975 * r3 = pointer to time accumulation struct, r4 = vcpu
2978 ld r5, HSTATE_KVM_VCORE(r13)
2979 ld r6, VCORE_TB_OFFSET_APPL(r5)
2981 subf r5, r6, r5 /* subtract current timebase offset */
2982 std r3, VCPU_CUR_ACTIVITY(r4)
2983 std r5, VCPU_ACTIVITY_START(r4)
2987 * Accumulate time to one activity and start another.
2988 * r3 = pointer to new time accumulation struct, r4 = vcpu
2990 kvmhv_accumulate_time:
2991 ld r5, HSTATE_KVM_VCORE(r13)
2992 ld r8, VCORE_TB_OFFSET_APPL(r5)
2993 ld r5, VCPU_CUR_ACTIVITY(r4)
2994 ld r6, VCPU_ACTIVITY_START(r4)
2995 std r3, VCPU_CUR_ACTIVITY(r4)
2997 subf r7, r8, r7 /* subtract current timebase offset */
2998 std r7, VCPU_ACTIVITY_START(r4)
3002 ld r8, TAS_SEQCOUNT(r5)
3005 std r8, TAS_SEQCOUNT(r5)
3007 ld r7, TAS_TOTAL(r5)
3009 std r7, TAS_TOTAL(r5)
3015 3: std r3, TAS_MIN(r5)
3021 std r8, TAS_SEQCOUNT(r5)