1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Copyright 2007-2010 Freescale Semiconductor, Inc.
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@samba.org)
11 * This file handles the architecture-dependent parts of hardware exceptions
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/kernel.h>
19 #include <linux/pkeys.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/user.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/extable.h>
27 #include <linux/module.h> /* print_modules */
28 #include <linux/prctl.h>
29 #include <linux/delay.h>
30 #include <linux/kprobes.h>
31 #include <linux/kexec.h>
32 #include <linux/backlight.h>
33 #include <linux/bug.h>
34 #include <linux/kdebug.h>
35 #include <linux/ratelimit.h>
36 #include <linux/context_tracking.h>
37 #include <linux/smp.h>
38 #include <linux/console.h>
39 #include <linux/kmsg_dump.h>
41 #include <asm/emulated_ops.h>
42 #include <linux/uaccess.h>
43 #include <asm/debugfs.h>
44 #include <asm/interrupt.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
57 #include <asm/kexec.h>
58 #include <asm/ppc-opcode.h>
60 #include <asm/fadump.h>
61 #include <asm/switch_to.h>
63 #include <asm/debug.h>
64 #include <asm/asm-prototypes.h>
66 #include <sysdev/fsl_pci.h>
67 #include <asm/kprobes.h>
68 #include <asm/stacktrace.h>
70 #include <asm/disassemble.h>
72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
73 int (*__debugger)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
81 EXPORT_SYMBOL(__debugger);
82 EXPORT_SYMBOL(__debugger_ipi);
83 EXPORT_SYMBOL(__debugger_bpt);
84 EXPORT_SYMBOL(__debugger_sstep);
85 EXPORT_SYMBOL(__debugger_iabr_match);
86 EXPORT_SYMBOL(__debugger_break_match);
87 EXPORT_SYMBOL(__debugger_fault_handler);
90 /* Transactional Memory trap debug */
92 #define TM_DEBUG(x...) printk(KERN_INFO x)
94 #define TM_DEBUG(x...) do { } while(0)
97 static const char *signame(int signr)
100 case SIGBUS: return "bus error";
101 case SIGFPE: return "floating point exception";
102 case SIGILL: return "illegal instruction";
103 case SIGSEGV: return "segfault";
104 case SIGTRAP: return "unhandled trap";
107 return "unknown signal";
111 * Trap & Exception support
114 #ifdef CONFIG_PMAC_BACKLIGHT
115 static void pmac_backlight_unblank(void)
117 mutex_lock(&pmac_backlight_mutex);
118 if (pmac_backlight) {
119 struct backlight_properties *props;
121 props = &pmac_backlight->props;
122 props->brightness = props->max_brightness;
123 props->power = FB_BLANK_UNBLANK;
124 backlight_update_status(pmac_backlight);
126 mutex_unlock(&pmac_backlight_mutex);
129 static inline void pmac_backlight_unblank(void) { }
133 * If oops/die is expected to crash the machine, return true here.
135 * This should not be expected to be 100% accurate, there may be
136 * notifiers registered or other unexpected conditions that may bring
137 * down the kernel. Or if the current process in the kernel is holding
138 * locks or has other critical state, the kernel may become effectively
141 bool die_will_crash(void)
143 if (should_fadump_crash())
145 if (kexec_should_crash(current))
147 if (in_interrupt() || panic_on_oops ||
148 !current->pid || is_global_init(current))
154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
155 static int die_owner = -1;
156 static unsigned int die_nest_count;
157 static int die_counter;
159 extern void panic_flush_kmsg_start(void)
162 * These are mostly taken from kernel/panic.c, but tries to do
163 * relatively minimal work. Don't use delay functions (TB may
164 * be broken), don't crash dump (need to set a firmware log),
165 * don't run notifiers. We do want to get some information to
172 extern void panic_flush_kmsg_end(void)
174 kmsg_dump(KMSG_DUMP_PANIC);
177 console_flush_on_panic(CONSOLE_FLUSH_PENDING);
180 static unsigned long oops_begin(struct pt_regs *regs)
187 /* racy, but better than risking deadlock. */
188 raw_local_irq_save(flags);
189 cpu = smp_processor_id();
190 if (!arch_spin_trylock(&die_lock)) {
191 if (cpu == die_owner)
192 /* nested oops. should stop eventually */;
194 arch_spin_lock(&die_lock);
200 if (machine_is(powermac))
201 pmac_backlight_unblank();
204 NOKPROBE_SYMBOL(oops_begin);
206 static void oops_end(unsigned long flags, struct pt_regs *regs,
210 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
214 if (!die_nest_count) {
215 /* Nest count reaches zero, release the lock. */
217 arch_spin_unlock(&die_lock);
219 raw_local_irq_restore(flags);
222 * system_reset_excption handles debugger, crash dump, panic, for 0x100
224 if (TRAP(regs) == INTERRUPT_SYSTEM_RESET)
227 crash_fadump(regs, "die oops");
229 if (kexec_should_crash(current))
236 * While our oops output is serialised by a spinlock, output
237 * from panic() called below can race and corrupt it. If we
238 * know we are going to panic, delay for 1 second so we have a
239 * chance to get clean backtraces from all CPUs that are oopsing.
241 if (in_interrupt() || panic_on_oops || !current->pid ||
242 is_global_init(current)) {
243 mdelay(MSEC_PER_SEC);
247 panic("Fatal exception");
250 NOKPROBE_SYMBOL(oops_end);
252 static char *get_mmu_str(void)
254 if (early_radix_enabled())
256 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE))
261 static int __die(const char *str, struct pt_regs *regs, long err)
263 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
265 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
266 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
267 PAGE_SIZE / 1024, get_mmu_str(),
268 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
269 IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
270 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
271 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
272 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "",
273 ppc_md.name ? ppc_md.name : "");
275 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
283 NOKPROBE_SYMBOL(__die);
285 void die(const char *str, struct pt_regs *regs, long err)
290 * system_reset_excption handles debugger, crash dump, panic, for 0x100
292 if (TRAP(regs) != INTERRUPT_SYSTEM_RESET) {
297 flags = oops_begin(regs);
298 if (__die(str, regs, err))
300 oops_end(flags, regs, err);
302 NOKPROBE_SYMBOL(die);
304 void user_single_step_report(struct pt_regs *regs)
306 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip);
309 static void show_signal_msg(int signr, struct pt_regs *regs, int code,
312 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
313 DEFAULT_RATELIMIT_BURST);
315 if (!show_unhandled_signals)
318 if (!unhandled_signal(current, signr))
321 if (!__ratelimit(&rs))
324 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
325 current->comm, current->pid, signame(signr), signr,
326 addr, regs->nip, regs->link, code);
328 print_vma_addr(KERN_CONT " in ", regs->nip);
332 show_user_instructions(regs);
335 static bool exception_common(int signr, struct pt_regs *regs, int code,
338 if (!user_mode(regs)) {
339 die("Exception in kernel mode", regs, signr);
343 show_signal_msg(signr, regs, code, addr);
345 if (arch_irqs_disabled())
346 interrupt_cond_local_irq_enable(regs);
348 current->thread.trap_nr = code;
353 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key)
355 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr))
358 force_sig_pkuerr((void __user *) addr, key);
361 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
363 if (!exception_common(signr, regs, code, addr))
366 force_sig_fault(signr, code, (void __user *)addr);
370 * The interrupt architecture has a quirk in that the HV interrupts excluding
371 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing
372 * that an interrupt handler must do is save off a GPR into a scratch register,
373 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch.
374 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing
375 * that it is non-reentrant, which leads to random data corruption.
377 * The solution is for NMI interrupts in HV mode to check if they originated
378 * from these critical HV interrupt regions. If so, then mark them not
381 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the
382 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux
383 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so
384 * that would work. However any other guest OS that may have the SPRG live
385 * and MSR[RI]=1 could encounter silent corruption.
387 * Builds that do not support KVM could take this second option to increase
388 * the recoverability of NMIs.
390 void hv_nmi_check_nonrecoverable(struct pt_regs *regs)
392 #ifdef CONFIG_PPC_POWERNV
393 unsigned long kbase = (unsigned long)_stext;
394 unsigned long nip = regs->nip;
396 if (!(regs->msr & MSR_RI))
398 if (!(regs->msr & MSR_HV))
400 if (regs->msr & MSR_PR)
404 * Now test if the interrupt has hit a range that may be using
405 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The
406 * problem ranges all run un-relocated. Test real and virt modes
407 * at the same time by dropping the high bit of the nip (virt mode
408 * entry points still have the +0x4000 offset).
410 nip &= ~0xc000000000000000ULL;
411 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600))
413 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00))
415 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0))
417 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0))
420 /* Trampoline code runs un-relocated so subtract kbase. */
421 if (nip >= (unsigned long)(start_real_trampolines - kbase) &&
422 nip < (unsigned long)(end_real_trampolines - kbase))
424 if (nip >= (unsigned long)(start_virt_trampolines - kbase) &&
425 nip < (unsigned long)(end_virt_trampolines - kbase))
430 regs_set_return_msr(regs, regs->msr & ~MSR_RI);
433 DEFINE_INTERRUPT_HANDLER_NMI(system_reset_exception)
435 unsigned long hsrr0, hsrr1;
436 bool saved_hsrrs = false;
439 * System reset can interrupt code where HSRRs are live and MSR[RI]=1.
440 * The system reset interrupt itself may clobber HSRRs (e.g., to call
441 * OPAL), so save them here and restore them before returning.
443 * Machine checks don't need to save HSRRs, as the real mode handler
444 * is careful to avoid them, and the regular handler is not delivered
447 if (cpu_has_feature(CPU_FTR_HVMODE)) {
448 hsrr0 = mfspr(SPRN_HSRR0);
449 hsrr1 = mfspr(SPRN_HSRR1);
453 hv_nmi_check_nonrecoverable(regs);
455 __this_cpu_inc(irq_stat.sreset_irqs);
457 /* See if any machine dependent calls */
458 if (ppc_md.system_reset_exception) {
459 if (ppc_md.system_reset_exception(regs))
466 kmsg_dump(KMSG_DUMP_OOPS);
468 * A system reset is a request to dump, so we always send
469 * it through the crashdump code (if fadump or kdump are
472 crash_fadump(regs, "System Reset");
477 * We aren't the primary crash CPU. We need to send it
478 * to a holding pattern to avoid it ending up in the panic
481 crash_kexec_secondary(regs);
484 * No debugger or crash dump registered, print logs then
487 die("System Reset", regs, SIGABRT);
489 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
490 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
491 nmi_panic(regs, "System Reset");
494 #ifdef CONFIG_PPC_BOOK3S_64
495 BUG_ON(get_paca()->in_nmi == 0);
496 if (get_paca()->in_nmi > 1)
497 die("Unrecoverable nested System Reset", regs, SIGABRT);
499 /* Must die if the interrupt is not recoverable */
500 if (!(regs->msr & MSR_RI)) {
501 /* For the reason explained in die_mce, nmi_exit before die */
503 die("Unrecoverable System Reset", regs, SIGABRT);
507 mtspr(SPRN_HSRR0, hsrr0);
508 mtspr(SPRN_HSRR1, hsrr1);
511 /* What should we do here? We could issue a shutdown or hard reset. */
517 * I/O accesses can cause machine checks on powermacs.
518 * Check if the NIP corresponds to the address of a sync
519 * instruction for which there is an entry in the exception
523 static inline int check_io_access(struct pt_regs *regs)
526 unsigned long msr = regs->msr;
527 const struct exception_table_entry *entry;
528 unsigned int *nip = (unsigned int *)regs->nip;
530 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
531 && (entry = search_exception_tables(regs->nip)) != NULL) {
533 * Check that it's a sync instruction, or somewhere
534 * in the twi; isync; nop sequence that inb/inw/inl uses.
535 * As the address is in the exception table
536 * we should be able to read the instr there.
537 * For the debug message, we look at the preceding
540 if (*nip == PPC_RAW_NOP())
542 else if (*nip == PPC_RAW_ISYNC())
544 if (*nip == PPC_RAW_SYNC() || get_op(*nip) == OP_TRAP) {
548 rb = (*nip >> 11) & 0x1f;
549 printk(KERN_DEBUG "%s bad port %lx at %p\n",
550 (*nip & 0x100)? "OUT to": "IN from",
551 regs->gpr[rb] - _IO_BASE, nip);
552 regs_set_return_msr(regs, regs->msr | MSR_RI);
553 regs_set_return_ip(regs, extable_fixup(entry));
557 #endif /* CONFIG_PPC32 */
561 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
562 /* On 4xx, the reason for the machine check or program exception
564 #define get_reason(regs) ((regs)->dsisr)
565 #define REASON_FP ESR_FP
566 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
567 #define REASON_PRIVILEGED ESR_PPR
568 #define REASON_TRAP ESR_PTR
569 #define REASON_PREFIXED 0
570 #define REASON_BOUNDARY 0
572 /* single-step stuff */
573 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
574 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
575 #define clear_br_trace(regs) do {} while(0)
577 /* On non-4xx, the reason for the machine check or program
578 exception is in the MSR. */
579 #define get_reason(regs) ((regs)->msr)
580 #define REASON_TM SRR1_PROGTM
581 #define REASON_FP SRR1_PROGFPE
582 #define REASON_ILLEGAL SRR1_PROGILL
583 #define REASON_PRIVILEGED SRR1_PROGPRIV
584 #define REASON_TRAP SRR1_PROGTRAP
585 #define REASON_PREFIXED SRR1_PREFIXED
586 #define REASON_BOUNDARY SRR1_BOUNDARY
588 #define single_stepping(regs) ((regs)->msr & MSR_SE)
589 #define clear_single_step(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_SE))
590 #define clear_br_trace(regs) (regs_set_return_msr((regs), (regs)->msr & ~MSR_BE))
593 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4)
595 #if defined(CONFIG_E500)
596 int machine_check_e500mc(struct pt_regs *regs)
598 unsigned long mcsr = mfspr(SPRN_MCSR);
599 unsigned long pvr = mfspr(SPRN_PVR);
600 unsigned long reason = mcsr;
603 if (reason & MCSR_LD) {
604 recoverable = fsl_rio_mcheck_exception(regs);
605 if (recoverable == 1)
609 printk("Machine check in kernel mode.\n");
610 printk("Caused by (from MCSR=%lx): ", reason);
612 if (reason & MCSR_MCP)
613 pr_cont("Machine Check Signal\n");
615 if (reason & MCSR_ICPERR) {
616 pr_cont("Instruction Cache Parity Error\n");
619 * This is recoverable by invalidating the i-cache.
621 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
622 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
626 * This will generally be accompanied by an instruction
627 * fetch error report -- only treat MCSR_IF as fatal
628 * if it wasn't due to an L1 parity error.
633 if (reason & MCSR_DCPERR_MC) {
634 pr_cont("Data Cache Parity Error\n");
637 * In write shadow mode we auto-recover from the error, but it
638 * may still get logged and cause a machine check. We should
639 * only treat the non-write shadow case as non-recoverable.
641 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
642 * is not implemented but L1 data cache always runs in write
643 * shadow mode. Hence on data cache parity errors HW will
644 * automatically invalidate the L1 Data Cache.
646 if (PVR_VER(pvr) != PVR_VER_E6500) {
647 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
652 if (reason & MCSR_L2MMU_MHIT) {
653 pr_cont("Hit on multiple TLB entries\n");
657 if (reason & MCSR_NMI)
658 pr_cont("Non-maskable interrupt\n");
660 if (reason & MCSR_IF) {
661 pr_cont("Instruction Fetch Error Report\n");
665 if (reason & MCSR_LD) {
666 pr_cont("Load Error Report\n");
670 if (reason & MCSR_ST) {
671 pr_cont("Store Error Report\n");
675 if (reason & MCSR_LDG) {
676 pr_cont("Guarded Load Error Report\n");
680 if (reason & MCSR_TLBSYNC)
681 pr_cont("Simultaneous tlbsync operations\n");
683 if (reason & MCSR_BSL2_ERR) {
684 pr_cont("Level 2 Cache Error\n");
688 if (reason & MCSR_MAV) {
691 addr = mfspr(SPRN_MCAR);
692 addr |= (u64)mfspr(SPRN_MCARU) << 32;
694 pr_cont("Machine Check %s Address: %#llx\n",
695 reason & MCSR_MEA ? "Effective" : "Physical", addr);
699 mtspr(SPRN_MCSR, mcsr);
700 return mfspr(SPRN_MCSR) == 0 && recoverable;
703 int machine_check_e500(struct pt_regs *regs)
705 unsigned long reason = mfspr(SPRN_MCSR);
707 if (reason & MCSR_BUS_RBERR) {
708 if (fsl_rio_mcheck_exception(regs))
710 if (fsl_pci_mcheck_exception(regs))
714 printk("Machine check in kernel mode.\n");
715 printk("Caused by (from MCSR=%lx): ", reason);
717 if (reason & MCSR_MCP)
718 pr_cont("Machine Check Signal\n");
719 if (reason & MCSR_ICPERR)
720 pr_cont("Instruction Cache Parity Error\n");
721 if (reason & MCSR_DCP_PERR)
722 pr_cont("Data Cache Push Parity Error\n");
723 if (reason & MCSR_DCPERR)
724 pr_cont("Data Cache Parity Error\n");
725 if (reason & MCSR_BUS_IAERR)
726 pr_cont("Bus - Instruction Address Error\n");
727 if (reason & MCSR_BUS_RAERR)
728 pr_cont("Bus - Read Address Error\n");
729 if (reason & MCSR_BUS_WAERR)
730 pr_cont("Bus - Write Address Error\n");
731 if (reason & MCSR_BUS_IBERR)
732 pr_cont("Bus - Instruction Data Error\n");
733 if (reason & MCSR_BUS_RBERR)
734 pr_cont("Bus - Read Data Bus Error\n");
735 if (reason & MCSR_BUS_WBERR)
736 pr_cont("Bus - Write Data Bus Error\n");
737 if (reason & MCSR_BUS_IPERR)
738 pr_cont("Bus - Instruction Parity Error\n");
739 if (reason & MCSR_BUS_RPERR)
740 pr_cont("Bus - Read Parity Error\n");
745 int machine_check_generic(struct pt_regs *regs)
749 #elif defined(CONFIG_PPC32)
750 int machine_check_generic(struct pt_regs *regs)
752 unsigned long reason = regs->msr;
754 printk("Machine check in kernel mode.\n");
755 printk("Caused by (from SRR1=%lx): ", reason);
756 switch (reason & 0x601F0000) {
758 pr_cont("Machine check signal\n");
761 case 0x140000: /* 7450 MSS error and TEA */
762 pr_cont("Transfer error ack signal\n");
765 pr_cont("Data parity error signal\n");
768 pr_cont("Address parity error signal\n");
771 pr_cont("L1 Data Cache error\n");
774 pr_cont("L1 Instruction Cache error\n");
777 pr_cont("L2 data cache parity error\n");
780 pr_cont("Unknown values in msr\n");
784 #endif /* everything else */
786 void die_mce(const char *str, struct pt_regs *regs, long err)
789 * The machine check wants to kill the interrupted context, but
790 * do_exit() checks for in_interrupt() and panics in that case, so
791 * exit the irq/nmi before calling die.
793 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64))
801 * BOOK3S_64 does not call this handler as a non-maskable interrupt
802 * (it uses its own early real-mode handler to handle the MCE proper
803 * and then raises irq_work to call this handler when interrupts are
806 #ifdef CONFIG_PPC_BOOK3S_64
807 DEFINE_INTERRUPT_HANDLER_ASYNC(machine_check_exception)
809 DEFINE_INTERRUPT_HANDLER_NMI(machine_check_exception)
814 __this_cpu_inc(irq_stat.mce_exceptions);
816 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
818 /* See if any machine dependent calls. In theory, we would want
819 * to call the CPU first, and call the ppc_md. one if the CPU
820 * one returns a positive number. However there is existing code
821 * that assumes the board gets a first chance, so let's keep it
822 * that way for now and fix things later. --BenH.
824 if (ppc_md.machine_check_exception)
825 recover = ppc_md.machine_check_exception(regs);
826 else if (cur_cpu_spec->machine_check)
827 recover = cur_cpu_spec->machine_check(regs);
832 if (debugger_fault_handler(regs))
835 if (check_io_access(regs))
838 die_mce("Machine check", regs, SIGBUS);
841 /* Must die if the interrupt is not recoverable */
842 if (!(regs->msr & MSR_RI))
843 die_mce("Unrecoverable Machine check", regs, SIGBUS);
845 #ifdef CONFIG_PPC_BOOK3S_64
852 DEFINE_INTERRUPT_HANDLER(SMIException) /* async? */
854 die("System Management Interrupt", regs, SIGABRT);
858 static void p9_hmi_special_emu(struct pt_regs *regs)
860 unsigned int ra, rb, t, i, sel, instr, rc;
861 const void __user *addr;
862 u8 vbuf[16] __aligned(16), *vdst;
863 unsigned long ea, msr, msr_mask;
866 if (__get_user(instr, (unsigned int __user *)regs->nip))
870 * lxvb16x opcode: 0x7c0006d8
871 * lxvd2x opcode: 0x7c000698
872 * lxvh8x opcode: 0x7c000658
873 * lxvw4x opcode: 0x7c000618
875 if ((instr & 0xfc00073e) != 0x7c000618) {
876 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
878 smp_processor_id(), current->comm, current->pid,
883 /* Grab vector registers into the task struct */
884 msr = regs->msr; /* Grab msr before we flush the bits */
885 flush_vsx_to_thread(current);
886 enable_kernel_altivec();
889 * Is userspace running with a different endian (this is rare but
892 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
894 /* Decode the instruction */
895 ra = (instr >> 16) & 0x1f;
896 rb = (instr >> 11) & 0x1f;
897 t = (instr >> 21) & 0x1f;
899 vdst = (u8 *)¤t->thread.vr_state.vr[t];
901 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0];
903 /* Grab the vector address */
904 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
907 addr = (__force const void __user *)ea;
910 if (!access_ok(addr, 16)) {
911 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
912 " instr=%08x addr=%016lx\n",
913 smp_processor_id(), current->comm, current->pid,
914 regs->nip, instr, (unsigned long)addr);
918 /* Read the vector */
920 if ((unsigned long)addr & 0xfUL)
922 rc = __copy_from_user_inatomic(vbuf, addr, 16);
924 __get_user_atomic_128_aligned(vbuf, addr, rc);
926 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
927 " instr=%08x addr=%016lx\n",
928 smp_processor_id(), current->comm, current->pid,
929 regs->nip, instr, (unsigned long)addr);
933 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
934 " instr=%08x addr=%016lx\n",
935 smp_processor_id(), current->comm, current->pid, regs->nip,
936 instr, (unsigned long) addr);
938 /* Grab instruction "selector" */
939 sel = (instr >> 6) & 3;
942 * Check to make sure the facility is actually enabled. This
943 * could happen if we get a false positive hit.
945 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
946 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
949 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
951 if (!(msr & msr_mask)) {
952 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
953 " instr=%08x msr:%016lx\n",
954 smp_processor_id(), current->comm, current->pid,
955 regs->nip, instr, msr);
959 /* Do logging here before we modify sel based on endian */
962 PPC_WARN_EMULATED(lxvw4x, regs);
965 PPC_WARN_EMULATED(lxvh8x, regs);
968 PPC_WARN_EMULATED(lxvd2x, regs);
970 case 3: /* lxvb16x */
971 PPC_WARN_EMULATED(lxvb16x, regs);
975 #ifdef __LITTLE_ENDIAN__
977 * An LE kernel stores the vector in the task struct as an LE
978 * byte array (effectively swapping both the components and
979 * the content of the components). Those instructions expect
980 * the components to remain in ascending address order, so we
983 * If we are running a BE user space, the expectation is that
984 * of a simple memcpy, so forcing the emulation to look like
985 * a lxvb16x should do the trick.
992 for (i = 0; i < 4; i++)
993 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
996 for (i = 0; i < 8; i++)
997 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
1000 for (i = 0; i < 2; i++)
1001 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
1003 case 3: /* lxvb16x */
1004 for (i = 0; i < 16; i++)
1005 vdst[i] = vbuf[15-i];
1008 #else /* __LITTLE_ENDIAN__ */
1009 /* On a big endian kernel, a BE userspace only needs a memcpy */
1013 /* Otherwise, we need to swap the content of the components */
1015 case 0: /* lxvw4x */
1016 for (i = 0; i < 4; i++)
1017 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
1019 case 1: /* lxvh8x */
1020 for (i = 0; i < 8; i++)
1021 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
1023 case 2: /* lxvd2x */
1024 for (i = 0; i < 2; i++)
1025 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
1027 case 3: /* lxvb16x */
1028 memcpy(vdst, vbuf, 16);
1031 #endif /* !__LITTLE_ENDIAN__ */
1033 /* Go to next instruction */
1034 regs_add_return_ip(regs, 4);
1036 #endif /* CONFIG_VSX */
1038 DEFINE_INTERRUPT_HANDLER_ASYNC(handle_hmi_exception)
1040 struct pt_regs *old_regs;
1042 old_regs = set_irq_regs(regs);
1045 /* Real mode flagged P9 special emu is needed */
1046 if (local_paca->hmi_p9_special_emu) {
1047 local_paca->hmi_p9_special_emu = 0;
1050 * We don't want to take page faults while doing the
1051 * emulation, we just replay the instruction if necessary.
1053 pagefault_disable();
1054 p9_hmi_special_emu(regs);
1057 #endif /* CONFIG_VSX */
1059 if (ppc_md.handle_hmi_exception)
1060 ppc_md.handle_hmi_exception(regs);
1062 set_irq_regs(old_regs);
1065 DEFINE_INTERRUPT_HANDLER(unknown_exception)
1067 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1068 regs->nip, regs->msr, regs->trap);
1070 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1073 DEFINE_INTERRUPT_HANDLER_ASYNC(unknown_async_exception)
1075 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1076 regs->nip, regs->msr, regs->trap);
1078 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1081 DEFINE_INTERRUPT_HANDLER_NMI(unknown_nmi_exception)
1083 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1084 regs->nip, regs->msr, regs->trap);
1086 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1091 DEFINE_INTERRUPT_HANDLER(instruction_breakpoint_exception)
1093 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
1094 5, SIGTRAP) == NOTIFY_STOP)
1096 if (debugger_iabr_match(regs))
1098 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1101 DEFINE_INTERRUPT_HANDLER(RunModeException)
1103 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1106 DEFINE_INTERRUPT_HANDLER(single_step_exception)
1108 clear_single_step(regs);
1109 clear_br_trace(regs);
1111 if (kprobe_post_handler(regs))
1114 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1115 5, SIGTRAP) == NOTIFY_STOP)
1117 if (debugger_sstep(regs))
1120 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1124 * After we have successfully emulated an instruction, we have to
1125 * check if the instruction was being single-stepped, and if so,
1126 * pretend we got a single-step exception. This was pointed out
1127 * by Kumar Gala. -- paulus
1129 static void emulate_single_step(struct pt_regs *regs)
1131 if (single_stepping(regs))
1132 single_step_exception(regs);
1135 static inline int __parse_fpscr(unsigned long fpscr)
1137 int ret = FPE_FLTUNK;
1139 /* Invalid operation */
1140 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
1144 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
1148 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
1151 /* Divide by zero */
1152 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
1155 /* Inexact result */
1156 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
1162 static void parse_fpe(struct pt_regs *regs)
1166 flush_fp_to_thread(current);
1168 #ifdef CONFIG_PPC_FPU_REGS
1169 code = __parse_fpscr(current->thread.fp_state.fpscr);
1172 _exception(SIGFPE, regs, code, regs->nip);
1176 * Illegal instruction emulation support. Originally written to
1177 * provide the PVR to user applications using the mfspr rd, PVR.
1178 * Return non-zero if we can't emulate, or -EFAULT if the associated
1179 * memory access caused an access fault. Return zero on success.
1181 * There are a couple of ways to do this, either "decode" the instruction
1182 * or directly match lots of bits. In this case, matching lots of
1183 * bits is faster and easier.
1186 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
1188 u8 rT = (instword >> 21) & 0x1f;
1189 u8 rA = (instword >> 16) & 0x1f;
1190 u8 NB_RB = (instword >> 11) & 0x1f;
1195 /* Early out if we are an invalid form of lswx */
1196 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
1197 if ((rT == rA) || (rT == NB_RB))
1200 EA = (rA == 0) ? 0 : regs->gpr[rA];
1202 switch (instword & PPC_INST_STRING_MASK) {
1204 case PPC_INST_STSWX:
1206 num_bytes = regs->xer & 0x7f;
1209 case PPC_INST_STSWI:
1210 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
1216 while (num_bytes != 0)
1219 u32 shift = 8 * (3 - (pos & 0x3));
1221 /* if process is 32-bit, clear upper 32 bits of EA */
1222 if ((regs->msr & MSR_64BIT) == 0)
1225 switch ((instword & PPC_INST_STRING_MASK)) {
1228 if (get_user(val, (u8 __user *)EA))
1230 /* first time updating this reg,
1234 regs->gpr[rT] |= val << shift;
1236 case PPC_INST_STSWI:
1237 case PPC_INST_STSWX:
1238 val = regs->gpr[rT] >> shift;
1239 if (put_user(val, (u8 __user *)EA))
1243 /* move EA to next address */
1247 /* manage our position within the register */
1258 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
1263 ra = (instword >> 16) & 0x1f;
1264 rs = (instword >> 21) & 0x1f;
1266 tmp = regs->gpr[rs];
1267 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
1268 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
1269 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1270 regs->gpr[ra] = tmp;
1275 static int emulate_isel(struct pt_regs *regs, u32 instword)
1277 u8 rT = (instword >> 21) & 0x1f;
1278 u8 rA = (instword >> 16) & 0x1f;
1279 u8 rB = (instword >> 11) & 0x1f;
1280 u8 BC = (instword >> 6) & 0x1f;
1284 tmp = (rA == 0) ? 0 : regs->gpr[rA];
1285 bit = (regs->ccr >> (31 - BC)) & 0x1;
1287 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
1292 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1293 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
1295 /* If we're emulating a load/store in an active transaction, we cannot
1296 * emulate it as the kernel operates in transaction suspended context.
1297 * We need to abort the transaction. This creates a persistent TM
1298 * abort so tell the user what caused it with a new code.
1300 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1308 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1314 static int emulate_instruction(struct pt_regs *regs)
1319 if (!user_mode(regs))
1322 if (get_user(instword, (u32 __user *)(regs->nip)))
1325 /* Emulate the mfspr rD, PVR. */
1326 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1327 PPC_WARN_EMULATED(mfpvr, regs);
1328 rd = (instword >> 21) & 0x1f;
1329 regs->gpr[rd] = mfspr(SPRN_PVR);
1333 /* Emulating the dcba insn is just a no-op. */
1334 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1335 PPC_WARN_EMULATED(dcba, regs);
1339 /* Emulate the mcrxr insn. */
1340 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1341 int shift = (instword >> 21) & 0x1c;
1342 unsigned long msk = 0xf0000000UL >> shift;
1344 PPC_WARN_EMULATED(mcrxr, regs);
1345 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1346 regs->xer &= ~0xf0000000UL;
1350 /* Emulate load/store string insn. */
1351 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1352 if (tm_abort_check(regs,
1353 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1355 PPC_WARN_EMULATED(string, regs);
1356 return emulate_string_inst(regs, instword);
1359 /* Emulate the popcntb (Population Count Bytes) instruction. */
1360 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1361 PPC_WARN_EMULATED(popcntb, regs);
1362 return emulate_popcntb_inst(regs, instword);
1365 /* Emulate isel (Integer Select) instruction */
1366 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1367 PPC_WARN_EMULATED(isel, regs);
1368 return emulate_isel(regs, instword);
1371 /* Emulate sync instruction variants */
1372 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1373 PPC_WARN_EMULATED(sync, regs);
1374 asm volatile("sync");
1379 /* Emulate the mfspr rD, DSCR. */
1380 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1381 PPC_INST_MFSPR_DSCR_USER) ||
1382 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1383 PPC_INST_MFSPR_DSCR)) &&
1384 cpu_has_feature(CPU_FTR_DSCR)) {
1385 PPC_WARN_EMULATED(mfdscr, regs);
1386 rd = (instword >> 21) & 0x1f;
1387 regs->gpr[rd] = mfspr(SPRN_DSCR);
1390 /* Emulate the mtspr DSCR, rD. */
1391 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1392 PPC_INST_MTSPR_DSCR_USER) ||
1393 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1394 PPC_INST_MTSPR_DSCR)) &&
1395 cpu_has_feature(CPU_FTR_DSCR)) {
1396 PPC_WARN_EMULATED(mtdscr, regs);
1397 rd = (instword >> 21) & 0x1f;
1398 current->thread.dscr = regs->gpr[rd];
1399 current->thread.dscr_inherit = 1;
1400 mtspr(SPRN_DSCR, current->thread.dscr);
1408 int is_valid_bugaddr(unsigned long addr)
1410 return is_kernel_addr(addr);
1413 #ifdef CONFIG_MATH_EMULATION
1414 static int emulate_math(struct pt_regs *regs)
1418 ret = do_mathemu(regs);
1420 PPC_WARN_EMULATED(math, regs);
1424 emulate_single_step(regs);
1428 code = __parse_fpscr(current->thread.fp_state.fpscr);
1429 _exception(SIGFPE, regs, code, regs->nip);
1433 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1440 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1443 static void do_program_check(struct pt_regs *regs)
1445 unsigned int reason = get_reason(regs);
1447 /* We can now get here via a FP Unavailable exception if the core
1448 * has no FPU, in that case the reason flags will be 0 */
1450 if (reason & REASON_FP) {
1451 /* IEEE FP exception */
1455 if (reason & REASON_TRAP) {
1456 unsigned long bugaddr;
1457 /* Debugger is first in line to stop recursive faults in
1458 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1459 if (debugger_bpt(regs))
1462 if (kprobe_handler(regs))
1465 /* trap exception */
1466 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1470 bugaddr = regs->nip;
1472 * Fixup bugaddr for BUG_ON() in real mode
1474 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1475 bugaddr += PAGE_OFFSET;
1477 if (!(regs->msr & MSR_PR) && /* not user-mode */
1478 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1479 regs_add_return_ip(regs, 4);
1482 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1485 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1486 if (reason & REASON_TM) {
1487 /* This is a TM "Bad Thing Exception" program check.
1489 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1490 * transition in TM states.
1491 * - A trechkpt is attempted when transactional.
1492 * - A treclaim is attempted when non transactional.
1493 * - A tend is illegally attempted.
1494 * - writing a TM SPR when transactional.
1496 * If usermode caused this, it's done something illegal and
1497 * gets a SIGILL slap on the wrist. We call it an illegal
1498 * operand to distinguish from the instruction just being bad
1499 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1500 * illegal /placement/ of a valid instruction.
1502 if (user_mode(regs)) {
1503 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1506 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1507 "at %lx (msr 0x%lx) tm_scratch=%llx\n",
1508 regs->nip, regs->msr, get_paca()->tm_scratch);
1509 die("Unrecoverable exception", regs, SIGABRT);
1515 * If we took the program check in the kernel skip down to sending a
1516 * SIGILL. The subsequent cases all relate to emulating instructions
1517 * which we should only do for userspace. We also do not want to enable
1518 * interrupts for kernel faults because that might lead to further
1519 * faults, and loose the context of the original exception.
1521 if (!user_mode(regs))
1524 interrupt_cond_local_irq_enable(regs);
1526 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1527 * but there seems to be a hardware bug on the 405GP (RevD)
1528 * that means ESR is sometimes set incorrectly - either to
1529 * ESR_DST (!?) or 0. In the process of chasing this with the
1530 * hardware people - not sure if it can happen on any illegal
1531 * instruction or only on FP instructions, whether there is a
1532 * pattern to occurrences etc. -dgibson 31/Mar/2003
1534 if (!emulate_math(regs))
1537 /* Try to emulate it if we should. */
1538 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1539 switch (emulate_instruction(regs)) {
1541 regs_add_return_ip(regs, 4);
1542 emulate_single_step(regs);
1545 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1551 if (reason & REASON_PRIVILEGED)
1552 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1554 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1558 DEFINE_INTERRUPT_HANDLER(program_check_exception)
1560 do_program_check(regs);
1564 * This occurs when running in hypervisor mode on POWER6 or later
1565 * and an illegal instruction is encountered.
1567 DEFINE_INTERRUPT_HANDLER(emulation_assist_interrupt)
1569 regs_set_return_msr(regs, regs->msr | REASON_ILLEGAL);
1570 do_program_check(regs);
1573 DEFINE_INTERRUPT_HANDLER(alignment_exception)
1575 int sig, code, fixed = 0;
1576 unsigned long reason;
1578 interrupt_cond_local_irq_enable(regs);
1580 reason = get_reason(regs);
1581 if (reason & REASON_BOUNDARY) {
1587 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1590 /* we don't implement logging of alignment exceptions */
1591 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1592 fixed = fix_alignment(regs);
1595 /* skip over emulated instruction */
1596 regs_add_return_ip(regs, inst_length(reason));
1597 emulate_single_step(regs);
1601 /* Operand address was bad */
1602 if (fixed == -EFAULT) {
1610 if (user_mode(regs))
1611 _exception(sig, regs, code, regs->dar);
1613 bad_page_fault(regs, sig);
1616 DEFINE_INTERRUPT_HANDLER(stack_overflow_exception)
1618 die("Kernel stack overflow", regs, SIGSEGV);
1621 DEFINE_INTERRUPT_HANDLER(kernel_fp_unavailable_exception)
1623 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1624 "%lx at %lx\n", regs->trap, regs->nip);
1625 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1628 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_exception)
1630 if (user_mode(regs)) {
1631 /* A user program has executed an altivec instruction,
1632 but this kernel doesn't support altivec. */
1633 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1637 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1638 "%lx at %lx\n", regs->trap, regs->nip);
1639 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1642 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_exception)
1644 if (user_mode(regs)) {
1645 /* A user program has executed an vsx instruction,
1646 but this kernel doesn't support vsx. */
1647 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1651 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1652 "%lx at %lx\n", regs->trap, regs->nip);
1653 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1657 static void tm_unavailable(struct pt_regs *regs)
1659 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1660 if (user_mode(regs)) {
1661 current->thread.load_tm++;
1662 regs_set_return_msr(regs, regs->msr | MSR_TM);
1664 tm_restore_sprs(¤t->thread);
1668 pr_emerg("Unrecoverable TM Unavailable Exception "
1669 "%lx at %lx\n", regs->trap, regs->nip);
1670 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1673 DEFINE_INTERRUPT_HANDLER(facility_unavailable_exception)
1675 static char *facility_strings[] = {
1676 [FSCR_FP_LG] = "FPU",
1677 [FSCR_VECVSX_LG] = "VMX/VSX",
1678 [FSCR_DSCR_LG] = "DSCR",
1679 [FSCR_PM_LG] = "PMU SPRs",
1680 [FSCR_BHRB_LG] = "BHRB",
1681 [FSCR_TM_LG] = "TM",
1682 [FSCR_EBB_LG] = "EBB",
1683 [FSCR_TAR_LG] = "TAR",
1684 [FSCR_MSGP_LG] = "MSGP",
1685 [FSCR_SCV_LG] = "SCV",
1686 [FSCR_PREFIX_LG] = "PREFIX",
1688 char *facility = "unknown";
1694 hv = (TRAP(regs) == INTERRUPT_H_FAC_UNAVAIL);
1696 value = mfspr(SPRN_HFSCR);
1698 value = mfspr(SPRN_FSCR);
1700 status = value >> 56;
1701 if ((hv || status >= 2) &&
1702 (status < ARRAY_SIZE(facility_strings)) &&
1703 facility_strings[status])
1704 facility = facility_strings[status];
1706 /* We should not have taken this interrupt in kernel */
1707 if (!user_mode(regs)) {
1708 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1709 facility, status, regs->nip);
1710 die("Unexpected facility unavailable exception", regs, SIGABRT);
1713 interrupt_cond_local_irq_enable(regs);
1715 if (status == FSCR_DSCR_LG) {
1717 * User is accessing the DSCR register using the problem
1718 * state only SPR number (0x03) either through a mfspr or
1719 * a mtspr instruction. If it is a write attempt through
1720 * a mtspr, then we set the inherit bit. This also allows
1721 * the user to write or read the register directly in the
1722 * future by setting via the FSCR DSCR bit. But in case it
1723 * is a read DSCR attempt through a mfspr instruction, we
1724 * just emulate the instruction instead. This code path will
1725 * always emulate all the mfspr instructions till the user
1726 * has attempted at least one mtspr instruction. This way it
1727 * preserves the same behaviour when the user is accessing
1728 * the DSCR through privilege level only SPR number (0x11)
1729 * which is emulated through illegal instruction exception.
1730 * We always leave HFSCR DSCR set.
1732 if (get_user(instword, (u32 __user *)(regs->nip))) {
1733 pr_err("Failed to fetch the user instruction\n");
1737 /* Write into DSCR (mtspr 0x03, RS) */
1738 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1739 == PPC_INST_MTSPR_DSCR_USER) {
1740 rd = (instword >> 21) & 0x1f;
1741 current->thread.dscr = regs->gpr[rd];
1742 current->thread.dscr_inherit = 1;
1743 current->thread.fscr |= FSCR_DSCR;
1744 mtspr(SPRN_FSCR, current->thread.fscr);
1747 /* Read from DSCR (mfspr RT, 0x03) */
1748 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1749 == PPC_INST_MFSPR_DSCR_USER) {
1750 if (emulate_instruction(regs)) {
1751 pr_err("DSCR based mfspr emulation failed\n");
1754 regs_add_return_ip(regs, 4);
1755 emulate_single_step(regs);
1760 if (status == FSCR_TM_LG) {
1762 * If we're here then the hardware is TM aware because it
1763 * generated an exception with FSRM_TM set.
1765 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1766 * told us not to do TM, or the kernel is not built with TM
1769 * If both of those things are true, then userspace can spam the
1770 * console by triggering the printk() below just by continually
1771 * doing tbegin (or any TM instruction). So in that case just
1772 * send the process a SIGILL immediately.
1774 if (!cpu_has_feature(CPU_FTR_TM))
1777 tm_unavailable(regs);
1781 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1782 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1785 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1789 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1791 DEFINE_INTERRUPT_HANDLER(fp_unavailable_tm)
1793 /* Note: This does not handle any kind of FP laziness. */
1795 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1796 regs->nip, regs->msr);
1798 /* We can only have got here if the task started using FP after
1799 * beginning the transaction. So, the transactional regs are just a
1800 * copy of the checkpointed ones. But, we still need to recheckpoint
1801 * as we're enabling FP for the process; it will return, abort the
1802 * transaction, and probably retry but now with FP enabled. So the
1803 * checkpointed FP registers need to be loaded.
1805 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1808 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
1809 * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
1811 * At this point, ck{fp,vr}_state contains the exact values we want to
1815 /* Enable FP for the task: */
1816 current->thread.load_fp = 1;
1819 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
1821 tm_recheckpoint(¤t->thread);
1824 DEFINE_INTERRUPT_HANDLER(altivec_unavailable_tm)
1826 /* See the comments in fp_unavailable_tm(). This function operates
1830 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1832 regs->nip, regs->msr);
1833 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1834 current->thread.load_vec = 1;
1835 tm_recheckpoint(¤t->thread);
1836 current->thread.used_vr = 1;
1839 DEFINE_INTERRUPT_HANDLER(vsx_unavailable_tm)
1841 /* See the comments in fp_unavailable_tm(). This works similarly,
1842 * though we're loading both FP and VEC registers in here.
1844 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1845 * regs. Either way, set MSR_VSX.
1848 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1850 regs->nip, regs->msr);
1852 current->thread.used_vsr = 1;
1854 /* This reclaims FP and/or VR regs if they're already enabled */
1855 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1857 current->thread.load_vec = 1;
1858 current->thread.load_fp = 1;
1860 tm_recheckpoint(¤t->thread);
1862 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1865 DECLARE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi);
1866 DEFINE_INTERRUPT_HANDLER_NMI(performance_monitor_exception_nmi)
1868 __this_cpu_inc(irq_stat.pmu_irqs);
1876 DECLARE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async);
1877 DEFINE_INTERRUPT_HANDLER_ASYNC(performance_monitor_exception_async)
1879 __this_cpu_inc(irq_stat.pmu_irqs);
1884 DEFINE_INTERRUPT_HANDLER_RAW(performance_monitor_exception)
1887 * On 64-bit, if perf interrupts hit in a local_irq_disable
1888 * (soft-masked) region, we consider them as NMIs. This is required to
1889 * prevent hash faults on user addresses when reading callchains (and
1890 * looks better from an irq tracing perspective).
1892 if (IS_ENABLED(CONFIG_PPC64) && unlikely(arch_irq_disabled_regs(regs)))
1893 performance_monitor_exception_nmi(regs);
1895 performance_monitor_exception_async(regs);
1900 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1901 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1905 * Determine the cause of the debug event, clear the
1906 * event flags and send a trap to the handler. Torez
1908 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1909 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1910 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1911 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1913 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status,
1916 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1917 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1918 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status,
1921 } else if (debug_status & DBSR_IAC1) {
1922 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1923 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1924 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status,
1927 } else if (debug_status & DBSR_IAC2) {
1928 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1929 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status,
1932 } else if (debug_status & DBSR_IAC3) {
1933 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1934 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1935 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status,
1938 } else if (debug_status & DBSR_IAC4) {
1939 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1940 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status,
1945 * At the point this routine was called, the MSR(DE) was turned off.
1946 * Check all other debug flags and see if that bit needs to be turned
1949 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1950 current->thread.debug.dbcr1))
1951 regs_set_return_msr(regs, regs->msr | MSR_DE);
1953 /* Make sure the IDM flag is off */
1954 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1957 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1960 DEFINE_INTERRUPT_HANDLER(DebugException)
1962 unsigned long debug_status = regs->dsisr;
1964 current->thread.debug.dbsr = debug_status;
1966 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1967 * on server, it stops on the target of the branch. In order to simulate
1968 * the server behaviour, we thus restart right away with a single step
1969 * instead of stopping here when hitting a BT
1971 if (debug_status & DBSR_BT) {
1972 regs_set_return_msr(regs, regs->msr & ~MSR_DE);
1975 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1976 /* Clear the BT event */
1977 mtspr(SPRN_DBSR, DBSR_BT);
1979 /* Do the single step trick only when coming from userspace */
1980 if (user_mode(regs)) {
1981 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1982 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1983 regs_set_return_msr(regs, regs->msr | MSR_DE);
1987 if (kprobe_post_handler(regs))
1990 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1991 5, SIGTRAP) == NOTIFY_STOP) {
1994 if (debugger_sstep(regs))
1996 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1997 regs_set_return_msr(regs, regs->msr & ~MSR_DE);
1999 /* Disable instruction completion */
2000 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
2001 /* Clear the instruction completion event */
2002 mtspr(SPRN_DBSR, DBSR_IC);
2004 if (kprobe_post_handler(regs))
2007 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
2008 5, SIGTRAP) == NOTIFY_STOP) {
2012 if (debugger_sstep(regs))
2015 if (user_mode(regs)) {
2016 current->thread.debug.dbcr0 &= ~DBCR0_IC;
2017 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
2018 current->thread.debug.dbcr1))
2019 regs_set_return_msr(regs, regs->msr | MSR_DE);
2021 /* Make sure the IDM bit is off */
2022 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
2025 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
2027 handle_debug(regs, debug_status);
2029 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2031 #ifdef CONFIG_ALTIVEC
2032 DEFINE_INTERRUPT_HANDLER(altivec_assist_exception)
2036 if (!user_mode(regs)) {
2037 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
2038 " at %lx\n", regs->nip);
2039 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
2042 flush_altivec_to_thread(current);
2044 PPC_WARN_EMULATED(altivec, regs);
2045 err = emulate_altivec(regs);
2047 regs_add_return_ip(regs, 4); /* skip emulated instruction */
2048 emulate_single_step(regs);
2052 if (err == -EFAULT) {
2053 /* got an error reading the instruction */
2054 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2056 /* didn't recognize the instruction */
2057 /* XXX quick hack for now: set the non-Java bit in the VSCR */
2058 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
2059 "in %s at %lx\n", current->comm, regs->nip);
2060 current->thread.vr_state.vscr.u[3] |= 0x10000;
2063 #endif /* CONFIG_ALTIVEC */
2065 #ifdef CONFIG_FSL_BOOKE
2066 DEFINE_INTERRUPT_HANDLER(CacheLockingException)
2068 unsigned long error_code = regs->dsisr;
2070 /* We treat cache locking instructions from the user
2071 * as priv ops, in the future we could try to do
2074 if (error_code & (ESR_DLK|ESR_ILK))
2075 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
2078 #endif /* CONFIG_FSL_BOOKE */
2081 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointException)
2083 extern int do_spe_mathemu(struct pt_regs *regs);
2084 unsigned long spefscr;
2086 int code = FPE_FLTUNK;
2089 interrupt_cond_local_irq_enable(regs);
2091 flush_spe_to_thread(current);
2093 spefscr = current->thread.spefscr;
2094 fpexc_mode = current->thread.fpexc_mode;
2096 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
2099 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
2102 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
2104 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
2107 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
2110 err = do_spe_mathemu(regs);
2112 regs_add_return_ip(regs, 4); /* skip emulated instruction */
2113 emulate_single_step(regs);
2117 if (err == -EFAULT) {
2118 /* got an error reading the instruction */
2119 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2120 } else if (err == -EINVAL) {
2121 /* didn't recognize the instruction */
2122 printk(KERN_ERR "unrecognized spe instruction "
2123 "in %s at %lx\n", current->comm, regs->nip);
2125 _exception(SIGFPE, regs, code, regs->nip);
2131 DEFINE_INTERRUPT_HANDLER(SPEFloatingPointRoundException)
2133 extern int speround_handler(struct pt_regs *regs);
2136 interrupt_cond_local_irq_enable(regs);
2139 if (regs->msr & MSR_SPE)
2140 giveup_spe(current);
2143 regs_add_return_ip(regs, -4);
2144 err = speround_handler(regs);
2146 regs_add_return_ip(regs, 4); /* skip emulated instruction */
2147 emulate_single_step(regs);
2151 if (err == -EFAULT) {
2152 /* got an error reading the instruction */
2153 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2154 } else if (err == -EINVAL) {
2155 /* didn't recognize the instruction */
2156 printk(KERN_ERR "unrecognized spe instruction "
2157 "in %s at %lx\n", current->comm, regs->nip);
2159 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip);
2166 * We enter here if we get an unrecoverable exception, that is, one
2167 * that happened at a point where the RI (recoverable interrupt) bit
2168 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2169 * we therefore lost state by taking this exception.
2171 void __noreturn unrecoverable_exception(struct pt_regs *regs)
2173 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
2174 regs->trap, regs->nip, regs->msr);
2175 die("Unrecoverable exception", regs, SIGABRT);
2176 /* die() should not return */
2181 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2183 * Default handler for a Watchdog exception,
2184 * spins until a reboot occurs
2186 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
2188 /* Generic WatchdogHandler, implement your own */
2189 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
2193 DEFINE_INTERRUPT_HANDLER_NMI(WatchdogException)
2195 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
2196 WatchdogHandler(regs);
2202 * We enter here if we discover during exception entry that we are
2203 * running in supervisor mode with a userspace value in the stack pointer.
2205 DEFINE_INTERRUPT_HANDLER(kernel_bad_stack)
2207 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
2208 regs->gpr[1], regs->nip);
2209 die("Bad kernel stack pointer", regs, SIGABRT);
2212 void __init trap_init(void)
2217 #ifdef CONFIG_PPC_EMULATED_STATS
2219 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2221 struct ppc_emulated ppc_emulated = {
2222 #ifdef CONFIG_ALTIVEC
2223 WARN_EMULATED_SETUP(altivec),
2225 WARN_EMULATED_SETUP(dcba),
2226 WARN_EMULATED_SETUP(dcbz),
2227 WARN_EMULATED_SETUP(fp_pair),
2228 WARN_EMULATED_SETUP(isel),
2229 WARN_EMULATED_SETUP(mcrxr),
2230 WARN_EMULATED_SETUP(mfpvr),
2231 WARN_EMULATED_SETUP(multiple),
2232 WARN_EMULATED_SETUP(popcntb),
2233 WARN_EMULATED_SETUP(spe),
2234 WARN_EMULATED_SETUP(string),
2235 WARN_EMULATED_SETUP(sync),
2236 WARN_EMULATED_SETUP(unaligned),
2237 #ifdef CONFIG_MATH_EMULATION
2238 WARN_EMULATED_SETUP(math),
2241 WARN_EMULATED_SETUP(vsx),
2244 WARN_EMULATED_SETUP(mfdscr),
2245 WARN_EMULATED_SETUP(mtdscr),
2246 WARN_EMULATED_SETUP(lq_stq),
2247 WARN_EMULATED_SETUP(lxvw4x),
2248 WARN_EMULATED_SETUP(lxvh8x),
2249 WARN_EMULATED_SETUP(lxvd2x),
2250 WARN_EMULATED_SETUP(lxvb16x),
2254 u32 ppc_warn_emulated;
2256 void ppc_warn_emulated_print(const char *type)
2258 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
2262 static int __init ppc_warn_emulated_init(void)
2266 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
2268 dir = debugfs_create_dir("emulated_instructions",
2269 powerpc_debugfs_root);
2271 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated);
2273 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++)
2274 debugfs_create_u32(entries[i].name, 0644, dir,
2275 (u32 *)&entries[i].val.counter);
2280 device_initcall(ppc_warn_emulated_init);
2282 #endif /* CONFIG_PPC_EMULATED_STATS */