2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38 #include <linux/context_tracking.h>
40 #include <asm/emulated_ops.h>
41 #include <asm/pgtable.h>
42 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <sysdev/fsl_pci.h>
67 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
68 int (*__debugger)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
70 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
71 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
72 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
73 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
76 EXPORT_SYMBOL(__debugger);
77 EXPORT_SYMBOL(__debugger_ipi);
78 EXPORT_SYMBOL(__debugger_bpt);
79 EXPORT_SYMBOL(__debugger_sstep);
80 EXPORT_SYMBOL(__debugger_iabr_match);
81 EXPORT_SYMBOL(__debugger_break_match);
82 EXPORT_SYMBOL(__debugger_fault_handler);
85 /* Transactional Memory trap debug */
87 #define TM_DEBUG(x...) printk(KERN_INFO x)
89 #define TM_DEBUG(x...) do { } while(0)
93 * Trap & Exception support
96 #ifdef CONFIG_PMAC_BACKLIGHT
97 static void pmac_backlight_unblank(void)
99 mutex_lock(&pmac_backlight_mutex);
100 if (pmac_backlight) {
101 struct backlight_properties *props;
103 props = &pmac_backlight->props;
104 props->brightness = props->max_brightness;
105 props->power = FB_BLANK_UNBLANK;
106 backlight_update_status(pmac_backlight);
108 mutex_unlock(&pmac_backlight_mutex);
111 static inline void pmac_backlight_unblank(void) { }
114 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
115 static int die_owner = -1;
116 static unsigned int die_nest_count;
117 static int die_counter;
119 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
129 /* racy, but better than risking deadlock. */
130 raw_local_irq_save(flags);
131 cpu = smp_processor_id();
132 if (!arch_spin_trylock(&die_lock)) {
133 if (cpu == die_owner)
134 /* nested oops. should stop eventually */;
136 arch_spin_lock(&die_lock);
142 if (machine_is(powermac))
143 pmac_backlight_unblank();
147 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
152 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
157 /* Nest count reaches zero, release the lock. */
158 arch_spin_unlock(&die_lock);
159 raw_local_irq_restore(flags);
161 crash_fadump(regs, "die oops");
164 * A system reset (0x100) is a request to dump, so we always send
165 * it through the crashdump code.
167 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
171 * We aren't the primary crash CPU. We need to send it
172 * to a holding pattern to avoid it ending up in the panic
175 crash_kexec_secondary(regs);
182 * While our oops output is serialised by a spinlock, output
183 * from panic() called below can race and corrupt it. If we
184 * know we are going to panic, delay for 1 second so we have a
185 * chance to get clean backtraces from all CPUs that are oopsing.
187 if (in_interrupt() || panic_on_oops || !current->pid ||
188 is_global_init(current)) {
189 mdelay(MSEC_PER_SEC);
193 panic("Fatal exception in interrupt");
195 panic("Fatal exception");
199 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
201 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
202 #ifdef CONFIG_PREEMPT
206 printk("SMP NR_CPUS=%d ", NR_CPUS);
208 #ifdef CONFIG_DEBUG_PAGEALLOC
209 printk("DEBUG_PAGEALLOC ");
214 printk("%s\n", ppc_md.name ? ppc_md.name : "");
216 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
225 void die(const char *str, struct pt_regs *regs, long err)
227 unsigned long flags = oops_begin(regs);
229 if (__die(str, regs, err))
231 oops_end(flags, regs, err);
234 void user_single_step_siginfo(struct task_struct *tsk,
235 struct pt_regs *regs, siginfo_t *info)
237 memset(info, 0, sizeof(*info));
238 info->si_signo = SIGTRAP;
239 info->si_code = TRAP_TRACE;
240 info->si_addr = (void __user *)regs->nip;
243 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
246 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
247 "at %08lx nip %08lx lr %08lx code %x\n";
248 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
249 "at %016lx nip %016lx lr %016lx code %x\n";
251 if (!user_mode(regs)) {
252 die("Exception in kernel mode", regs, signr);
256 if (show_unhandled_signals && unhandled_signal(current, signr)) {
257 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
258 current->comm, current->pid, signr,
259 addr, regs->nip, regs->link, code);
262 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
265 current->thread.trap_nr = code;
266 memset(&info, 0, sizeof(info));
267 info.si_signo = signr;
269 info.si_addr = (void __user *) addr;
270 force_sig_info(signr, &info, current);
274 void system_reset_exception(struct pt_regs *regs)
276 /* See if any machine dependent calls */
277 if (ppc_md.system_reset_exception) {
278 if (ppc_md.system_reset_exception(regs))
282 die("System Reset", regs, SIGABRT);
284 /* Must die if the interrupt is not recoverable */
285 if (!(regs->msr & MSR_RI))
286 panic("Unrecoverable System Reset");
288 /* What should we do here? We could issue a shutdown or hard reset. */
293 * I/O accesses can cause machine checks on powermacs.
294 * Check if the NIP corresponds to the address of a sync
295 * instruction for which there is an entry in the exception
297 * Note that the 601 only takes a machine check on TEA
298 * (transfer error ack) signal assertion, and does not
299 * set any of the top 16 bits of SRR1.
302 static inline int check_io_access(struct pt_regs *regs)
305 unsigned long msr = regs->msr;
306 const struct exception_table_entry *entry;
307 unsigned int *nip = (unsigned int *)regs->nip;
309 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
310 && (entry = search_exception_tables(regs->nip)) != NULL) {
312 * Check that it's a sync instruction, or somewhere
313 * in the twi; isync; nop sequence that inb/inw/inl uses.
314 * As the address is in the exception table
315 * we should be able to read the instr there.
316 * For the debug message, we look at the preceding
319 if (*nip == 0x60000000) /* nop */
321 else if (*nip == 0x4c00012c) /* isync */
323 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
328 rb = (*nip >> 11) & 0x1f;
329 printk(KERN_DEBUG "%s bad port %lx at %p\n",
330 (*nip & 0x100)? "OUT to": "IN from",
331 regs->gpr[rb] - _IO_BASE, nip);
333 regs->nip = entry->fixup;
337 #endif /* CONFIG_PPC32 */
341 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
342 /* On 4xx, the reason for the machine check or program exception
344 #define get_reason(regs) ((regs)->dsisr)
345 #ifndef CONFIG_FSL_BOOKE
346 #define get_mc_reason(regs) ((regs)->dsisr)
348 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
350 #define REASON_FP ESR_FP
351 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
352 #define REASON_PRIVILEGED ESR_PPR
353 #define REASON_TRAP ESR_PTR
355 /* single-step stuff */
356 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
357 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
360 /* On non-4xx, the reason for the machine check or program
361 exception is in the MSR. */
362 #define get_reason(regs) ((regs)->msr)
363 #define get_mc_reason(regs) ((regs)->msr)
364 #define REASON_TM 0x200000
365 #define REASON_FP 0x100000
366 #define REASON_ILLEGAL 0x80000
367 #define REASON_PRIVILEGED 0x40000
368 #define REASON_TRAP 0x20000
370 #define single_stepping(regs) ((regs)->msr & MSR_SE)
371 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
374 #if defined(CONFIG_4xx)
375 int machine_check_4xx(struct pt_regs *regs)
377 unsigned long reason = get_mc_reason(regs);
379 if (reason & ESR_IMCP) {
380 printk("Instruction");
381 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
384 printk(" machine check in kernel mode.\n");
389 int machine_check_440A(struct pt_regs *regs)
391 unsigned long reason = get_mc_reason(regs);
393 printk("Machine check in kernel mode.\n");
394 if (reason & ESR_IMCP){
395 printk("Instruction Synchronous Machine Check exception\n");
396 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
399 u32 mcsr = mfspr(SPRN_MCSR);
401 printk("Instruction Read PLB Error\n");
403 printk("Data Read PLB Error\n");
405 printk("Data Write PLB Error\n");
406 if (mcsr & MCSR_TLBP)
407 printk("TLB Parity Error\n");
408 if (mcsr & MCSR_ICP){
409 flush_instruction_cache();
410 printk("I-Cache Parity Error\n");
412 if (mcsr & MCSR_DCSP)
413 printk("D-Cache Search Parity Error\n");
414 if (mcsr & MCSR_DCFP)
415 printk("D-Cache Flush Parity Error\n");
416 if (mcsr & MCSR_IMPE)
417 printk("Machine Check exception is imprecise\n");
420 mtspr(SPRN_MCSR, mcsr);
425 int machine_check_47x(struct pt_regs *regs)
427 unsigned long reason = get_mc_reason(regs);
430 printk(KERN_ERR "Machine check in kernel mode.\n");
431 if (reason & ESR_IMCP) {
433 "Instruction Synchronous Machine Check exception\n");
434 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
437 mcsr = mfspr(SPRN_MCSR);
439 printk(KERN_ERR "Instruction Read PLB Error\n");
441 printk(KERN_ERR "Data Read PLB Error\n");
443 printk(KERN_ERR "Data Write PLB Error\n");
444 if (mcsr & MCSR_TLBP)
445 printk(KERN_ERR "TLB Parity Error\n");
446 if (mcsr & MCSR_ICP) {
447 flush_instruction_cache();
448 printk(KERN_ERR "I-Cache Parity Error\n");
450 if (mcsr & MCSR_DCSP)
451 printk(KERN_ERR "D-Cache Search Parity Error\n");
452 if (mcsr & PPC47x_MCSR_GPR)
453 printk(KERN_ERR "GPR Parity Error\n");
454 if (mcsr & PPC47x_MCSR_FPR)
455 printk(KERN_ERR "FPR Parity Error\n");
456 if (mcsr & PPC47x_MCSR_IPR)
457 printk(KERN_ERR "Machine Check exception is imprecise\n");
460 mtspr(SPRN_MCSR, mcsr);
464 #elif defined(CONFIG_E500)
465 int machine_check_e500mc(struct pt_regs *regs)
467 unsigned long mcsr = mfspr(SPRN_MCSR);
468 unsigned long reason = mcsr;
471 if (reason & MCSR_LD) {
472 recoverable = fsl_rio_mcheck_exception(regs);
473 if (recoverable == 1)
477 printk("Machine check in kernel mode.\n");
478 printk("Caused by (from MCSR=%lx): ", reason);
480 if (reason & MCSR_MCP)
481 printk("Machine Check Signal\n");
483 if (reason & MCSR_ICPERR) {
484 printk("Instruction Cache Parity Error\n");
487 * This is recoverable by invalidating the i-cache.
489 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
490 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
494 * This will generally be accompanied by an instruction
495 * fetch error report -- only treat MCSR_IF as fatal
496 * if it wasn't due to an L1 parity error.
501 if (reason & MCSR_DCPERR_MC) {
502 printk("Data Cache Parity Error\n");
505 * In write shadow mode we auto-recover from the error, but it
506 * may still get logged and cause a machine check. We should
507 * only treat the non-write shadow case as non-recoverable.
509 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
513 if (reason & MCSR_L2MMU_MHIT) {
514 printk("Hit on multiple TLB entries\n");
518 if (reason & MCSR_NMI)
519 printk("Non-maskable interrupt\n");
521 if (reason & MCSR_IF) {
522 printk("Instruction Fetch Error Report\n");
526 if (reason & MCSR_LD) {
527 printk("Load Error Report\n");
531 if (reason & MCSR_ST) {
532 printk("Store Error Report\n");
536 if (reason & MCSR_LDG) {
537 printk("Guarded Load Error Report\n");
541 if (reason & MCSR_TLBSYNC)
542 printk("Simultaneous tlbsync operations\n");
544 if (reason & MCSR_BSL2_ERR) {
545 printk("Level 2 Cache Error\n");
549 if (reason & MCSR_MAV) {
552 addr = mfspr(SPRN_MCAR);
553 addr |= (u64)mfspr(SPRN_MCARU) << 32;
555 printk("Machine Check %s Address: %#llx\n",
556 reason & MCSR_MEA ? "Effective" : "Physical", addr);
560 mtspr(SPRN_MCSR, mcsr);
561 return mfspr(SPRN_MCSR) == 0 && recoverable;
564 int machine_check_e500(struct pt_regs *regs)
566 unsigned long reason = get_mc_reason(regs);
568 if (reason & MCSR_BUS_RBERR) {
569 if (fsl_rio_mcheck_exception(regs))
571 if (fsl_pci_mcheck_exception(regs))
575 printk("Machine check in kernel mode.\n");
576 printk("Caused by (from MCSR=%lx): ", reason);
578 if (reason & MCSR_MCP)
579 printk("Machine Check Signal\n");
580 if (reason & MCSR_ICPERR)
581 printk("Instruction Cache Parity Error\n");
582 if (reason & MCSR_DCP_PERR)
583 printk("Data Cache Push Parity Error\n");
584 if (reason & MCSR_DCPERR)
585 printk("Data Cache Parity Error\n");
586 if (reason & MCSR_BUS_IAERR)
587 printk("Bus - Instruction Address Error\n");
588 if (reason & MCSR_BUS_RAERR)
589 printk("Bus - Read Address Error\n");
590 if (reason & MCSR_BUS_WAERR)
591 printk("Bus - Write Address Error\n");
592 if (reason & MCSR_BUS_IBERR)
593 printk("Bus - Instruction Data Error\n");
594 if (reason & MCSR_BUS_RBERR)
595 printk("Bus - Read Data Bus Error\n");
596 if (reason & MCSR_BUS_WBERR)
597 printk("Bus - Read Data Bus Error\n");
598 if (reason & MCSR_BUS_IPERR)
599 printk("Bus - Instruction Parity Error\n");
600 if (reason & MCSR_BUS_RPERR)
601 printk("Bus - Read Parity Error\n");
606 int machine_check_generic(struct pt_regs *regs)
610 #elif defined(CONFIG_E200)
611 int machine_check_e200(struct pt_regs *regs)
613 unsigned long reason = get_mc_reason(regs);
615 printk("Machine check in kernel mode.\n");
616 printk("Caused by (from MCSR=%lx): ", reason);
618 if (reason & MCSR_MCP)
619 printk("Machine Check Signal\n");
620 if (reason & MCSR_CP_PERR)
621 printk("Cache Push Parity Error\n");
622 if (reason & MCSR_CPERR)
623 printk("Cache Parity Error\n");
624 if (reason & MCSR_EXCP_ERR)
625 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
626 if (reason & MCSR_BUS_IRERR)
627 printk("Bus - Read Bus Error on instruction fetch\n");
628 if (reason & MCSR_BUS_DRERR)
629 printk("Bus - Read Bus Error on data load\n");
630 if (reason & MCSR_BUS_WRERR)
631 printk("Bus - Write Bus Error on buffered store or cache line push\n");
636 int machine_check_generic(struct pt_regs *regs)
638 unsigned long reason = get_mc_reason(regs);
640 printk("Machine check in kernel mode.\n");
641 printk("Caused by (from SRR1=%lx): ", reason);
642 switch (reason & 0x601F0000) {
644 printk("Machine check signal\n");
646 case 0: /* for 601 */
648 case 0x140000: /* 7450 MSS error and TEA */
649 printk("Transfer error ack signal\n");
652 printk("Data parity error signal\n");
655 printk("Address parity error signal\n");
658 printk("L1 Data Cache error\n");
661 printk("L1 Instruction Cache error\n");
664 printk("L2 data cache parity error\n");
667 printk("Unknown values in msr\n");
671 #endif /* everything else */
673 void machine_check_exception(struct pt_regs *regs)
675 enum ctx_state prev_state = exception_enter();
678 __get_cpu_var(irq_stat).mce_exceptions++;
680 /* See if any machine dependent calls. In theory, we would want
681 * to call the CPU first, and call the ppc_md. one if the CPU
682 * one returns a positive number. However there is existing code
683 * that assumes the board gets a first chance, so let's keep it
684 * that way for now and fix things later. --BenH.
686 if (ppc_md.machine_check_exception)
687 recover = ppc_md.machine_check_exception(regs);
688 else if (cur_cpu_spec->machine_check)
689 recover = cur_cpu_spec->machine_check(regs);
694 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
695 /* the qspan pci read routines can cause machine checks -- Cort
697 * yuck !!! that totally needs to go away ! There are better ways
698 * to deal with that than having a wart in the mcheck handler.
701 bad_page_fault(regs, regs->dar, SIGBUS);
705 if (debugger_fault_handler(regs))
708 if (check_io_access(regs))
711 die("Machine check", regs, SIGBUS);
713 /* Must die if the interrupt is not recoverable */
714 if (!(regs->msr & MSR_RI))
715 panic("Unrecoverable Machine check");
718 exception_exit(prev_state);
721 void SMIException(struct pt_regs *regs)
723 die("System Management Interrupt", regs, SIGABRT);
726 void unknown_exception(struct pt_regs *regs)
728 enum ctx_state prev_state = exception_enter();
730 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
731 regs->nip, regs->msr, regs->trap);
733 _exception(SIGTRAP, regs, 0, 0);
735 exception_exit(prev_state);
738 void instruction_breakpoint_exception(struct pt_regs *regs)
740 enum ctx_state prev_state = exception_enter();
742 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
743 5, SIGTRAP) == NOTIFY_STOP)
745 if (debugger_iabr_match(regs))
747 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
750 exception_exit(prev_state);
753 void RunModeException(struct pt_regs *regs)
755 _exception(SIGTRAP, regs, 0, 0);
758 void __kprobes single_step_exception(struct pt_regs *regs)
760 enum ctx_state prev_state = exception_enter();
762 clear_single_step(regs);
764 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
765 5, SIGTRAP) == NOTIFY_STOP)
767 if (debugger_sstep(regs))
770 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
773 exception_exit(prev_state);
777 * After we have successfully emulated an instruction, we have to
778 * check if the instruction was being single-stepped, and if so,
779 * pretend we got a single-step exception. This was pointed out
780 * by Kumar Gala. -- paulus
782 static void emulate_single_step(struct pt_regs *regs)
784 if (single_stepping(regs))
785 single_step_exception(regs);
788 static inline int __parse_fpscr(unsigned long fpscr)
792 /* Invalid operation */
793 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
797 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
801 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
805 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
809 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
815 static void parse_fpe(struct pt_regs *regs)
819 flush_fp_to_thread(current);
821 code = __parse_fpscr(current->thread.fpscr.val);
823 _exception(SIGFPE, regs, code, regs->nip);
827 * Illegal instruction emulation support. Originally written to
828 * provide the PVR to user applications using the mfspr rd, PVR.
829 * Return non-zero if we can't emulate, or -EFAULT if the associated
830 * memory access caused an access fault. Return zero on success.
832 * There are a couple of ways to do this, either "decode" the instruction
833 * or directly match lots of bits. In this case, matching lots of
834 * bits is faster and easier.
837 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
839 u8 rT = (instword >> 21) & 0x1f;
840 u8 rA = (instword >> 16) & 0x1f;
841 u8 NB_RB = (instword >> 11) & 0x1f;
846 /* Early out if we are an invalid form of lswx */
847 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
848 if ((rT == rA) || (rT == NB_RB))
851 EA = (rA == 0) ? 0 : regs->gpr[rA];
853 switch (instword & PPC_INST_STRING_MASK) {
857 num_bytes = regs->xer & 0x7f;
861 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
867 while (num_bytes != 0)
870 u32 shift = 8 * (3 - (pos & 0x3));
872 /* if process is 32-bit, clear upper 32 bits of EA */
873 if ((regs->msr & MSR_64BIT) == 0)
876 switch ((instword & PPC_INST_STRING_MASK)) {
879 if (get_user(val, (u8 __user *)EA))
881 /* first time updating this reg,
885 regs->gpr[rT] |= val << shift;
889 val = regs->gpr[rT] >> shift;
890 if (put_user(val, (u8 __user *)EA))
894 /* move EA to next address */
898 /* manage our position within the register */
909 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
914 ra = (instword >> 16) & 0x1f;
915 rs = (instword >> 21) & 0x1f;
918 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
919 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
920 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
926 static int emulate_isel(struct pt_regs *regs, u32 instword)
928 u8 rT = (instword >> 21) & 0x1f;
929 u8 rA = (instword >> 16) & 0x1f;
930 u8 rB = (instword >> 11) & 0x1f;
931 u8 BC = (instword >> 6) & 0x1f;
935 tmp = (rA == 0) ? 0 : regs->gpr[rA];
936 bit = (regs->ccr >> (31 - BC)) & 0x1;
938 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
943 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
944 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
946 /* If we're emulating a load/store in an active transaction, we cannot
947 * emulate it as the kernel operates in transaction suspended context.
948 * We need to abort the transaction. This creates a persistent TM
949 * abort so tell the user what caused it with a new code.
951 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
959 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
965 static int emulate_instruction(struct pt_regs *regs)
970 if (!user_mode(regs) || (regs->msr & MSR_LE))
972 CHECK_FULL_REGS(regs);
974 if (get_user(instword, (u32 __user *)(regs->nip)))
977 /* Emulate the mfspr rD, PVR. */
978 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
979 PPC_WARN_EMULATED(mfpvr, regs);
980 rd = (instword >> 21) & 0x1f;
981 regs->gpr[rd] = mfspr(SPRN_PVR);
985 /* Emulating the dcba insn is just a no-op. */
986 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
987 PPC_WARN_EMULATED(dcba, regs);
991 /* Emulate the mcrxr insn. */
992 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
993 int shift = (instword >> 21) & 0x1c;
994 unsigned long msk = 0xf0000000UL >> shift;
996 PPC_WARN_EMULATED(mcrxr, regs);
997 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
998 regs->xer &= ~0xf0000000UL;
1002 /* Emulate load/store string insn. */
1003 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1004 if (tm_abort_check(regs,
1005 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1007 PPC_WARN_EMULATED(string, regs);
1008 return emulate_string_inst(regs, instword);
1011 /* Emulate the popcntb (Population Count Bytes) instruction. */
1012 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1013 PPC_WARN_EMULATED(popcntb, regs);
1014 return emulate_popcntb_inst(regs, instword);
1017 /* Emulate isel (Integer Select) instruction */
1018 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1019 PPC_WARN_EMULATED(isel, regs);
1020 return emulate_isel(regs, instword);
1024 /* Emulate the mfspr rD, DSCR. */
1025 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1026 PPC_INST_MFSPR_DSCR_USER) ||
1027 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1028 PPC_INST_MFSPR_DSCR)) &&
1029 cpu_has_feature(CPU_FTR_DSCR)) {
1030 PPC_WARN_EMULATED(mfdscr, regs);
1031 rd = (instword >> 21) & 0x1f;
1032 regs->gpr[rd] = mfspr(SPRN_DSCR);
1035 /* Emulate the mtspr DSCR, rD. */
1036 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1037 PPC_INST_MTSPR_DSCR_USER) ||
1038 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1039 PPC_INST_MTSPR_DSCR)) &&
1040 cpu_has_feature(CPU_FTR_DSCR)) {
1041 PPC_WARN_EMULATED(mtdscr, regs);
1042 rd = (instword >> 21) & 0x1f;
1043 current->thread.dscr = regs->gpr[rd];
1044 current->thread.dscr_inherit = 1;
1045 mtspr(SPRN_DSCR, current->thread.dscr);
1053 int is_valid_bugaddr(unsigned long addr)
1055 return is_kernel_addr(addr);
1058 void __kprobes program_check_exception(struct pt_regs *regs)
1060 enum ctx_state prev_state = exception_enter();
1061 unsigned int reason = get_reason(regs);
1062 extern int do_mathemu(struct pt_regs *regs);
1064 /* We can now get here via a FP Unavailable exception if the core
1065 * has no FPU, in that case the reason flags will be 0 */
1067 if (reason & REASON_FP) {
1068 /* IEEE FP exception */
1072 if (reason & REASON_TRAP) {
1073 /* Debugger is first in line to stop recursive faults in
1074 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1075 if (debugger_bpt(regs))
1078 /* trap exception */
1079 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1083 if (!(regs->msr & MSR_PR) && /* not user-mode */
1084 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1088 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1091 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1092 if (reason & REASON_TM) {
1093 /* This is a TM "Bad Thing Exception" program check.
1095 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1096 * transition in TM states.
1097 * - A trechkpt is attempted when transactional.
1098 * - A treclaim is attempted when non transactional.
1099 * - A tend is illegally attempted.
1100 * - writing a TM SPR when transactional.
1102 if (!user_mode(regs) &&
1103 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1107 /* If usermode caused this, it's done something illegal and
1108 * gets a SIGILL slap on the wrist. We call it an illegal
1109 * operand to distinguish from the instruction just being bad
1110 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1111 * illegal /placement/ of a valid instruction.
1113 if (user_mode(regs)) {
1114 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1117 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1118 "at %lx (msr 0x%x)\n", regs->nip, reason);
1119 die("Unrecoverable exception", regs, SIGABRT);
1124 /* We restore the interrupt state now */
1125 if (!arch_irq_disabled_regs(regs))
1128 #ifdef CONFIG_MATH_EMULATION
1129 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1130 * but there seems to be a hardware bug on the 405GP (RevD)
1131 * that means ESR is sometimes set incorrectly - either to
1132 * ESR_DST (!?) or 0. In the process of chasing this with the
1133 * hardware people - not sure if it can happen on any illegal
1134 * instruction or only on FP instructions, whether there is a
1135 * pattern to occurrences etc. -dgibson 31/Mar/2003
1137 switch (do_mathemu(regs)) {
1139 emulate_single_step(regs);
1143 code = __parse_fpscr(current->thread.fpscr.val);
1144 _exception(SIGFPE, regs, code, regs->nip);
1148 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1151 /* fall through on any other errors */
1152 #endif /* CONFIG_MATH_EMULATION */
1154 /* Try to emulate it if we should. */
1155 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1156 switch (emulate_instruction(regs)) {
1159 emulate_single_step(regs);
1162 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1167 if (reason & REASON_PRIVILEGED)
1168 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1170 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1173 exception_exit(prev_state);
1177 * This occurs when running in hypervisor mode on POWER6 or later
1178 * and an illegal instruction is encountered.
1180 void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
1182 regs->msr |= REASON_ILLEGAL;
1183 program_check_exception(regs);
1186 void alignment_exception(struct pt_regs *regs)
1188 enum ctx_state prev_state = exception_enter();
1189 int sig, code, fixed = 0;
1191 /* We restore the interrupt state now */
1192 if (!arch_irq_disabled_regs(regs))
1195 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1198 /* we don't implement logging of alignment exceptions */
1199 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1200 fixed = fix_alignment(regs);
1203 regs->nip += 4; /* skip over emulated instruction */
1204 emulate_single_step(regs);
1208 /* Operand address was bad */
1209 if (fixed == -EFAULT) {
1216 if (user_mode(regs))
1217 _exception(sig, regs, code, regs->dar);
1219 bad_page_fault(regs, regs->dar, sig);
1222 exception_exit(prev_state);
1225 void StackOverflow(struct pt_regs *regs)
1227 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1228 current, regs->gpr[1]);
1231 panic("kernel stack overflow");
1234 void nonrecoverable_exception(struct pt_regs *regs)
1236 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1237 regs->nip, regs->msr);
1239 die("nonrecoverable exception", regs, SIGKILL);
1242 void trace_syscall(struct pt_regs *regs)
1244 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1245 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1246 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1249 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1251 enum ctx_state prev_state = exception_enter();
1253 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1254 "%lx at %lx\n", regs->trap, regs->nip);
1255 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1257 exception_exit(prev_state);
1260 void altivec_unavailable_exception(struct pt_regs *regs)
1262 enum ctx_state prev_state = exception_enter();
1264 if (user_mode(regs)) {
1265 /* A user program has executed an altivec instruction,
1266 but this kernel doesn't support altivec. */
1267 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1271 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1272 "%lx at %lx\n", regs->trap, regs->nip);
1273 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1276 exception_exit(prev_state);
1279 void vsx_unavailable_exception(struct pt_regs *regs)
1281 if (user_mode(regs)) {
1282 /* A user program has executed an vsx instruction,
1283 but this kernel doesn't support vsx. */
1284 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1288 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1289 "%lx at %lx\n", regs->trap, regs->nip);
1290 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1293 void facility_unavailable_exception(struct pt_regs *regs)
1295 static char *facility_strings[] = {
1306 char *facility, *prefix;
1309 if (regs->trap == 0xf60) {
1310 value = mfspr(SPRN_FSCR);
1313 value = mfspr(SPRN_HFSCR);
1314 prefix = "Hypervisor ";
1317 value = value >> 56;
1319 /* We restore the interrupt state now */
1320 if (!arch_irq_disabled_regs(regs))
1323 if (value < ARRAY_SIZE(facility_strings))
1324 facility = facility_strings[value];
1326 facility = "unknown";
1328 pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
1329 prefix, facility, regs->nip, regs->msr);
1331 if (user_mode(regs)) {
1332 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1336 die("Unexpected facility unavailable exception", regs, SIGABRT);
1339 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1341 extern void do_load_up_fpu(struct pt_regs *regs);
1343 void fp_unavailable_tm(struct pt_regs *regs)
1345 /* Note: This does not handle any kind of FP laziness. */
1347 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1348 regs->nip, regs->msr);
1351 /* We can only have got here if the task started using FP after
1352 * beginning the transaction. So, the transactional regs are just a
1353 * copy of the checkpointed ones. But, we still need to recheckpoint
1354 * as we're enabling FP for the process; it will return, abort the
1355 * transaction, and probably retry but now with FP enabled. So the
1356 * checkpointed FP registers need to be loaded.
1358 tm_reclaim(¤t->thread, current->thread.regs->msr,
1360 /* Reclaim didn't save out any FPRs to transact_fprs. */
1362 /* Enable FP for the task: */
1363 regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1365 /* This loads and recheckpoints the FP registers from
1366 * thread.fpr[]. They will remain in registers after the
1367 * checkpoint so we don't need to reload them after.
1369 tm_recheckpoint(¤t->thread, regs->msr);
1372 #ifdef CONFIG_ALTIVEC
1373 extern void do_load_up_altivec(struct pt_regs *regs);
1375 void altivec_unavailable_tm(struct pt_regs *regs)
1377 /* See the comments in fp_unavailable_tm(). This function operates
1381 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1383 regs->nip, regs->msr);
1385 tm_reclaim(¤t->thread, current->thread.regs->msr,
1387 regs->msr |= MSR_VEC;
1388 tm_recheckpoint(¤t->thread, regs->msr);
1389 current->thread.used_vr = 1;
1394 void vsx_unavailable_tm(struct pt_regs *regs)
1396 /* See the comments in fp_unavailable_tm(). This works similarly,
1397 * though we're loading both FP and VEC registers in here.
1399 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1400 * regs. Either way, set MSR_VSX.
1403 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1405 regs->nip, regs->msr);
1408 /* This reclaims FP and/or VR regs if they're already enabled */
1409 tm_reclaim(¤t->thread, current->thread.regs->msr,
1412 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1414 /* This loads & recheckpoints FP and VRs. */
1415 tm_recheckpoint(¤t->thread, regs->msr);
1416 current->thread.used_vsr = 1;
1419 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1421 void performance_monitor_exception(struct pt_regs *regs)
1423 __get_cpu_var(irq_stat).pmu_irqs++;
1429 void SoftwareEmulation(struct pt_regs *regs)
1431 extern int do_mathemu(struct pt_regs *);
1432 #if defined(CONFIG_MATH_EMULATION)
1436 CHECK_FULL_REGS(regs);
1438 if (!user_mode(regs)) {
1440 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1443 #ifdef CONFIG_MATH_EMULATION
1444 errcode = do_mathemu(regs);
1446 PPC_WARN_EMULATED(math, regs);
1450 emulate_single_step(regs);
1454 code = __parse_fpscr(current->thread.fpscr.val);
1455 _exception(SIGFPE, regs, code, regs->nip);
1459 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1462 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1466 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1469 #endif /* CONFIG_8xx */
1471 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1472 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1476 * Determine the cause of the debug event, clear the
1477 * event flags and send a trap to the handler. Torez
1479 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1480 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1481 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1482 current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1484 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1487 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1488 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1489 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1492 } else if (debug_status & DBSR_IAC1) {
1493 current->thread.dbcr0 &= ~DBCR0_IAC1;
1494 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1495 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1498 } else if (debug_status & DBSR_IAC2) {
1499 current->thread.dbcr0 &= ~DBCR0_IAC2;
1500 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1503 } else if (debug_status & DBSR_IAC3) {
1504 current->thread.dbcr0 &= ~DBCR0_IAC3;
1505 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1506 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1509 } else if (debug_status & DBSR_IAC4) {
1510 current->thread.dbcr0 &= ~DBCR0_IAC4;
1511 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1516 * At the point this routine was called, the MSR(DE) was turned off.
1517 * Check all other debug flags and see if that bit needs to be turned
1520 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1521 regs->msr |= MSR_DE;
1523 /* Make sure the IDM flag is off */
1524 current->thread.dbcr0 &= ~DBCR0_IDM;
1527 mtspr(SPRN_DBCR0, current->thread.dbcr0);
1530 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1532 current->thread.dbsr = debug_status;
1534 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1535 * on server, it stops on the target of the branch. In order to simulate
1536 * the server behaviour, we thus restart right away with a single step
1537 * instead of stopping here when hitting a BT
1539 if (debug_status & DBSR_BT) {
1540 regs->msr &= ~MSR_DE;
1543 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1544 /* Clear the BT event */
1545 mtspr(SPRN_DBSR, DBSR_BT);
1547 /* Do the single step trick only when coming from userspace */
1548 if (user_mode(regs)) {
1549 current->thread.dbcr0 &= ~DBCR0_BT;
1550 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1551 regs->msr |= MSR_DE;
1555 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1556 5, SIGTRAP) == NOTIFY_STOP) {
1559 if (debugger_sstep(regs))
1561 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1562 regs->msr &= ~MSR_DE;
1564 /* Disable instruction completion */
1565 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1566 /* Clear the instruction completion event */
1567 mtspr(SPRN_DBSR, DBSR_IC);
1569 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1570 5, SIGTRAP) == NOTIFY_STOP) {
1574 if (debugger_sstep(regs))
1577 if (user_mode(regs)) {
1578 current->thread.dbcr0 &= ~DBCR0_IC;
1579 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1580 current->thread.dbcr1))
1581 regs->msr |= MSR_DE;
1583 /* Make sure the IDM bit is off */
1584 current->thread.dbcr0 &= ~DBCR0_IDM;
1587 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1589 handle_debug(regs, debug_status);
1591 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1593 #if !defined(CONFIG_TAU_INT)
1594 void TAUException(struct pt_regs *regs)
1596 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1597 regs->nip, regs->msr, regs->trap, print_tainted());
1599 #endif /* CONFIG_INT_TAU */
1601 #ifdef CONFIG_ALTIVEC
1602 void altivec_assist_exception(struct pt_regs *regs)
1606 if (!user_mode(regs)) {
1607 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1608 " at %lx\n", regs->nip);
1609 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1612 flush_altivec_to_thread(current);
1614 PPC_WARN_EMULATED(altivec, regs);
1615 err = emulate_altivec(regs);
1617 regs->nip += 4; /* skip emulated instruction */
1618 emulate_single_step(regs);
1622 if (err == -EFAULT) {
1623 /* got an error reading the instruction */
1624 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1626 /* didn't recognize the instruction */
1627 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1628 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1629 "in %s at %lx\n", current->comm, regs->nip);
1630 current->thread.vscr.u[3] |= 0x10000;
1633 #endif /* CONFIG_ALTIVEC */
1636 void vsx_assist_exception(struct pt_regs *regs)
1638 if (!user_mode(regs)) {
1639 printk(KERN_EMERG "VSX assist exception in kernel mode"
1640 " at %lx\n", regs->nip);
1641 die("Kernel VSX assist exception", regs, SIGILL);
1644 flush_vsx_to_thread(current);
1645 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1646 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1648 #endif /* CONFIG_VSX */
1650 #ifdef CONFIG_FSL_BOOKE
1651 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1652 unsigned long error_code)
1654 /* We treat cache locking instructions from the user
1655 * as priv ops, in the future we could try to do
1658 if (error_code & (ESR_DLK|ESR_ILK))
1659 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1662 #endif /* CONFIG_FSL_BOOKE */
1665 void SPEFloatingPointException(struct pt_regs *regs)
1667 extern int do_spe_mathemu(struct pt_regs *regs);
1668 unsigned long spefscr;
1673 flush_spe_to_thread(current);
1675 spefscr = current->thread.spefscr;
1676 fpexc_mode = current->thread.fpexc_mode;
1678 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1681 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1684 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1686 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1689 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1692 err = do_spe_mathemu(regs);
1694 regs->nip += 4; /* skip emulated instruction */
1695 emulate_single_step(regs);
1699 if (err == -EFAULT) {
1700 /* got an error reading the instruction */
1701 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1702 } else if (err == -EINVAL) {
1703 /* didn't recognize the instruction */
1704 printk(KERN_ERR "unrecognized spe instruction "
1705 "in %s at %lx\n", current->comm, regs->nip);
1707 _exception(SIGFPE, regs, code, regs->nip);
1713 void SPEFloatingPointRoundException(struct pt_regs *regs)
1715 extern int speround_handler(struct pt_regs *regs);
1719 if (regs->msr & MSR_SPE)
1720 giveup_spe(current);
1724 err = speround_handler(regs);
1726 regs->nip += 4; /* skip emulated instruction */
1727 emulate_single_step(regs);
1731 if (err == -EFAULT) {
1732 /* got an error reading the instruction */
1733 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1734 } else if (err == -EINVAL) {
1735 /* didn't recognize the instruction */
1736 printk(KERN_ERR "unrecognized spe instruction "
1737 "in %s at %lx\n", current->comm, regs->nip);
1739 _exception(SIGFPE, regs, 0, regs->nip);
1746 * We enter here if we get an unrecoverable exception, that is, one
1747 * that happened at a point where the RI (recoverable interrupt) bit
1748 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1749 * we therefore lost state by taking this exception.
1751 void unrecoverable_exception(struct pt_regs *regs)
1753 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1754 regs->trap, regs->nip);
1755 die("Unrecoverable exception", regs, SIGABRT);
1758 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1760 * Default handler for a Watchdog exception,
1761 * spins until a reboot occurs
1763 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1765 /* Generic WatchdogHandler, implement your own */
1766 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1770 void WatchdogException(struct pt_regs *regs)
1772 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1773 WatchdogHandler(regs);
1778 * We enter here if we discover during exception entry that we are
1779 * running in supervisor mode with a userspace value in the stack pointer.
1781 void kernel_bad_stack(struct pt_regs *regs)
1783 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1784 regs->gpr[1], regs->nip);
1785 die("Bad kernel stack pointer", regs, SIGABRT);
1788 void __init trap_init(void)
1793 #ifdef CONFIG_PPC_EMULATED_STATS
1795 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1797 struct ppc_emulated ppc_emulated = {
1798 #ifdef CONFIG_ALTIVEC
1799 WARN_EMULATED_SETUP(altivec),
1801 WARN_EMULATED_SETUP(dcba),
1802 WARN_EMULATED_SETUP(dcbz),
1803 WARN_EMULATED_SETUP(fp_pair),
1804 WARN_EMULATED_SETUP(isel),
1805 WARN_EMULATED_SETUP(mcrxr),
1806 WARN_EMULATED_SETUP(mfpvr),
1807 WARN_EMULATED_SETUP(multiple),
1808 WARN_EMULATED_SETUP(popcntb),
1809 WARN_EMULATED_SETUP(spe),
1810 WARN_EMULATED_SETUP(string),
1811 WARN_EMULATED_SETUP(unaligned),
1812 #ifdef CONFIG_MATH_EMULATION
1813 WARN_EMULATED_SETUP(math),
1816 WARN_EMULATED_SETUP(vsx),
1819 WARN_EMULATED_SETUP(mfdscr),
1820 WARN_EMULATED_SETUP(mtdscr),
1824 u32 ppc_warn_emulated;
1826 void ppc_warn_emulated_print(const char *type)
1828 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1832 static int __init ppc_warn_emulated_init(void)
1834 struct dentry *dir, *d;
1836 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1838 if (!powerpc_debugfs_root)
1841 dir = debugfs_create_dir("emulated_instructions",
1842 powerpc_debugfs_root);
1846 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1847 &ppc_warn_emulated);
1851 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1852 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1853 (u32 *)&entries[i].val.counter);
1861 debugfs_remove_recursive(dir);
1865 device_initcall(ppc_warn_emulated_init);
1867 #endif /* CONFIG_PPC_EMULATED_STATS */