1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
6 * deal of code from the sparc and intel versions.
8 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and
11 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/sched/mm.h>
19 #include <linux/sched/task_stack.h>
20 #include <linux/sched/topology.h>
21 #include <linux/smp.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/init.h>
25 #include <linux/spinlock.h>
26 #include <linux/cache.h>
27 #include <linux/err.h>
28 #include <linux/device.h>
29 #include <linux/cpu.h>
30 #include <linux/notifier.h>
31 #include <linux/topology.h>
32 #include <linux/profile.h>
33 #include <linux/processor.h>
34 #include <linux/random.h>
35 #include <linux/stackprotector.h>
36 #include <linux/pgtable.h>
37 #include <linux/clockchips.h>
39 #include <asm/ptrace.h>
40 #include <linux/atomic.h>
42 #include <asm/hw_irq.h>
43 #include <asm/kvm_ppc.h>
44 #include <asm/dbell.h>
49 #include <asm/machdep.h>
50 #include <asm/cputhreads.h>
51 #include <asm/cputable.h>
53 #include <asm/vdso_datapage.h>
58 #include <asm/debug.h>
59 #include <asm/kexec.h>
60 #include <asm/asm-prototypes.h>
61 #include <asm/cpu_has_feature.h>
62 #include <asm/ftrace.h>
67 #define DBG(fmt...) udbg_printf(fmt)
72 #ifdef CONFIG_HOTPLUG_CPU
73 /* State of each CPU during hotplug phases */
74 static DEFINE_PER_CPU(int, cpu_state) = { 0 };
77 struct task_struct *secondary_current;
79 bool coregroup_enabled;
80 bool thread_group_shares_l2;
81 bool thread_group_shares_l3;
83 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
84 DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map);
85 DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map);
86 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
87 static DEFINE_PER_CPU(cpumask_var_t, cpu_coregroup_map);
89 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
90 EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
92 EXPORT_SYMBOL_GPL(has_big_cores);
95 #ifdef CONFIG_SCHED_SMT
103 #define MAX_THREAD_LIST_SIZE 8
104 #define THREAD_GROUP_SHARE_L1 1
105 #define THREAD_GROUP_SHARE_L2_L3 2
106 struct thread_groups {
107 unsigned int property;
108 unsigned int nr_groups;
109 unsigned int threads_per_group;
110 unsigned int thread_list[MAX_THREAD_LIST_SIZE];
113 /* Maximum number of properties that groups of threads within a core can share */
114 #define MAX_THREAD_GROUP_PROPERTIES 2
116 struct thread_groups_list {
117 unsigned int nr_properties;
118 struct thread_groups property_tgs[MAX_THREAD_GROUP_PROPERTIES];
121 static struct thread_groups_list tgl[NR_CPUS] __initdata;
123 * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to
124 * the set its siblings that share the L1-cache.
126 DEFINE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map);
129 * On some big-cores system, thread_group_l2_cache_map for each CPU
130 * corresponds to the set its siblings within the core that share the
133 DEFINE_PER_CPU(cpumask_var_t, thread_group_l2_cache_map);
136 * On P10, thread_group_l3_cache_map for each CPU is equal to the
137 * thread_group_l2_cache_map
139 DEFINE_PER_CPU(cpumask_var_t, thread_group_l3_cache_map);
141 /* SMP operations for this machine */
142 struct smp_ops_t *smp_ops;
144 /* Can't be static due to PowerMac hackery */
145 volatile unsigned int cpu_callin_map[NR_CPUS];
147 int smt_enabled_at_boot = 1;
150 * Returns 1 if the specified cpu should be brought up during boot.
151 * Used to inhibit booting threads if they've been disabled or
152 * limited on the command line
154 int smp_generic_cpu_bootable(unsigned int nr)
156 /* Special case - we inhibit secondary thread startup
157 * during boot if the user requests it.
159 if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) {
160 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
162 if (smt_enabled_at_boot
163 && cpu_thread_in_core(nr) >= smt_enabled_at_boot)
172 int smp_generic_kick_cpu(int nr)
174 if (nr < 0 || nr >= nr_cpu_ids)
178 * The processor is currently spinning, waiting for the
179 * cpu_start field to become non-zero After we set cpu_start,
180 * the processor will continue on to secondary_start
182 if (!paca_ptrs[nr]->cpu_start) {
183 paca_ptrs[nr]->cpu_start = 1;
188 #ifdef CONFIG_HOTPLUG_CPU
190 * Ok it's not there, so it might be soft-unplugged, let's
191 * try to bring it back
193 generic_set_cpu_up(nr);
195 smp_send_reschedule(nr);
196 #endif /* CONFIG_HOTPLUG_CPU */
200 #endif /* CONFIG_PPC64 */
202 static irqreturn_t call_function_action(int irq, void *data)
204 generic_smp_call_function_interrupt();
208 static irqreturn_t reschedule_action(int irq, void *data)
214 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
215 static irqreturn_t tick_broadcast_ipi_action(int irq, void *data)
217 timer_broadcast_interrupt();
222 #ifdef CONFIG_NMI_IPI
223 static irqreturn_t nmi_ipi_action(int irq, void *data)
225 smp_handle_nmi_ipi(get_irq_regs());
230 static irq_handler_t smp_ipi_action[] = {
231 [PPC_MSG_CALL_FUNCTION] = call_function_action,
232 [PPC_MSG_RESCHEDULE] = reschedule_action,
233 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
234 [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action,
236 #ifdef CONFIG_NMI_IPI
237 [PPC_MSG_NMI_IPI] = nmi_ipi_action,
242 * The NMI IPI is a fallback and not truly non-maskable. It is simpler
243 * than going through the call function infrastructure, and strongly
244 * serialized, so it is more appropriate for debugging.
246 const char *smp_ipi_name[] = {
247 [PPC_MSG_CALL_FUNCTION] = "ipi call function",
248 [PPC_MSG_RESCHEDULE] = "ipi reschedule",
249 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
250 [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast",
252 #ifdef CONFIG_NMI_IPI
253 [PPC_MSG_NMI_IPI] = "nmi ipi",
257 /* optional function to request ipi, for controllers with >= 4 ipis */
258 int smp_request_message_ipi(int virq, int msg)
262 if (msg < 0 || msg > PPC_MSG_NMI_IPI)
264 #ifndef CONFIG_NMI_IPI
265 if (msg == PPC_MSG_NMI_IPI)
269 err = request_irq(virq, smp_ipi_action[msg],
270 IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND,
271 smp_ipi_name[msg], NULL);
272 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n",
273 virq, smp_ipi_name[msg], err);
278 #ifdef CONFIG_PPC_SMP_MUXED_IPI
279 struct cpu_messages {
280 long messages; /* current messages */
282 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message);
284 void smp_muxed_ipi_set_message(int cpu, int msg)
286 struct cpu_messages *info = &per_cpu(ipi_message, cpu);
287 char *message = (char *)&info->messages;
290 * Order previous accesses before accesses in the IPI handler.
296 void smp_muxed_ipi_message_pass(int cpu, int msg)
298 smp_muxed_ipi_set_message(cpu, msg);
301 * cause_ipi functions are required to include a full barrier
302 * before doing whatever causes the IPI.
304 smp_ops->cause_ipi(cpu);
307 #ifdef __BIG_ENDIAN__
308 #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A)))
310 #define IPI_MESSAGE(A) (1uL << (8 * (A)))
313 irqreturn_t smp_ipi_demux(void)
315 mb(); /* order any irq clear */
317 return smp_ipi_demux_relaxed();
320 /* sync-free variant. Callers should ensure synchronization */
321 irqreturn_t smp_ipi_demux_relaxed(void)
323 struct cpu_messages *info;
326 info = this_cpu_ptr(&ipi_message);
328 all = xchg(&info->messages, 0);
329 #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE)
331 * Must check for PPC_MSG_RM_HOST_ACTION messages
332 * before PPC_MSG_CALL_FUNCTION messages because when
333 * a VM is destroyed, we call kick_all_cpus_sync()
334 * to ensure that any pending PPC_MSG_RM_HOST_ACTION
335 * messages have completed before we free any VCPUs.
337 if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION))
338 kvmppc_xics_ipi_action();
340 if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION))
341 generic_smp_call_function_interrupt();
342 if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE))
344 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
345 if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST))
346 timer_broadcast_interrupt();
348 #ifdef CONFIG_NMI_IPI
349 if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI))
350 nmi_ipi_action(0, NULL);
352 } while (info->messages);
356 #endif /* CONFIG_PPC_SMP_MUXED_IPI */
358 static inline void do_message_pass(int cpu, int msg)
360 if (smp_ops->message_pass)
361 smp_ops->message_pass(cpu, msg);
362 #ifdef CONFIG_PPC_SMP_MUXED_IPI
364 smp_muxed_ipi_message_pass(cpu, msg);
368 void smp_send_reschedule(int cpu)
371 do_message_pass(cpu, PPC_MSG_RESCHEDULE);
373 EXPORT_SYMBOL_GPL(smp_send_reschedule);
375 void arch_send_call_function_single_ipi(int cpu)
377 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
380 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
384 for_each_cpu(cpu, mask)
385 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
388 #ifdef CONFIG_NMI_IPI
393 * NMI IPIs may not be recoverable, so should not be used as ongoing part of
394 * a running system. They can be used for crash, debug, halt/reboot, etc.
396 * The IPI call waits with interrupts disabled until all targets enter the
397 * NMI handler, then returns. Subsequent IPIs can be issued before targets
398 * have returned from their handlers, so there is no guarantee about
399 * concurrency or re-entrancy.
401 * A new NMI can be issued before all targets exit the handler.
403 * The IPI call may time out without all targets entering the NMI handler.
404 * In that case, there is some logic to recover (and ignore subsequent
405 * NMI interrupts that may eventually be raised), but the platform interrupt
406 * handler may not be able to distinguish this from other exception causes,
407 * which may cause a crash.
410 static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0);
411 static struct cpumask nmi_ipi_pending_mask;
412 static bool nmi_ipi_busy = false;
413 static void (*nmi_ipi_function)(struct pt_regs *) = NULL;
415 static void nmi_ipi_lock_start(unsigned long *flags)
417 raw_local_irq_save(*flags);
419 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) {
420 raw_local_irq_restore(*flags);
421 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0);
422 raw_local_irq_save(*flags);
427 static void nmi_ipi_lock(void)
429 while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1)
430 spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0);
433 static void nmi_ipi_unlock(void)
436 WARN_ON(atomic_read(&__nmi_ipi_lock) != 1);
437 atomic_set(&__nmi_ipi_lock, 0);
440 static void nmi_ipi_unlock_end(unsigned long *flags)
443 raw_local_irq_restore(*flags);
447 * Platform NMI handler calls this to ack
449 int smp_handle_nmi_ipi(struct pt_regs *regs)
451 void (*fn)(struct pt_regs *) = NULL;
453 int me = raw_smp_processor_id();
457 * Unexpected NMIs are possible here because the interrupt may not
458 * be able to distinguish NMI IPIs from other types of NMIs, or
459 * because the caller may have timed out.
461 nmi_ipi_lock_start(&flags);
462 if (cpumask_test_cpu(me, &nmi_ipi_pending_mask)) {
463 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
464 fn = READ_ONCE(nmi_ipi_function);
468 nmi_ipi_unlock_end(&flags);
476 static void do_smp_send_nmi_ipi(int cpu, bool safe)
478 if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu))
482 do_message_pass(cpu, PPC_MSG_NMI_IPI);
486 for_each_online_cpu(c) {
487 if (c == raw_smp_processor_id())
489 do_message_pass(c, PPC_MSG_NMI_IPI);
495 * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS.
496 * - fn is the target callback function.
497 * - delay_us > 0 is the delay before giving up waiting for targets to
498 * begin executing the handler, == 0 specifies indefinite delay.
500 static int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *),
501 u64 delay_us, bool safe)
504 int me = raw_smp_processor_id();
508 BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS);
510 if (unlikely(!smp_ops))
513 nmi_ipi_lock_start(&flags);
514 while (nmi_ipi_busy) {
515 nmi_ipi_unlock_end(&flags);
516 spin_until_cond(!nmi_ipi_busy);
517 nmi_ipi_lock_start(&flags);
520 nmi_ipi_function = fn;
522 WARN_ON_ONCE(!cpumask_empty(&nmi_ipi_pending_mask));
526 cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask);
527 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
529 cpumask_set_cpu(cpu, &nmi_ipi_pending_mask);
534 /* Interrupts remain hard disabled */
536 do_smp_send_nmi_ipi(cpu, safe);
539 /* nmi_ipi_busy is set here, so unlock/lock is okay */
540 while (!cpumask_empty(&nmi_ipi_pending_mask)) {
551 if (!cpumask_empty(&nmi_ipi_pending_mask)) {
552 /* Timeout waiting for CPUs to call smp_handle_nmi_ipi */
554 cpumask_clear(&nmi_ipi_pending_mask);
557 nmi_ipi_function = NULL;
558 nmi_ipi_busy = false;
560 nmi_ipi_unlock_end(&flags);
565 int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
567 return __smp_send_nmi_ipi(cpu, fn, delay_us, false);
570 int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
572 return __smp_send_nmi_ipi(cpu, fn, delay_us, true);
574 #endif /* CONFIG_NMI_IPI */
576 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
577 void tick_broadcast(const struct cpumask *mask)
581 for_each_cpu(cpu, mask)
582 do_message_pass(cpu, PPC_MSG_TICK_BROADCAST);
586 #ifdef CONFIG_DEBUGGER
587 static void debugger_ipi_callback(struct pt_regs *regs)
592 void smp_send_debugger_break(void)
594 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000);
598 #ifdef CONFIG_KEXEC_CORE
599 void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *))
603 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000);
604 if (kdump_in_progress() && crash_wake_offline) {
605 for_each_present_cpu(cpu) {
609 * crash_ipi_callback will wait for
610 * all cpus, including offline CPUs.
611 * We don't care about nmi_ipi_function.
612 * Offline cpus will jump straight into
613 * crash_ipi_callback, we can skip the
614 * entire NMI dance and waiting for
615 * cpus to clear pending mask, etc.
617 do_smp_send_nmi_ipi(cpu, false);
623 #ifdef CONFIG_NMI_IPI
624 static void crash_stop_this_cpu(struct pt_regs *regs)
626 static void crash_stop_this_cpu(void *dummy)
630 * Just busy wait here and avoid marking CPU as offline to ensure
631 * register data is captured appropriately.
637 void crash_smp_send_stop(void)
639 static bool stopped = false;
646 #ifdef CONFIG_NMI_IPI
647 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_stop_this_cpu, 1000000);
649 smp_call_function(crash_stop_this_cpu, NULL, 0);
650 #endif /* CONFIG_NMI_IPI */
653 #ifdef CONFIG_NMI_IPI
654 static void nmi_stop_this_cpu(struct pt_regs *regs)
657 * IRQs are already hard disabled by the smp_handle_nmi_ipi.
659 set_cpu_online(smp_processor_id(), false);
666 void smp_send_stop(void)
668 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000);
671 #else /* CONFIG_NMI_IPI */
673 static void stop_this_cpu(void *dummy)
678 * Offlining CPUs in stop_this_cpu can result in scheduler warnings,
679 * (see commit de6e5d38417e), but printk_safe_flush_on_panic() wants
680 * to know other CPUs are offline before it breaks locks to flush
681 * printk buffers, in case we panic()ed while holding the lock.
683 set_cpu_online(smp_processor_id(), false);
690 void smp_send_stop(void)
692 static bool stopped = false;
695 * Prevent waiting on csd lock from a previous smp_send_stop.
696 * This is racy, but in general callers try to do the right
697 * thing and only fire off one smp_send_stop (e.g., see
705 smp_call_function(stop_this_cpu, NULL, 0);
707 #endif /* CONFIG_NMI_IPI */
709 struct task_struct *current_set[NR_CPUS];
711 static void smp_store_cpu_info(int id)
713 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
714 #ifdef CONFIG_PPC_FSL_BOOK3E
715 per_cpu(next_tlbcam_idx, id)
716 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
721 * Relationships between CPUs are maintained in a set of per-cpu cpumasks so
722 * rather than just passing around the cpumask we pass around a function that
723 * returns the that cpumask for the given CPU.
725 static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int))
727 cpumask_set_cpu(i, get_cpumask(j));
728 cpumask_set_cpu(j, get_cpumask(i));
731 #ifdef CONFIG_HOTPLUG_CPU
732 static void set_cpus_unrelated(int i, int j,
733 struct cpumask *(*get_cpumask)(int))
735 cpumask_clear_cpu(i, get_cpumask(j));
736 cpumask_clear_cpu(j, get_cpumask(i));
741 * Extends set_cpus_related. Instead of setting one CPU at a time in
742 * dstmask, set srcmask at oneshot. dstmask should be super set of srcmask.
744 static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int),
745 struct cpumask *(*dstmask)(int))
747 struct cpumask *mask;
751 for_each_cpu(k, srcmask(i))
752 cpumask_or(dstmask(k), dstmask(k), mask);
758 for_each_cpu(k, srcmask(j))
759 cpumask_or(dstmask(k), dstmask(k), mask);
763 * parse_thread_groups: Parses the "ibm,thread-groups" device tree
764 * property for the CPU device node @dn and stores
765 * the parsed output in the thread_groups_list
768 * @dn: The device node of the CPU device.
769 * @tglp: Pointer to a thread group list structure into which the parsed
770 * output of "ibm,thread-groups" is stored.
772 * ibm,thread-groups[0..N-1] array defines which group of threads in
773 * the CPU-device node can be grouped together based on the property.
775 * This array can represent thread groupings for multiple properties.
777 * ibm,thread-groups[i + 0] tells us the property based on which the
778 * threads are being grouped together. If this value is 1, it implies
779 * that the threads in the same group share L1, translation cache. If
780 * the value is 2, it implies that the threads in the same group share
783 * ibm,thread-groups[i+1] tells us how many such thread groups exist for the
784 * property ibm,thread-groups[i]
786 * ibm,thread-groups[i+2] tells us the number of threads in each such
788 * Suppose k = (ibm,thread-groups[i+1] * ibm,thread-groups[i+2]), then,
790 * ibm,thread-groups[i+3..i+k+2] (is the list of threads identified by
791 * "ibm,ppc-interrupt-server#s" arranged as per their membership in
795 * If "ibm,thread-groups" = [1,2,4,8,10,12,14,9,11,13,15,2,2,4,8,10,12,14,9,11,13,15]
796 * This can be decomposed up into two consecutive arrays:
797 * a) [1,2,4,8,10,12,14,9,11,13,15]
798 * b) [2,2,4,8,10,12,14,9,11,13,15]
802 * a) provides information of Property "1" being shared by "2" groups,
803 * each with "4" threads each. The "ibm,ppc-interrupt-server#s" of
804 * the first group is {8,10,12,14} and the
805 * "ibm,ppc-interrupt-server#s" of the second group is
806 * {9,11,13,15}. Property "1" is indicative of the thread in the
807 * group sharing L1 cache, translation cache and Instruction Data
810 * b) provides information of Property "2" being shared by "2" groups,
811 * each group with "4" threads. The "ibm,ppc-interrupt-server#s" of
812 * the first group is {8,10,12,14} and the
813 * "ibm,ppc-interrupt-server#s" of the second group is
814 * {9,11,13,15}. Property "2" indicates that the threads in each
815 * group share the L2-cache.
817 * Returns 0 on success, -EINVAL if the property does not exist,
818 * -ENODATA if property does not have a value, and -EOVERFLOW if the
819 * property data isn't large enough.
821 static int parse_thread_groups(struct device_node *dn,
822 struct thread_groups_list *tglp)
824 unsigned int property_idx = 0;
825 u32 *thread_group_array;
826 size_t total_threads;
831 count = of_property_count_u32_elems(dn, "ibm,thread-groups");
832 thread_group_array = kcalloc(count, sizeof(u32), GFP_KERNEL);
833 ret = of_property_read_u32_array(dn, "ibm,thread-groups",
834 thread_group_array, count);
838 while (i < count && property_idx < MAX_THREAD_GROUP_PROPERTIES) {
840 struct thread_groups *tg = &tglp->property_tgs[property_idx++];
842 tg->property = thread_group_array[i];
843 tg->nr_groups = thread_group_array[i + 1];
844 tg->threads_per_group = thread_group_array[i + 2];
845 total_threads = tg->nr_groups * tg->threads_per_group;
847 thread_list = &thread_group_array[i + 3];
849 for (j = 0; j < total_threads; j++)
850 tg->thread_list[j] = thread_list[j];
851 i = i + 3 + total_threads;
854 tglp->nr_properties = property_idx;
857 kfree(thread_group_array);
862 * get_cpu_thread_group_start : Searches the thread group in tg->thread_list
863 * that @cpu belongs to.
865 * @cpu : The logical CPU whose thread group is being searched.
866 * @tg : The thread-group structure of the CPU node which @cpu belongs
869 * Returns the index to tg->thread_list that points to the the start
870 * of the thread_group that @cpu belongs to.
872 * Returns -1 if cpu doesn't belong to any of the groups pointed to by
875 static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg)
877 int hw_cpu_id = get_hard_smp_processor_id(cpu);
880 for (i = 0; i < tg->nr_groups; i++) {
881 int group_start = i * tg->threads_per_group;
883 for (j = 0; j < tg->threads_per_group; j++) {
884 int idx = group_start + j;
886 if (tg->thread_list[idx] == hw_cpu_id)
894 static struct thread_groups *__init get_thread_groups(int cpu,
898 struct device_node *dn = of_get_cpu_node(cpu, NULL);
899 struct thread_groups_list *cpu_tgl = &tgl[cpu];
900 struct thread_groups *tg = NULL;
909 if (!cpu_tgl->nr_properties) {
910 *err = parse_thread_groups(dn, cpu_tgl);
915 for (i = 0; i < cpu_tgl->nr_properties; i++) {
916 if (cpu_tgl->property_tgs[i].property == group_property) {
917 tg = &cpu_tgl->property_tgs[i];
929 static int update_mask_from_threadgroup(cpumask_var_t *mask, struct thread_groups *tg, int cpu, int cpu_group_start)
931 int first_thread = cpu_first_thread_sibling(cpu);
934 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cpu));
936 for (i = first_thread; i < first_thread + threads_per_core; i++) {
937 int i_group_start = get_cpu_thread_group_start(i, tg);
939 if (unlikely(i_group_start == -1)) {
944 if (i_group_start == cpu_group_start)
945 cpumask_set_cpu(i, *mask);
951 static int __init init_thread_group_cache_map(int cpu, int cache_property)
954 int cpu_group_start = -1, err = 0;
955 struct thread_groups *tg = NULL;
956 cpumask_var_t *mask = NULL;
958 if (cache_property != THREAD_GROUP_SHARE_L1 &&
959 cache_property != THREAD_GROUP_SHARE_L2_L3)
962 tg = get_thread_groups(cpu, cache_property, &err);
967 cpu_group_start = get_cpu_thread_group_start(cpu, tg);
969 if (unlikely(cpu_group_start == -1)) {
974 if (cache_property == THREAD_GROUP_SHARE_L1) {
975 mask = &per_cpu(thread_group_l1_cache_map, cpu);
976 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
978 else if (cache_property == THREAD_GROUP_SHARE_L2_L3) {
979 mask = &per_cpu(thread_group_l2_cache_map, cpu);
980 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
981 mask = &per_cpu(thread_group_l3_cache_map, cpu);
982 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
989 static bool shared_caches;
991 #ifdef CONFIG_SCHED_SMT
992 /* cpumask of CPUs with asymmetric SMT dependency */
993 static int powerpc_smt_flags(void)
995 int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES;
997 if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
998 printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
999 flags |= SD_ASYM_PACKING;
1006 * P9 has a slightly odd architecture where pairs of cores share an L2 cache.
1007 * This topology makes it *much* cheaper to migrate tasks between adjacent cores
1008 * since the migrated task remains cache hot. We want to take advantage of this
1009 * at the scheduler level so an extra topology level is required.
1011 static int powerpc_shared_cache_flags(void)
1013 return SD_SHARE_PKG_RESOURCES;
1017 * We can't just pass cpu_l2_cache_mask() directly because
1018 * returns a non-const pointer and the compiler barfs on that.
1020 static const struct cpumask *shared_cache_mask(int cpu)
1022 return per_cpu(cpu_l2_cache_map, cpu);
1025 #ifdef CONFIG_SCHED_SMT
1026 static const struct cpumask *smallcore_smt_mask(int cpu)
1028 return cpu_smallcore_mask(cpu);
1032 static struct cpumask *cpu_coregroup_mask(int cpu)
1034 return per_cpu(cpu_coregroup_map, cpu);
1037 static bool has_coregroup_support(void)
1039 return coregroup_enabled;
1042 static const struct cpumask *cpu_mc_mask(int cpu)
1044 return cpu_coregroup_mask(cpu);
1047 static struct sched_domain_topology_level powerpc_topology[] = {
1048 #ifdef CONFIG_SCHED_SMT
1049 { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
1051 { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) },
1052 { cpu_mc_mask, SD_INIT_NAME(MC) },
1053 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
1057 static int __init init_big_cores(void)
1061 for_each_possible_cpu(cpu) {
1062 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L1);
1067 zalloc_cpumask_var_node(&per_cpu(cpu_smallcore_map, cpu),
1072 has_big_cores = true;
1074 for_each_possible_cpu(cpu) {
1075 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L2_L3);
1081 thread_group_shares_l2 = true;
1082 thread_group_shares_l3 = true;
1083 pr_debug("L2/L3 cache only shared by the threads in the small core\n");
1088 void __init smp_prepare_cpus(unsigned int max_cpus)
1092 DBG("smp_prepare_cpus\n");
1095 * setup_cpu may need to be called on the boot cpu. We havent
1096 * spun any cpus up but lets be paranoid.
1098 BUG_ON(boot_cpuid != smp_processor_id());
1100 /* Fixup boot cpu */
1101 smp_store_cpu_info(boot_cpuid);
1102 cpu_callin_map[boot_cpuid] = 1;
1104 for_each_possible_cpu(cpu) {
1105 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu),
1106 GFP_KERNEL, cpu_to_node(cpu));
1107 zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu),
1108 GFP_KERNEL, cpu_to_node(cpu));
1109 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu),
1110 GFP_KERNEL, cpu_to_node(cpu));
1111 if (has_coregroup_support())
1112 zalloc_cpumask_var_node(&per_cpu(cpu_coregroup_map, cpu),
1113 GFP_KERNEL, cpu_to_node(cpu));
1117 * numa_node_id() works after this.
1119 if (cpu_present(cpu)) {
1120 set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]);
1121 set_cpu_numa_mem(cpu,
1122 local_memory_node(numa_cpu_lookup_table[cpu]));
1127 /* Init the cpumasks so the boot CPU is related to itself */
1128 cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid));
1129 cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid));
1130 cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid));
1132 if (has_coregroup_support())
1133 cpumask_set_cpu(boot_cpuid, cpu_coregroup_mask(boot_cpuid));
1136 if (has_big_cores) {
1137 cpumask_set_cpu(boot_cpuid,
1138 cpu_smallcore_mask(boot_cpuid));
1141 if (cpu_to_chip_id(boot_cpuid) != -1) {
1142 int idx = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1145 * All threads of a core will all belong to the same core,
1146 * chip_id_lookup_table will have one entry per core.
1147 * Assumption: if boot_cpuid doesn't have a chip-id, then no
1148 * other CPUs, will also not have chip-id.
1150 chip_id_lookup_table = kcalloc(idx, sizeof(int), GFP_KERNEL);
1151 if (chip_id_lookup_table)
1152 memset(chip_id_lookup_table, -1, sizeof(int) * idx);
1155 if (smp_ops && smp_ops->probe)
1159 void smp_prepare_boot_cpu(void)
1161 BUG_ON(smp_processor_id() != boot_cpuid);
1163 paca_ptrs[boot_cpuid]->__current = current;
1165 set_numa_node(numa_cpu_lookup_table[boot_cpuid]);
1166 current_set[boot_cpuid] = current;
1169 #ifdef CONFIG_HOTPLUG_CPU
1171 int generic_cpu_disable(void)
1173 unsigned int cpu = smp_processor_id();
1175 if (cpu == boot_cpuid)
1178 set_cpu_online(cpu, false);
1180 vdso_data->processorCount--;
1182 /* Update affinity of all IRQs previously aimed at this CPU */
1183 irq_migrate_all_off_this_cpu();
1186 * Depending on the details of the interrupt controller, it's possible
1187 * that one of the interrupts we just migrated away from this CPU is
1188 * actually already pending on this CPU. If we leave it in that state
1189 * the interrupt will never be EOI'ed, and will never fire again. So
1190 * temporarily enable interrupts here, to allow any pending interrupt to
1191 * be received (and EOI'ed), before we take this CPU offline.
1195 local_irq_disable();
1200 void generic_cpu_die(unsigned int cpu)
1204 for (i = 0; i < 100; i++) {
1206 if (is_cpu_dead(cpu))
1210 printk(KERN_ERR "CPU%d didn't die...\n", cpu);
1213 void generic_set_cpu_dead(unsigned int cpu)
1215 per_cpu(cpu_state, cpu) = CPU_DEAD;
1219 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
1220 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
1221 * which makes the delay in generic_cpu_die() not happen.
1223 void generic_set_cpu_up(unsigned int cpu)
1225 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1228 int generic_check_cpu_restart(unsigned int cpu)
1230 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
1233 int is_cpu_dead(unsigned int cpu)
1235 return per_cpu(cpu_state, cpu) == CPU_DEAD;
1238 static bool secondaries_inhibited(void)
1240 return kvm_hv_mode_active();
1243 #else /* HOTPLUG_CPU */
1245 #define secondaries_inhibited() 0
1249 static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle)
1252 paca_ptrs[cpu]->__current = idle;
1253 paca_ptrs[cpu]->kstack = (unsigned long)task_stack_page(idle) +
1254 THREAD_SIZE - STACK_FRAME_OVERHEAD;
1257 secondary_current = current_set[cpu] = idle;
1260 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1265 * Don't allow secondary threads to come online if inhibited
1267 if (threads_per_core > 1 && secondaries_inhibited() &&
1268 cpu_thread_in_subcore(cpu))
1271 if (smp_ops == NULL ||
1272 (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu)))
1275 cpu_idle_thread_init(cpu, tidle);
1278 * The platform might need to allocate resources prior to bringing
1281 if (smp_ops->prepare_cpu) {
1282 rc = smp_ops->prepare_cpu(cpu);
1287 /* Make sure callin-map entry is 0 (can be leftover a CPU
1290 cpu_callin_map[cpu] = 0;
1292 /* The information for processor bringup must
1293 * be written out to main store before we release
1299 DBG("smp: kicking cpu %d\n", cpu);
1300 rc = smp_ops->kick_cpu(cpu);
1302 pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc);
1307 * wait to see if the cpu made a callin (is actually up).
1308 * use this value that I found through experimentation.
1311 if (system_state < SYSTEM_RUNNING)
1312 for (c = 50000; c && !cpu_callin_map[cpu]; c--)
1314 #ifdef CONFIG_HOTPLUG_CPU
1317 * CPUs can take much longer to come up in the
1318 * hotplug case. Wait five seconds.
1320 for (c = 5000; c && !cpu_callin_map[cpu]; c--)
1324 if (!cpu_callin_map[cpu]) {
1325 printk(KERN_ERR "Processor %u is stuck.\n", cpu);
1329 DBG("Processor %u found.\n", cpu);
1331 if (smp_ops->give_timebase)
1332 smp_ops->give_timebase();
1334 /* Wait until cpu puts itself in the online & active maps */
1335 spin_until_cond(cpu_online(cpu));
1340 /* Return the value of the reg property corresponding to the given
1343 int cpu_to_core_id(int cpu)
1345 struct device_node *np;
1349 np = of_get_cpu_node(cpu, NULL);
1353 reg = of_get_property(np, "reg", NULL);
1357 id = be32_to_cpup(reg);
1362 EXPORT_SYMBOL_GPL(cpu_to_core_id);
1364 /* Helper routines for cpu to core mapping */
1365 int cpu_core_index_of_thread(int cpu)
1367 return cpu >> threads_shift;
1369 EXPORT_SYMBOL_GPL(cpu_core_index_of_thread);
1371 int cpu_first_thread_of_core(int core)
1373 return core << threads_shift;
1375 EXPORT_SYMBOL_GPL(cpu_first_thread_of_core);
1377 /* Must be called when no change can occur to cpu_present_mask,
1378 * i.e. during cpu online or offline.
1380 static struct device_node *cpu_to_l2cache(int cpu)
1382 struct device_node *np;
1383 struct device_node *cache;
1385 if (!cpu_present(cpu))
1388 np = of_get_cpu_node(cpu, NULL);
1392 cache = of_find_next_cache_node(np);
1399 static bool update_mask_by_l2(int cpu, cpumask_var_t *mask)
1401 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1402 struct device_node *l2_cache, *np;
1406 submask_fn = cpu_smallcore_mask;
1409 * If the threads in a thread-group share L2 cache, then the
1410 * L2-mask can be obtained from thread_group_l2_cache_map.
1412 if (thread_group_shares_l2) {
1413 cpumask_set_cpu(cpu, cpu_l2_cache_mask(cpu));
1415 for_each_cpu(i, per_cpu(thread_group_l2_cache_map, cpu)) {
1417 set_cpus_related(i, cpu, cpu_l2_cache_mask);
1420 /* Verify that L1-cache siblings are a subset of L2 cache-siblings */
1421 if (!cpumask_equal(submask_fn(cpu), cpu_l2_cache_mask(cpu)) &&
1422 !cpumask_subset(submask_fn(cpu), cpu_l2_cache_mask(cpu))) {
1423 pr_warn_once("CPU %d : Inconsistent L1 and L2 cache siblings\n",
1430 l2_cache = cpu_to_l2cache(cpu);
1431 if (!l2_cache || !*mask) {
1432 /* Assume only core siblings share cache with this CPU */
1433 for_each_cpu(i, cpu_sibling_mask(cpu))
1434 set_cpus_related(cpu, i, cpu_l2_cache_mask);
1439 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu));
1441 /* Update l2-cache mask with all the CPUs that are part of submask */
1442 or_cpumasks_related(cpu, cpu, submask_fn, cpu_l2_cache_mask);
1444 /* Skip all CPUs already part of current CPU l2-cache mask */
1445 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(cpu));
1447 for_each_cpu(i, *mask) {
1449 * when updating the marks the current CPU has not been marked
1450 * online, but we need to update the cache masks
1452 np = cpu_to_l2cache(i);
1454 /* Skip all CPUs already part of current CPU l2-cache */
1455 if (np == l2_cache) {
1456 or_cpumasks_related(cpu, i, submask_fn, cpu_l2_cache_mask);
1457 cpumask_andnot(*mask, *mask, submask_fn(i));
1459 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(i));
1464 of_node_put(l2_cache);
1469 #ifdef CONFIG_HOTPLUG_CPU
1470 static void remove_cpu_from_masks(int cpu)
1472 struct cpumask *(*mask_fn)(int) = cpu_sibling_mask;
1475 unmap_cpu_from_node(cpu);
1478 mask_fn = cpu_l2_cache_mask;
1480 for_each_cpu(i, mask_fn(cpu)) {
1481 set_cpus_unrelated(cpu, i, cpu_l2_cache_mask);
1482 set_cpus_unrelated(cpu, i, cpu_sibling_mask);
1484 set_cpus_unrelated(cpu, i, cpu_smallcore_mask);
1487 for_each_cpu(i, cpu_core_mask(cpu))
1488 set_cpus_unrelated(cpu, i, cpu_core_mask);
1490 if (has_coregroup_support()) {
1491 for_each_cpu(i, cpu_coregroup_mask(cpu))
1492 set_cpus_unrelated(cpu, i, cpu_coregroup_mask);
1497 static inline void add_cpu_to_smallcore_masks(int cpu)
1504 cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu));
1506 for_each_cpu(i, per_cpu(thread_group_l1_cache_map, cpu)) {
1508 set_cpus_related(i, cpu, cpu_smallcore_mask);
1512 static void update_coregroup_mask(int cpu, cpumask_var_t *mask)
1514 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1515 int coregroup_id = cpu_to_coregroup_id(cpu);
1519 submask_fn = cpu_l2_cache_mask;
1522 /* Assume only siblings are part of this CPU's coregroup */
1523 for_each_cpu(i, submask_fn(cpu))
1524 set_cpus_related(cpu, i, cpu_coregroup_mask);
1529 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu));
1531 /* Update coregroup mask with all the CPUs that are part of submask */
1532 or_cpumasks_related(cpu, cpu, submask_fn, cpu_coregroup_mask);
1534 /* Skip all CPUs already part of coregroup mask */
1535 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(cpu));
1537 for_each_cpu(i, *mask) {
1538 /* Skip all CPUs not part of this coregroup */
1539 if (coregroup_id == cpu_to_coregroup_id(i)) {
1540 or_cpumasks_related(cpu, i, submask_fn, cpu_coregroup_mask);
1541 cpumask_andnot(*mask, *mask, submask_fn(i));
1543 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(i));
1548 static void add_cpu_to_masks(int cpu)
1550 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1551 int first_thread = cpu_first_thread_sibling(cpu);
1558 * This CPU will not be in the online mask yet so we need to manually
1559 * add it to it's own thread sibling mask.
1561 map_cpu_to_node(cpu, cpu_to_node(cpu));
1562 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
1563 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
1565 for (i = first_thread; i < first_thread + threads_per_core; i++)
1567 set_cpus_related(i, cpu, cpu_sibling_mask);
1569 add_cpu_to_smallcore_masks(cpu);
1571 /* In CPU-hotplug path, hence use GFP_ATOMIC */
1572 ret = alloc_cpumask_var_node(&mask, GFP_ATOMIC, cpu_to_node(cpu));
1573 update_mask_by_l2(cpu, &mask);
1575 if (has_coregroup_support())
1576 update_coregroup_mask(cpu, &mask);
1578 if (chip_id_lookup_table && ret)
1579 chip_id = cpu_to_chip_id(cpu);
1582 submask_fn = cpu_l2_cache_mask;
1584 /* Update core_mask with all the CPUs that are part of submask */
1585 or_cpumasks_related(cpu, cpu, submask_fn, cpu_core_mask);
1587 /* Skip all CPUs already part of current CPU core mask */
1588 cpumask_andnot(mask, cpu_online_mask, cpu_core_mask(cpu));
1590 /* If chip_id is -1; limit the cpu_core_mask to within DIE*/
1592 cpumask_and(mask, mask, cpu_cpu_mask(cpu));
1594 for_each_cpu(i, mask) {
1595 if (chip_id == cpu_to_chip_id(i)) {
1596 or_cpumasks_related(cpu, i, submask_fn, cpu_core_mask);
1597 cpumask_andnot(mask, mask, submask_fn(i));
1599 cpumask_andnot(mask, mask, cpu_core_mask(i));
1603 free_cpumask_var(mask);
1606 /* Activate a secondary processor. */
1607 void start_secondary(void *unused)
1609 unsigned int cpu = raw_smp_processor_id();
1611 /* PPC64 calls setup_kup() in early_setup_secondary() */
1612 if (IS_ENABLED(CONFIG_PPC32))
1616 current->active_mm = &init_mm;
1618 smp_store_cpu_info(cpu);
1619 set_dec(tb_ticks_per_jiffy);
1620 rcu_cpu_starting(cpu);
1621 cpu_callin_map[cpu] = 1;
1623 if (smp_ops->setup_cpu)
1624 smp_ops->setup_cpu(cpu);
1625 if (smp_ops->take_timebase)
1626 smp_ops->take_timebase();
1628 secondary_cpu_time_init();
1631 if (system_state == SYSTEM_RUNNING)
1632 vdso_data->processorCount++;
1636 set_numa_node(numa_cpu_lookup_table[cpu]);
1637 set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu]));
1639 /* Update topology CPU masks */
1640 add_cpu_to_masks(cpu);
1643 * Check for any shared caches. Note that this must be done on a
1644 * per-core basis because one core in the pair might be disabled.
1646 if (!shared_caches) {
1647 struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask;
1648 struct cpumask *mask = cpu_l2_cache_mask(cpu);
1651 sibling_mask = cpu_smallcore_mask;
1653 if (cpumask_weight(mask) > cpumask_weight(sibling_mask(cpu)))
1654 shared_caches = true;
1658 notify_cpu_starting(cpu);
1659 set_cpu_online(cpu, true);
1661 boot_init_stack_canary();
1665 /* We can enable ftrace for secondary cpus now */
1666 this_cpu_enable_ftrace();
1668 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1673 #ifdef CONFIG_PROFILING
1674 int setup_profiling_timer(unsigned int multiplier)
1680 static void fixup_topology(void)
1684 #ifdef CONFIG_SCHED_SMT
1685 if (has_big_cores) {
1686 pr_info("Big cores detected but using small core scheduling\n");
1687 powerpc_topology[smt_idx].mask = smallcore_smt_mask;
1691 if (!has_coregroup_support())
1692 powerpc_topology[mc_idx].mask = powerpc_topology[cache_idx].mask;
1695 * Try to consolidate topology levels here instead of
1696 * allowing scheduler to degenerate.
1697 * - Dont consolidate if masks are different.
1698 * - Dont consolidate if sd_flags exists and are different.
1700 for (i = 1; i <= die_idx; i++) {
1701 if (powerpc_topology[i].mask != powerpc_topology[i - 1].mask)
1704 if (powerpc_topology[i].sd_flags && powerpc_topology[i - 1].sd_flags &&
1705 powerpc_topology[i].sd_flags != powerpc_topology[i - 1].sd_flags)
1708 if (!powerpc_topology[i - 1].sd_flags)
1709 powerpc_topology[i - 1].sd_flags = powerpc_topology[i].sd_flags;
1711 powerpc_topology[i].mask = powerpc_topology[i + 1].mask;
1712 powerpc_topology[i].sd_flags = powerpc_topology[i + 1].sd_flags;
1713 #ifdef CONFIG_SCHED_DEBUG
1714 powerpc_topology[i].name = powerpc_topology[i + 1].name;
1719 void __init smp_cpus_done(unsigned int max_cpus)
1722 * We are running pinned to the boot CPU, see rest_init().
1724 if (smp_ops && smp_ops->setup_cpu)
1725 smp_ops->setup_cpu(boot_cpuid);
1727 if (smp_ops && smp_ops->bringup_done)
1728 smp_ops->bringup_done();
1730 dump_numa_cpu_topology();
1733 set_sched_topology(powerpc_topology);
1736 #ifdef CONFIG_HOTPLUG_CPU
1737 int __cpu_disable(void)
1739 int cpu = smp_processor_id();
1742 if (!smp_ops->cpu_disable)
1745 this_cpu_disable_ftrace();
1747 err = smp_ops->cpu_disable();
1751 /* Update sibling maps */
1752 remove_cpu_from_masks(cpu);
1757 void __cpu_die(unsigned int cpu)
1759 if (smp_ops->cpu_die)
1760 smp_ops->cpu_die(cpu);
1763 void arch_cpu_idle_dead(void)
1766 * Disable on the down path. This will be re-enabled by
1767 * start_secondary() via start_secondary_resume() below
1769 this_cpu_disable_ftrace();
1771 if (smp_ops->cpu_offline_self)
1772 smp_ops->cpu_offline_self();
1774 /* If we return, we re-enter start_secondary */
1775 start_secondary_resume();