arch/powerpc/kernel/setup_64.c

   1 /*
   2  *
   3  * Common boot and setup code.
   4  *
   5  * Copyright (C) 2001 PPC64 Team, IBM Corp
   6  *
   7  *      This program is free software; you can redistribute it and/or
   8  *      modify it under the terms of the GNU General Public License
   9  *      as published by the Free Software Foundation; either version
  10  *      2 of the License, or (at your option) any later version.
  11  */
  12
  13 #undef DEBUG
  14
  15 #include <linux/export.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <linux/reboot.h>
  21 #include <linux/delay.h>
  22 #include <linux/initrd.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/ioport.h>
  25 #include <linux/console.h>
  26 #include <linux/utsname.h>
  27 #include <linux/tty.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/notifier.h>
  30 #include <linux/cpu.h>
  31 #include <linux/unistd.h>
  32 #include <linux/serial.h>
  33 #include <linux/serial_8250.h>
  34 #include <linux/bootmem.h>
  35 #include <linux/pci.h>
  36 #include <linux/lockdep.h>
  37 #include <linux/memblock.h>
  38 #include <linux/hugetlb.h>
  39
  40 #include <asm/io.h>
  41 #include <asm/kdump.h>
  42 #include <asm/prom.h>
  43 #include <asm/processor.h>
  44 #include <asm/pgtable.h>
  45 #include <asm/smp.h>
  46 #include <asm/elf.h>
  47 #include <asm/machdep.h>
  48 #include <asm/paca.h>
  49 #include <asm/time.h>
  50 #include <asm/cputable.h>
  51 #include <asm/sections.h>
  52 #include <asm/btext.h>
  53 #include <asm/nvram.h>
  54 #include <asm/setup.h>
  55 #include <asm/rtas.h>
  56 #include <asm/iommu.h>
  57 #include <asm/serial.h>
  58 #include <asm/cache.h>
  59 #include <asm/page.h>
  60 #include <asm/mmu.h>
  61 #include <asm/firmware.h>
  62 #include <asm/xmon.h>
  63 #include <asm/udbg.h>
  64 #include <asm/kexec.h>
  65 #include <asm/mmu_context.h>
  66 #include <asm/code-patching.h>
  67 #include <asm/kvm_ppc.h>
  68 #include <asm/hugetlb.h>
  69
  70 #include "setup.h"
  71
  72 #ifdef DEBUG
  73 #define DBG(fmt...) udbg_printf(fmt)
  74 #else
  75 #define DBG(fmt...)
  76 #endif
  77
  78 int boot_cpuid = 0;
  79 int __initdata spinning_secondaries;
  80 u64 ppc64_pft_size;
  81
  82 /* Pick defaults since we might want to patch instructions
  83  * before we've read this from the device tree.
  84  */
  85 struct ppc64_caches ppc64_caches = {
  86         .dline_size = 0x40,
  87         .log_dline_size = 6,
  88         .iline_size = 0x40,
  89         .log_iline_size = 6
  90 };
  91 EXPORT_SYMBOL_GPL(ppc64_caches);
  92
  93 /*
  94  * These are used in binfmt_elf.c to put aux entries on the stack
  95  * for each elf executable being started.
  96  */
  97 int dcache_bsize;
  98 int icache_bsize;
  99 int ucache_bsize;
 100
 101 #ifdef CONFIG_SMP
 102
 103 static char *smt_enabled_cmdline;
 104
 105 /* Look for ibm,smt-enabled OF option */
 106 static void check_smt_enabled(void)
 107 {
 108         struct device_node *dn;
 109         const char *smt_option;
 110
 111         /* Default to enabling all threads */
 112         smt_enabled_at_boot = threads_per_core;
 113
 114         /* Allow the command line to overrule the OF option */
 115         if (smt_enabled_cmdline) {
 116                 if (!strcmp(smt_enabled_cmdline, "on"))
 117                         smt_enabled_at_boot = threads_per_core;
 118                 else if (!strcmp(smt_enabled_cmdline, "off"))
 119                         smt_enabled_at_boot = 0;
 120                 else {
 121                         long smt;
 122                         int rc;
 123
 124                         rc = strict_strtol(smt_enabled_cmdline, 10, &smt);
 125                         if (!rc)
 126                                 smt_enabled_at_boot =
 127                                         min(threads_per_core, (int)smt);
 128                 }
 129         } else {
 130                 dn = of_find_node_by_path("/options");
 131                 if (dn) {
 132                         smt_option = of_get_property(dn, "ibm,smt-enabled",
 133                                                      NULL);
 134
 135                         if (smt_option) {
 136                                 if (!strcmp(smt_option, "on"))
 137                                         smt_enabled_at_boot = threads_per_core;
 138                                 else if (!strcmp(smt_option, "off"))
 139                                         smt_enabled_at_boot = 0;
 140                         }
 141
 142                         of_node_put(dn);
 143                 }
 144         }
 145 }
 146
 147 /* Look for smt-enabled= cmdline option */
 148 static int __init early_smt_enabled(char *p)
 149 {
 150         smt_enabled_cmdline = p;
 151         return 0;
 152 }
 153 early_param("smt-enabled", early_smt_enabled);
 154
 155 #else
 156 #define check_smt_enabled()
 157 #endif /* CONFIG_SMP */
 158
 159 /** Fix up paca fields required for the boot cpu */
 160 static void fixup_boot_paca(void)
 161 {
 162         /* The boot cpu is started */
 163         get_paca()->cpu_start = 1;
 164         /* Allow percpu accesses to work until we setup percpu data */
 165         get_paca()->data_offset = 0;
 166 }
 167
 168 /*
 169  * Early initialization entry point. This is called by head.S
 170  * with MMU translation disabled. We rely on the "feature" of
 171  * the CPU that ignores the top 2 bits of the address in real
 172  * mode so we can access kernel globals normally provided we
 173  * only toy with things in the RMO region. From here, we do
 174  * some early parsing of the device-tree to setup out MEMBLOCK
 175  * data structures, and allocate & initialize the hash table
 176  * and segment tables so we can start running with translation
 177  * enabled.
 178  *
 179  * It is this function which will call the probe() callback of
 180  * the various platform types and copy the matching one to the
 181  * global ppc_md structure. Your platform can eventually do
 182  * some very early initializations from the probe() routine, but
 183  * this is not recommended, be very careful as, for example, the
 184  * device-tree is not accessible via normal means at this point.
 185  */
 186
 187 void __init early_setup(unsigned long dt_ptr)
 188 {
 189         /* -------- printk is _NOT_ safe to use here ! ------- */
 190
 191         /* Identify CPU type */
 192         identify_cpu(0, mfspr(SPRN_PVR));
 193
 194         /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
 195         initialise_paca(&boot_paca, 0);
 196         setup_paca(&boot_paca);
 197         fixup_boot_paca();
 198
 199         /* Initialize lockdep early or else spinlocks will blow */
 200         lockdep_init();
 201
 202         /* -------- printk is now safe to use ------- */
 203
 204         /* Enable early debugging if any specified (see udbg.h) */
 205         udbg_early_init();
 206
 207         DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
 208
 209         /*
 210          * Do early initialization using the flattened device
 211          * tree, such as retrieving the physical memory map or
 212          * calculating/retrieving the hash table size.
 213          */
 214         early_init_devtree(__va(dt_ptr));
 215
 216         /* Now we know the logical id of our boot cpu, setup the paca. */
 217         setup_paca(&paca[boot_cpuid]);
 218         fixup_boot_paca();
 219
 220         /* Probe the machine type */
 221         probe_machine();
 222
 223         setup_kdump_trampoline();
 224
 225         DBG("Found, Initializing memory management...\n");
 226
 227         /* Initialize the hash table or TLB handling */
 228         early_init_mmu();
 229
 230         /*
 231          * Reserve any gigantic pages requested on the command line.
 232          * memblock needs to have been initialized by the time this is
 233          * called since this will reserve memory.
 234          */
 235         reserve_hugetlb_gpages();
 236
 237         DBG(" <- early_setup()\n");
 238 }
 239
 240 #ifdef CONFIG_SMP
 241 void early_setup_secondary(void)
 242 {
 243         /* Mark interrupts enabled in PACA */
 244         get_paca()->soft_enabled = 0;
 245
 246         /* Initialize the hash table or TLB handling */
 247         early_init_mmu_secondary();
 248 }
 249
 250 #endif /* CONFIG_SMP */
 251
 252 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
 253 void smp_release_cpus(void)
 254 {
 255         unsigned long *ptr;
 256         int i;
 257
 258         DBG(" -> smp_release_cpus()\n");
 259
 260         /* All secondary cpus are spinning on a common spinloop, release them
 261          * all now so they can start to spin on their individual paca
 262          * spinloops. For non SMP kernels, the secondary cpus never get out
 263          * of the common spinloop.
 264          */
 265
 266         ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
 267                         - PHYSICAL_START);
 268         *ptr = __pa(generic_secondary_smp_init);
 269
 270         /* And wait a bit for them to catch up */
 271         for (i = 0; i < 100000; i++) {
 272                 mb();
 273                 HMT_low();
 274                 if (spinning_secondaries == 0)
 275                         break;
 276                 udelay(1);
 277         }
 278         DBG("spinning_secondaries = %d\n", spinning_secondaries);
 279
 280         DBG(" <- smp_release_cpus()\n");
 281 }
 282 #endif /* CONFIG_SMP || CONFIG_KEXEC */
 283
 284 /*
 285  * Initialize some remaining members of the ppc64_caches and systemcfg
 286  * structures
 287  * (at least until we get rid of them completely). This is mostly some
 288  * cache informations about the CPU that will be used by cache flush
 289  * routines and/or provided to userland
 290  */
 291 static void __init initialize_cache_info(void)
 292 {
 293         struct device_node *np;
 294         unsigned long num_cpus = 0;
 295
 296         DBG(" -> initialize_cache_info()\n");
 297
 298         for_each_node_by_type(np, "cpu") {
 299                 num_cpus += 1;
 300
 301                 /*
 302                  * We're assuming *all* of the CPUs have the same
 303                  * d-cache and i-cache sizes... -Peter
 304                  */
 305                 if (num_cpus == 1) {
 306                         const u32 *sizep, *lsizep;
 307                         u32 size, lsize;
 308
 309                         size = 0;
 310                         lsize = cur_cpu_spec->dcache_bsize;
 311                         sizep = of_get_property(np, "d-cache-size", NULL);
 312                         if (sizep != NULL)
 313                                 size = *sizep;
 314                         lsizep = of_get_property(np, "d-cache-block-size",
 315                                                  NULL);
 316                         /* fallback if block size missing */
 317                         if (lsizep == NULL)
 318                                 lsizep = of_get_property(np,
 319                                                          "d-cache-line-size",
 320                                                          NULL);
 321                         if (lsizep != NULL)
 322                                 lsize = *lsizep;
 323                         if (sizep == 0 || lsizep == 0)
 324                                 DBG("Argh, can't find dcache properties ! "
 325                                     "sizep: %p, lsizep: %p\n", sizep, lsizep);
 326
 327                         ppc64_caches.dsize = size;
 328                         ppc64_caches.dline_size = lsize;
 329                         ppc64_caches.log_dline_size = __ilog2(lsize);
 330                         ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
 331
 332                         size = 0;
 333                         lsize = cur_cpu_spec->icache_bsize;
 334                         sizep = of_get_property(np, "i-cache-size", NULL);
 335                         if (sizep != NULL)
 336                                 size = *sizep;
 337                         lsizep = of_get_property(np, "i-cache-block-size",
 338                                                  NULL);
 339                         if (lsizep == NULL)
 340                                 lsizep = of_get_property(np,
 341                                                          "i-cache-line-size",
 342                                                          NULL);
 343                         if (lsizep != NULL)
 344                                 lsize = *lsizep;
 345                         if (sizep == 0 || lsizep == 0)
 346                                 DBG("Argh, can't find icache properties ! "
 347                                     "sizep: %p, lsizep: %p\n", sizep, lsizep);
 348
 349                         ppc64_caches.isize = size;
 350                         ppc64_caches.iline_size = lsize;
 351                         ppc64_caches.log_iline_size = __ilog2(lsize);
 352                         ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
 353                 }
 354         }
 355
 356         DBG(" <- initialize_cache_info()\n");
 357 }
 358
 359
 360 /*
 361  * Do some initial setup of the system.  The parameters are those which
 362  * were passed in from the bootloader.
 363  */
 364 void __init setup_system(void)
 365 {
 366         DBG(" -> setup_system()\n");
 367
 368         /* Apply the CPUs-specific and firmware specific fixups to kernel
 369          * text (nop out sections not relevant to this CPU or this firmware)
 370          */
 371         do_feature_fixups(cur_cpu_spec->cpu_features,
 372                           &__start___ftr_fixup, &__stop___ftr_fixup);
 373         do_feature_fixups(cur_cpu_spec->mmu_features,
 374                           &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup);
 375         do_feature_fixups(powerpc_firmware_features,
 376                           &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
 377         do_lwsync_fixups(cur_cpu_spec->cpu_features,
 378                          &__start___lwsync_fixup, &__stop___lwsync_fixup);
 379         do_final_fixups();
 380
 381         /*
 382          * Unflatten the device-tree passed by prom_init or kexec
 383          */
 384         unflatten_device_tree();
 385
 386         /*
 387          * Fill the ppc64_caches & systemcfg structures with informations
 388          * retrieved from the device-tree.
 389          */
 390         initialize_cache_info();
 391
 392 #ifdef CONFIG_PPC_RTAS
 393         /*
 394          * Initialize RTAS if available
 395          */
 396         rtas_initialize();
 397 #endif /* CONFIG_PPC_RTAS */
 398
 399         /*
 400          * Check if we have an initrd provided via the device-tree
 401          */
 402         check_for_initrd();
 403
 404         /*
 405          * Do some platform specific early initializations, that includes
 406          * setting up the hash table pointers. It also sets up some interrupt-mapping
 407          * related options that will be used by finish_device_tree()
 408          */
 409         if (ppc_md.init_early)
 410                 ppc_md.init_early();
 411
 412         /*
 413          * We can discover serial ports now since the above did setup the
 414          * hash table management for us, thus ioremap works. We do that early
 415          * so that further code can be debugged
 416          */
 417         find_legacy_serial_ports();
 418
 419         /*
 420          * Register early console
 421          */
 422         register_early_udbg_console();
 423
 424         /*
 425          * Initialize xmon
 426          */
 427         xmon_setup();
 428
 429         smp_setup_cpu_maps();
 430         check_smt_enabled();
 431
 432 #ifdef CONFIG_SMP
 433         /* Release secondary cpus out of their spinloops at 0x60 now that
 434          * we can map physical -> logical CPU ids
 435          */
 436         smp_release_cpus();
 437 #endif
 438
 439         printk("Starting Linux PPC64 %s\n", init_utsname()->version);
 440
 441         printk("-----------------------------------------------------\n");
 442         printk("ppc64_pft_size                = 0x%llx\n", ppc64_pft_size);
 443         printk("physicalMemorySize            = 0x%llx\n", memblock_phys_mem_size());
 444         if (ppc64_caches.dline_size != 0x80)
 445                 printk("ppc64_caches.dcache_line_size = 0x%x\n",
 446                        ppc64_caches.dline_size);
 447         if (ppc64_caches.iline_size != 0x80)
 448                 printk("ppc64_caches.icache_line_size = 0x%x\n",
 449                        ppc64_caches.iline_size);
 450 #ifdef CONFIG_PPC_STD_MMU_64
 451         if (htab_address)
 452                 printk("htab_address                  = 0x%p\n", htab_address);
 453         printk("htab_hash_mask                = 0x%lx\n", htab_hash_mask);
 454 #endif /* CONFIG_PPC_STD_MMU_64 */
 455         if (PHYSICAL_START > 0)
 456                 printk("physical_start                = 0x%llx\n",
 457                        (unsigned long long)PHYSICAL_START);
 458         printk("-----------------------------------------------------\n");
 459
 460         DBG(" <- setup_system()\n");
 461 }
 462
 463 /* This returns the limit below which memory accesses to the linear
 464  * mapping are guarnateed not to cause a TLB or SLB miss. This is
 465  * used to allocate interrupt or emergency stacks for which our
 466  * exception entry path doesn't deal with being interrupted.
 467  */
 468 static u64 safe_stack_limit(void)
 469 {
 470 #ifdef CONFIG_PPC_BOOK3E
 471         /* Freescale BookE bolts the entire linear mapping */
 472         if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
 473                 return linear_map_top;
 474         /* Other BookE, we assume the first GB is bolted */
 475         return 1ul << 30;
 476 #else
 477         /* BookS, the first segment is bolted */
 478         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
 479                 return 1UL << SID_SHIFT_1T;
 480         return 1UL << SID_SHIFT;
 481 #endif
 482 }
 483
 484 static void __init irqstack_early_init(void)
 485 {
 486         u64 limit = safe_stack_limit();
 487         unsigned int i;
 488
 489         /*
 490          * Interrupt stacks must be in the first segment since we
 491          * cannot afford to take SLB misses on them.
 492          */
 493         for_each_possible_cpu(i) {
 494                 softirq_ctx[i] = (struct thread_info *)
 495                         __va(memblock_alloc_base(THREAD_SIZE,
 496                                             THREAD_SIZE, limit));
 497                 hardirq_ctx[i] = (struct thread_info *)
 498                         __va(memblock_alloc_base(THREAD_SIZE,
 499                                             THREAD_SIZE, limit));
 500         }
 501 }
 502
 503 #ifdef CONFIG_PPC_BOOK3E
 504 static void __init exc_lvl_early_init(void)
 505 {
 506         extern unsigned int interrupt_base_book3e;
 507         extern unsigned int exc_debug_debug_book3e;
 508
 509         unsigned int i;
 510
 511         for_each_possible_cpu(i) {
 512                 critirq_ctx[i] = (struct thread_info *)
 513                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 514                 dbgirq_ctx[i] = (struct thread_info *)
 515                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 516                 mcheckirq_ctx[i] = (struct thread_info *)
 517                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 518         }
 519
 520         if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
 521                 patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1,
 522                              (unsigned long)&exc_debug_debug_book3e, 0);
 523 }
 524 #else
 525 #define exc_lvl_early_init()
 526 #endif
 527
 528 /*
 529  * Stack space used when we detect a bad kernel stack pointer, and
 530  * early in SMP boots before relocation is enabled.
 531  */
 532 static void __init emergency_stack_init(void)
 533 {
 534         u64 limit;
 535         unsigned int i;
 536
 537         /*
 538          * Emergency stacks must be under 256MB, we cannot afford to take
 539          * SLB misses on them. The ABI also requires them to be 128-byte
 540          * aligned.
 541          *
 542          * Since we use these as temporary stacks during secondary CPU
 543          * bringup, we need to get at them in real mode. This means they
 544          * must also be within the RMO region.
 545          */
 546         limit = min(safe_stack_limit(), ppc64_rma_size);
 547
 548         for_each_possible_cpu(i) {
 549                 unsigned long sp;
 550                 sp  = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
 551                 sp += THREAD_SIZE;
 552                 paca[i].emergency_sp = __va(sp);
 553         }
 554 }
 555
 556 /*
 557  * Called into from start_kernel this initializes bootmem, which is used
 558  * to manage page allocation until mem_init is called.
 559  */
 560 void __init setup_arch(char **cmdline_p)
 561 {
 562         ppc64_boot_msg(0x12, "Setup Arch");
 563
 564         *cmdline_p = cmd_line;
 565
 566         /*
 567          * Set cache line size based on type of cpu as a default.
 568          * Systems with OF can look in the properties on the cpu node(s)
 569          * for a possibly more accurate value.
 570          */
 571         dcache_bsize = ppc64_caches.dline_size;
 572         icache_bsize = ppc64_caches.iline_size;
 573
 574         /* reboot on panic */
 575         panic_timeout = 180;
 576
 577         if (ppc_md.panic)
 578                 setup_panic();
 579
 580         init_mm.start_code = (unsigned long)_stext;
 581         init_mm.end_code = (unsigned long) _etext;
 582         init_mm.end_data = (unsigned long) _edata;
 583         init_mm.brk = klimit;
 584
 585         irqstack_early_init();
 586         exc_lvl_early_init();
 587         emergency_stack_init();
 588
 589 #ifdef CONFIG_PPC_STD_MMU_64
 590         stabs_alloc();
 591 #endif
 592         /* set up the bootmem stuff with available memory */
 593         do_init_bootmem();
 594         sparse_init();
 595
 596 #ifdef CONFIG_DUMMY_CONSOLE
 597         conswitchp = &dummy_con;
 598 #endif
 599
 600         if (ppc_md.setup_arch)
 601                 ppc_md.setup_arch();
 602
 603         paging_init();
 604
 605         /* Initialize the MMU context management stuff */
 606         mmu_context_init();
 607
 608         kvm_linear_init();
 609
 610         /* Interrupt code needs to be 64K-aligned */
 611         if ((unsigned long)_stext & 0xffff)
 612                 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
 613                       (unsigned long)_stext);
 614
 615         ppc64_boot_msg(0x15, "Setup Done");
 616 }
 617
 618
 619 /* ToDo: do something useful if ppc_md is not yet setup. */
 620 #define PPC64_LINUX_FUNCTION 0x0f000000
 621 #define PPC64_IPL_MESSAGE 0xc0000000
 622 #define PPC64_TERM_MESSAGE 0xb0000000
 623
 624 static void ppc64_do_msg(unsigned int src, const char *msg)
 625 {
 626         if (ppc_md.progress) {
 627                 char buf[128];
 628
 629                 sprintf(buf, "%08X\n", src);
 630                 ppc_md.progress(buf, 0);
 631                 snprintf(buf, 128, "%s", msg);
 632                 ppc_md.progress(buf, 0);
 633         }
 634 }
 635
 636 /* Print a boot progress message. */
 637 void ppc64_boot_msg(unsigned int src, const char *msg)
 638 {
 639         ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg);
 640         printk("[boot]%04x %s\n", src, msg);
 641 }
 642
 643 #ifdef CONFIG_SMP
 644 #define PCPU_DYN_SIZE           ()
 645
 646 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
 647 {
 648         return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
 649                                     __pa(MAX_DMA_ADDRESS));
 650 }
 651
 652 static void __init pcpu_fc_free(void *ptr, size_t size)
 653 {
 654         free_bootmem(__pa(ptr), size);
 655 }
 656
 657 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
 658 {
 659         if (cpu_to_node(from) == cpu_to_node(to))
 660                 return LOCAL_DISTANCE;
 661         else
 662                 return REMOTE_DISTANCE;
 663 }
 664
 665 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
 666 EXPORT_SYMBOL(__per_cpu_offset);
 667
 668 void __init setup_per_cpu_areas(void)
 669 {
 670         const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
 671         size_t atom_size;
 672         unsigned long delta;
 673         unsigned int cpu;
 674         int rc;
 675
 676         /*
 677          * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
 678          * to group units.  For larger mappings, use 1M atom which
 679          * should be large enough to contain a number of units.
 680          */
 681         if (mmu_linear_psize == MMU_PAGE_4K)
 682                 atom_size = PAGE_SIZE;
 683         else
 684                 atom_size = 1 << 20;
 685
 686         rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
 687                                     pcpu_fc_alloc, pcpu_fc_free);
 688         if (rc < 0)
 689                 panic("cannot initialize percpu area (err=%d)", rc);
 690
 691         delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
 692         for_each_possible_cpu(cpu) {
 693                 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
 694                 paca[cpu].data_offset = __per_cpu_offset[cpu];
 695         }
 696 }
 697 #endif
 698
 699
 700 #ifdef CONFIG_PPC_INDIRECT_IO
 701 struct ppc_pci_io ppc_pci_io;
 702 EXPORT_SYMBOL(ppc_pci_io);
 703 #endif /* CONFIG_PPC_INDIRECT_IO */
 704