1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from "arch/i386/kernel/process.c"
4 * Copyright (C) 1995 Linus Torvalds
6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7 * Paul Mackerras (paulus@cs.anu.edu.au)
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/hw_breakpoint.h>
38 #include <linux/uaccess.h>
39 #include <linux/pkeys.h>
40 #include <linux/seq_buf.h>
42 #include <asm/interrupt.h>
44 #include <asm/processor.h>
46 #include <asm/machdep.h>
48 #include <asm/runlatch.h>
49 #include <asm/syscalls.h>
50 #include <asm/switch_to.h>
52 #include <asm/debug.h>
54 #include <asm/firmware.h>
55 #include <asm/hw_irq.h>
57 #include <asm/code-patching.h>
59 #include <asm/livepatch.h>
60 #include <asm/cpu_has_feature.h>
61 #include <asm/asm-prototypes.h>
62 #include <asm/stacktrace.h>
63 #include <asm/hw_breakpoint.h>
65 #include <linux/kprobes.h>
66 #include <linux/kdebug.h>
68 /* Transactional Memory debug */
70 #define TM_DEBUG(x...) printk(KERN_INFO x)
72 #define TM_DEBUG(x...) do { } while(0)
75 extern unsigned long _get_SP(void);
77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
79 * Are we running in "Suspend disabled" mode? If so we have to block any
80 * sigreturn that would get us into suspended state, and we also warn in some
81 * other paths that we should never reach with suspend disabled.
83 bool tm_suspend_disabled __ro_after_init = false;
85 static void check_if_tm_restore_required(struct task_struct *tsk)
88 * If we are saving the current thread's registers, and the
89 * thread is in a transactional state, set the TIF_RESTORE_TM
90 * bit so that we know to restore the registers before
91 * returning to userspace.
93 if (tsk == current && tsk->thread.regs &&
94 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
95 !test_thread_flag(TIF_RESTORE_TM)) {
96 regs_set_return_msr(&tsk->thread.ckpt_regs,
97 tsk->thread.regs->msr);
98 set_thread_flag(TIF_RESTORE_TM);
103 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
104 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
106 bool strict_msr_control;
107 EXPORT_SYMBOL(strict_msr_control);
109 static int __init enable_strict_msr_control(char *str)
111 strict_msr_control = true;
112 pr_info("Enabling strict facility control\n");
116 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
118 /* notrace because it's called by restore_math */
119 unsigned long notrace msr_check_and_set(unsigned long bits)
121 unsigned long oldmsr = mfmsr();
122 unsigned long newmsr;
124 newmsr = oldmsr | bits;
126 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
129 if (oldmsr != newmsr)
134 EXPORT_SYMBOL_GPL(msr_check_and_set);
136 /* notrace because it's called by restore_math */
137 void notrace __msr_check_and_clear(unsigned long bits)
139 unsigned long oldmsr = mfmsr();
140 unsigned long newmsr;
142 newmsr = oldmsr & ~bits;
144 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
147 if (oldmsr != newmsr)
150 EXPORT_SYMBOL(__msr_check_and_clear);
152 #ifdef CONFIG_PPC_FPU
153 static void __giveup_fpu(struct task_struct *tsk)
158 msr = tsk->thread.regs->msr;
159 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
160 if (cpu_has_feature(CPU_FTR_VSX))
162 regs_set_return_msr(tsk->thread.regs, msr);
165 void giveup_fpu(struct task_struct *tsk)
167 check_if_tm_restore_required(tsk);
169 msr_check_and_set(MSR_FP);
171 msr_check_and_clear(MSR_FP);
173 EXPORT_SYMBOL(giveup_fpu);
176 * Make sure the floating-point register state in the
177 * the thread_struct is up to date for task tsk.
179 void flush_fp_to_thread(struct task_struct *tsk)
181 if (tsk->thread.regs) {
183 * We need to disable preemption here because if we didn't,
184 * another process could get scheduled after the regs->msr
185 * test but before we have finished saving the FP registers
186 * to the thread_struct. That process could take over the
187 * FPU, and then when we get scheduled again we would store
188 * bogus values for the remaining FP registers.
191 if (tsk->thread.regs->msr & MSR_FP) {
193 * This should only ever be called for current or
194 * for a stopped child process. Since we save away
195 * the FP register state on context switch,
196 * there is something wrong if a stopped child appears
197 * to still have its FP state in the CPU registers.
199 BUG_ON(tsk != current);
205 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
207 void enable_kernel_fp(void)
209 unsigned long cpumsr;
211 WARN_ON(preemptible());
213 cpumsr = msr_check_and_set(MSR_FP);
215 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
216 check_if_tm_restore_required(current);
218 * If a thread has already been reclaimed then the
219 * checkpointed registers are on the CPU but have definitely
220 * been saved by the reclaim code. Don't need to and *cannot*
221 * giveup as this would save to the 'live' structure not the
222 * checkpointed structure.
224 if (!MSR_TM_ACTIVE(cpumsr) &&
225 MSR_TM_ACTIVE(current->thread.regs->msr))
227 __giveup_fpu(current);
230 EXPORT_SYMBOL(enable_kernel_fp);
232 static inline void __giveup_fpu(struct task_struct *tsk) { }
233 #endif /* CONFIG_PPC_FPU */
235 #ifdef CONFIG_ALTIVEC
236 static void __giveup_altivec(struct task_struct *tsk)
241 msr = tsk->thread.regs->msr;
243 if (cpu_has_feature(CPU_FTR_VSX))
245 regs_set_return_msr(tsk->thread.regs, msr);
248 void giveup_altivec(struct task_struct *tsk)
250 check_if_tm_restore_required(tsk);
252 msr_check_and_set(MSR_VEC);
253 __giveup_altivec(tsk);
254 msr_check_and_clear(MSR_VEC);
256 EXPORT_SYMBOL(giveup_altivec);
258 void enable_kernel_altivec(void)
260 unsigned long cpumsr;
262 WARN_ON(preemptible());
264 cpumsr = msr_check_and_set(MSR_VEC);
266 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
267 check_if_tm_restore_required(current);
269 * If a thread has already been reclaimed then the
270 * checkpointed registers are on the CPU but have definitely
271 * been saved by the reclaim code. Don't need to and *cannot*
272 * giveup as this would save to the 'live' structure not the
273 * checkpointed structure.
275 if (!MSR_TM_ACTIVE(cpumsr) &&
276 MSR_TM_ACTIVE(current->thread.regs->msr))
278 __giveup_altivec(current);
281 EXPORT_SYMBOL(enable_kernel_altivec);
284 * Make sure the VMX/Altivec register state in the
285 * the thread_struct is up to date for task tsk.
287 void flush_altivec_to_thread(struct task_struct *tsk)
289 if (tsk->thread.regs) {
291 if (tsk->thread.regs->msr & MSR_VEC) {
292 BUG_ON(tsk != current);
298 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
299 #endif /* CONFIG_ALTIVEC */
302 static void __giveup_vsx(struct task_struct *tsk)
304 unsigned long msr = tsk->thread.regs->msr;
307 * We should never be setting MSR_VSX without also setting
310 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
312 /* __giveup_fpu will clear MSR_VSX */
316 __giveup_altivec(tsk);
319 static void giveup_vsx(struct task_struct *tsk)
321 check_if_tm_restore_required(tsk);
323 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
325 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
328 void enable_kernel_vsx(void)
330 unsigned long cpumsr;
332 WARN_ON(preemptible());
334 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
336 if (current->thread.regs &&
337 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
338 check_if_tm_restore_required(current);
340 * If a thread has already been reclaimed then the
341 * checkpointed registers are on the CPU but have definitely
342 * been saved by the reclaim code. Don't need to and *cannot*
343 * giveup as this would save to the 'live' structure not the
344 * checkpointed structure.
346 if (!MSR_TM_ACTIVE(cpumsr) &&
347 MSR_TM_ACTIVE(current->thread.regs->msr))
349 __giveup_vsx(current);
352 EXPORT_SYMBOL(enable_kernel_vsx);
354 void flush_vsx_to_thread(struct task_struct *tsk)
356 if (tsk->thread.regs) {
358 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
359 BUG_ON(tsk != current);
365 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
366 #endif /* CONFIG_VSX */
369 void giveup_spe(struct task_struct *tsk)
371 check_if_tm_restore_required(tsk);
373 msr_check_and_set(MSR_SPE);
375 msr_check_and_clear(MSR_SPE);
377 EXPORT_SYMBOL(giveup_spe);
379 void enable_kernel_spe(void)
381 WARN_ON(preemptible());
383 msr_check_and_set(MSR_SPE);
385 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
386 check_if_tm_restore_required(current);
387 __giveup_spe(current);
390 EXPORT_SYMBOL(enable_kernel_spe);
392 void flush_spe_to_thread(struct task_struct *tsk)
394 if (tsk->thread.regs) {
396 if (tsk->thread.regs->msr & MSR_SPE) {
397 BUG_ON(tsk != current);
398 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
404 #endif /* CONFIG_SPE */
406 static unsigned long msr_all_available;
408 static int __init init_msr_all_available(void)
410 if (IS_ENABLED(CONFIG_PPC_FPU))
411 msr_all_available |= MSR_FP;
412 if (cpu_has_feature(CPU_FTR_ALTIVEC))
413 msr_all_available |= MSR_VEC;
414 if (cpu_has_feature(CPU_FTR_VSX))
415 msr_all_available |= MSR_VSX;
416 if (cpu_has_feature(CPU_FTR_SPE))
417 msr_all_available |= MSR_SPE;
421 early_initcall(init_msr_all_available);
423 void giveup_all(struct task_struct *tsk)
425 unsigned long usermsr;
427 if (!tsk->thread.regs)
430 check_if_tm_restore_required(tsk);
432 usermsr = tsk->thread.regs->msr;
434 if ((usermsr & msr_all_available) == 0)
437 msr_check_and_set(msr_all_available);
439 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
441 if (usermsr & MSR_FP)
443 if (usermsr & MSR_VEC)
444 __giveup_altivec(tsk);
445 if (usermsr & MSR_SPE)
448 msr_check_and_clear(msr_all_available);
450 EXPORT_SYMBOL(giveup_all);
452 #ifdef CONFIG_PPC_BOOK3S_64
453 #ifdef CONFIG_PPC_FPU
454 static bool should_restore_fp(void)
456 if (current->thread.load_fp) {
457 current->thread.load_fp++;
463 static void do_restore_fp(void)
465 load_fp_state(¤t->thread.fp_state);
468 static bool should_restore_fp(void) { return false; }
469 static void do_restore_fp(void) { }
470 #endif /* CONFIG_PPC_FPU */
472 #ifdef CONFIG_ALTIVEC
473 static bool should_restore_altivec(void)
475 if (cpu_has_feature(CPU_FTR_ALTIVEC) && (current->thread.load_vec)) {
476 current->thread.load_vec++;
482 static void do_restore_altivec(void)
484 load_vr_state(¤t->thread.vr_state);
485 current->thread.used_vr = 1;
488 static bool should_restore_altivec(void) { return false; }
489 static void do_restore_altivec(void) { }
490 #endif /* CONFIG_ALTIVEC */
492 static bool should_restore_vsx(void)
494 if (cpu_has_feature(CPU_FTR_VSX))
499 static void do_restore_vsx(void)
501 current->thread.used_vsr = 1;
504 static void do_restore_vsx(void) { }
505 #endif /* CONFIG_VSX */
508 * The exception exit path calls restore_math() with interrupts hard disabled
509 * but the soft irq state not "reconciled". ftrace code that calls
510 * local_irq_save/restore causes warnings.
512 * Rather than complicate the exit path, just don't trace restore_math. This
513 * could be done by having ftrace entry code check for this un-reconciled
514 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
515 * temporarily fix it up for the duration of the ftrace call.
517 void notrace restore_math(struct pt_regs *regs)
520 unsigned long new_msr = 0;
525 * new_msr tracks the facilities that are to be restored. Only reload
526 * if the bit is not set in the user MSR (if it is set, the registers
527 * are live for the user thread).
529 if ((!(msr & MSR_FP)) && should_restore_fp())
532 if ((!(msr & MSR_VEC)) && should_restore_altivec())
535 if ((!(msr & MSR_VSX)) && should_restore_vsx()) {
536 if (((msr | new_msr) & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC))
541 unsigned long fpexc_mode = 0;
543 msr_check_and_set(new_msr);
545 if (new_msr & MSR_FP) {
548 // This also covers VSX, because VSX implies FP
549 fpexc_mode = current->thread.fpexc_mode;
552 if (new_msr & MSR_VEC)
553 do_restore_altivec();
555 if (new_msr & MSR_VSX)
558 msr_check_and_clear(new_msr);
560 regs_set_return_msr(regs, regs->msr | new_msr | fpexc_mode);
563 #endif /* CONFIG_PPC_BOOK3S_64 */
565 static void save_all(struct task_struct *tsk)
567 unsigned long usermsr;
569 if (!tsk->thread.regs)
572 usermsr = tsk->thread.regs->msr;
574 if ((usermsr & msr_all_available) == 0)
577 msr_check_and_set(msr_all_available);
579 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
581 if (usermsr & MSR_FP)
584 if (usermsr & MSR_VEC)
587 if (usermsr & MSR_SPE)
590 msr_check_and_clear(msr_all_available);
593 void flush_all_to_thread(struct task_struct *tsk)
595 if (tsk->thread.regs) {
597 BUG_ON(tsk != current);
599 if (tsk->thread.regs->msr & MSR_SPE)
600 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
607 EXPORT_SYMBOL(flush_all_to_thread);
609 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
610 void do_send_trap(struct pt_regs *regs, unsigned long address,
611 unsigned long error_code, int breakpt)
613 current->thread.trap_nr = TRAP_HWBKPT;
614 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
615 11, SIGSEGV) == NOTIFY_STOP)
618 /* Deliver the signal to userspace */
619 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
620 (void __user *)address);
622 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
624 static void do_break_handler(struct pt_regs *regs)
626 struct arch_hw_breakpoint null_brk = {0};
627 struct arch_hw_breakpoint *info;
628 ppc_inst_t instr = ppc_inst(0);
635 * If underneath hw supports only one watchpoint, we know it
636 * caused exception. 8xx also falls into this category.
638 if (nr_wp_slots() == 1) {
639 __set_breakpoint(0, &null_brk);
640 current->thread.hw_brk[0] = null_brk;
641 current->thread.hw_brk[0].flags |= HW_BRK_FLAG_DISABLED;
645 /* Otherwise find out which DAWR caused exception and disable it. */
646 wp_get_instr_detail(regs, &instr, &type, &size, &ea);
648 for (i = 0; i < nr_wp_slots(); i++) {
649 info = ¤t->thread.hw_brk[i];
653 if (wp_check_constraints(regs, instr, ea, type, size, info)) {
654 __set_breakpoint(i, &null_brk);
655 current->thread.hw_brk[i] = null_brk;
656 current->thread.hw_brk[i].flags |= HW_BRK_FLAG_DISABLED;
661 DEFINE_INTERRUPT_HANDLER(do_break)
663 current->thread.trap_nr = TRAP_HWBKPT;
664 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, regs->dsisr,
665 11, SIGSEGV) == NOTIFY_STOP)
668 if (debugger_break_match(regs))
672 * We reach here only when watchpoint exception is generated by ptrace
673 * event (or hw is buggy!). Now if CONFIG_HAVE_HW_BREAKPOINT is set,
674 * watchpoint is already handled by hw_breakpoint_handler() so we don't
675 * have to do anything. But when CONFIG_HAVE_HW_BREAKPOINT is not set,
676 * we need to manually handle the watchpoint here.
678 if (!IS_ENABLED(CONFIG_HAVE_HW_BREAKPOINT))
679 do_break_handler(regs);
681 /* Deliver the signal to userspace */
682 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)regs->dar);
684 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
686 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]);
688 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
690 * Set the debug registers back to their default "safe" values.
692 static void set_debug_reg_defaults(struct thread_struct *thread)
694 thread->debug.iac1 = thread->debug.iac2 = 0;
695 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
696 thread->debug.iac3 = thread->debug.iac4 = 0;
698 thread->debug.dac1 = thread->debug.dac2 = 0;
699 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
700 thread->debug.dvc1 = thread->debug.dvc2 = 0;
702 thread->debug.dbcr0 = 0;
705 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
707 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
708 DBCR1_IAC3US | DBCR1_IAC4US;
710 * Force Data Address Compare User/Supervisor bits to be User-only
711 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
713 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
715 thread->debug.dbcr1 = 0;
719 static void prime_debug_regs(struct debug_reg *debug)
722 * We could have inherited MSR_DE from userspace, since
723 * it doesn't get cleared on exception entry. Make sure
724 * MSR_DE is clear before we enable any debug events.
726 mtmsr(mfmsr() & ~MSR_DE);
728 mtspr(SPRN_IAC1, debug->iac1);
729 mtspr(SPRN_IAC2, debug->iac2);
730 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
731 mtspr(SPRN_IAC3, debug->iac3);
732 mtspr(SPRN_IAC4, debug->iac4);
734 mtspr(SPRN_DAC1, debug->dac1);
735 mtspr(SPRN_DAC2, debug->dac2);
736 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
737 mtspr(SPRN_DVC1, debug->dvc1);
738 mtspr(SPRN_DVC2, debug->dvc2);
740 mtspr(SPRN_DBCR0, debug->dbcr0);
741 mtspr(SPRN_DBCR1, debug->dbcr1);
743 mtspr(SPRN_DBCR2, debug->dbcr2);
747 * Unless neither the old or new thread are making use of the
748 * debug registers, set the debug registers from the values
749 * stored in the new thread.
751 void switch_booke_debug_regs(struct debug_reg *new_debug)
753 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
754 || (new_debug->dbcr0 & DBCR0_IDM))
755 prime_debug_regs(new_debug);
757 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
758 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
759 #ifndef CONFIG_HAVE_HW_BREAKPOINT
760 static void set_breakpoint(int i, struct arch_hw_breakpoint *brk)
763 __set_breakpoint(i, brk);
767 static void set_debug_reg_defaults(struct thread_struct *thread)
770 struct arch_hw_breakpoint null_brk = {0};
772 for (i = 0; i < nr_wp_slots(); i++) {
773 thread->hw_brk[i] = null_brk;
774 if (ppc_breakpoint_available())
775 set_breakpoint(i, &thread->hw_brk[i]);
779 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
780 struct arch_hw_breakpoint *b)
782 if (a->address != b->address)
784 if (a->type != b->type)
786 if (a->len != b->len)
788 /* no need to check hw_len. it's calculated from address and len */
792 static void switch_hw_breakpoint(struct task_struct *new)
796 for (i = 0; i < nr_wp_slots(); i++) {
797 if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]),
798 &new->thread.hw_brk[i])))
801 __set_breakpoint(i, &new->thread.hw_brk[i]);
804 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
805 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
807 static inline int set_dabr(struct arch_hw_breakpoint *brk)
809 unsigned long dabr, dabrx;
811 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
812 dabrx = ((brk->type >> 3) & 0x7);
815 return ppc_md.set_dabr(dabr, dabrx);
817 if (IS_ENABLED(CONFIG_PPC_ADV_DEBUG_REGS)) {
818 mtspr(SPRN_DAC1, dabr);
819 if (IS_ENABLED(CONFIG_PPC_47x))
822 } else if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
823 mtspr(SPRN_DABR, dabr);
824 if (cpu_has_feature(CPU_FTR_DABRX))
825 mtspr(SPRN_DABRX, dabrx);
832 static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk)
834 unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW |
836 unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN;
837 unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE);
838 unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE);
841 lctrl2 |= LCTRL2_LW0LA_F;
842 else if (end_addr == 0)
843 lctrl2 |= LCTRL2_LW0LA_E;
845 lctrl2 |= LCTRL2_LW0LA_EandF;
847 mtspr(SPRN_LCTRL2, 0);
849 if ((brk->type & HW_BRK_TYPE_RDWR) == 0)
852 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
853 lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO;
854 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
855 lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO;
857 mtspr(SPRN_CMPE, start_addr - 1);
858 mtspr(SPRN_CMPF, end_addr);
859 mtspr(SPRN_LCTRL1, lctrl1);
860 mtspr(SPRN_LCTRL2, lctrl2);
865 void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk)
867 memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk));
872 else if (IS_ENABLED(CONFIG_PPC_8xx))
873 set_breakpoint_8xx(brk);
874 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
878 // Shouldn't happen due to higher level checks
882 /* Check if we have DAWR or DABR hardware */
883 bool ppc_breakpoint_available(void)
886 return true; /* POWER8 DAWR or POWER9 forced DAWR */
887 if (cpu_has_feature(CPU_FTR_ARCH_207S))
888 return false; /* POWER9 with DAWR disabled */
889 /* DABR: Everything but POWER8 and POWER9 */
892 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
894 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
896 static inline bool tm_enabled(struct task_struct *tsk)
898 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
901 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
904 * Use the current MSR TM suspended bit to track if we have
905 * checkpointed state outstanding.
906 * On signal delivery, we'd normally reclaim the checkpointed
907 * state to obtain stack pointer (see:get_tm_stackpointer()).
908 * This will then directly return to userspace without going
909 * through __switch_to(). However, if the stack frame is bad,
910 * we need to exit this thread which calls __switch_to() which
911 * will again attempt to reclaim the already saved tm state.
912 * Hence we need to check that we've not already reclaimed
914 * We do this using the current MSR, rather tracking it in
915 * some specific thread_struct bit, as it has the additional
916 * benefit of checking for a potential TM bad thing exception.
918 if (!MSR_TM_SUSPENDED(mfmsr()))
921 giveup_all(container_of(thr, struct task_struct, thread));
923 tm_reclaim(thr, cause);
926 * If we are in a transaction and FP is off then we can't have
927 * used FP inside that transaction. Hence the checkpointed
928 * state is the same as the live state. We need to copy the
929 * live state to the checkpointed state so that when the
930 * transaction is restored, the checkpointed state is correct
931 * and the aborted transaction sees the correct state. We use
932 * ckpt_regs.msr here as that's what tm_reclaim will use to
933 * determine if it's going to write the checkpointed state or
934 * not. So either this will write the checkpointed registers,
935 * or reclaim will. Similarly for VMX.
937 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
938 memcpy(&thr->ckfp_state, &thr->fp_state,
939 sizeof(struct thread_fp_state));
940 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
941 memcpy(&thr->ckvr_state, &thr->vr_state,
942 sizeof(struct thread_vr_state));
945 void tm_reclaim_current(uint8_t cause)
948 tm_reclaim_thread(¤t->thread, cause);
951 static inline void tm_reclaim_task(struct task_struct *tsk)
953 /* We have to work out if we're switching from/to a task that's in the
954 * middle of a transaction.
956 * In switching we need to maintain a 2nd register state as
957 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
958 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
961 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
963 struct thread_struct *thr = &tsk->thread;
968 if (!MSR_TM_ACTIVE(thr->regs->msr))
969 goto out_and_saveregs;
971 WARN_ON(tm_suspend_disabled);
973 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
974 "ccr=%lx, msr=%lx, trap=%lx)\n",
975 tsk->pid, thr->regs->nip,
976 thr->regs->ccr, thr->regs->msr,
979 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
981 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
985 /* Always save the regs here, even if a transaction's not active.
986 * This context-switches a thread's TM info SPRs. We do it here to
987 * be consistent with the restore path (in recheckpoint) which
988 * cannot happen later in _switch().
993 extern void __tm_recheckpoint(struct thread_struct *thread);
995 void tm_recheckpoint(struct thread_struct *thread)
999 if (!(thread->regs->msr & MSR_TM))
1002 /* We really can't be interrupted here as the TEXASR registers can't
1003 * change and later in the trecheckpoint code, we have a userspace R1.
1004 * So let's hard disable over this region.
1006 local_irq_save(flags);
1009 /* The TM SPRs are restored here, so that TEXASR.FS can be set
1010 * before the trecheckpoint and no explosion occurs.
1012 tm_restore_sprs(thread);
1014 __tm_recheckpoint(thread);
1016 local_irq_restore(flags);
1019 static inline void tm_recheckpoint_new_task(struct task_struct *new)
1021 if (!cpu_has_feature(CPU_FTR_TM))
1024 /* Recheckpoint the registers of the thread we're about to switch to.
1026 * If the task was using FP, we non-lazily reload both the original and
1027 * the speculative FP register states. This is because the kernel
1028 * doesn't see if/when a TM rollback occurs, so if we take an FP
1029 * unavailable later, we are unable to determine which set of FP regs
1030 * need to be restored.
1032 if (!tm_enabled(new))
1035 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
1036 tm_restore_sprs(&new->thread);
1039 /* Recheckpoint to restore original checkpointed register state. */
1040 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1041 new->pid, new->thread.regs->msr);
1043 tm_recheckpoint(&new->thread);
1046 * The checkpointed state has been restored but the live state has
1047 * not, ensure all the math functionality is turned off to trigger
1048 * restore_math() to reload.
1050 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1052 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1053 "(kernel msr 0x%lx)\n",
1057 static inline void __switch_to_tm(struct task_struct *prev,
1058 struct task_struct *new)
1060 if (cpu_has_feature(CPU_FTR_TM)) {
1061 if (tm_enabled(prev) || tm_enabled(new))
1064 if (tm_enabled(prev)) {
1065 prev->thread.load_tm++;
1066 tm_reclaim_task(prev);
1067 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1068 prev->thread.regs->msr &= ~MSR_TM;
1071 tm_recheckpoint_new_task(new);
1076 * This is called if we are on the way out to userspace and the
1077 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1078 * FP and/or vector state and does so if necessary.
1079 * If userspace is inside a transaction (whether active or
1080 * suspended) and FP/VMX/VSX instructions have ever been enabled
1081 * inside that transaction, then we have to keep them enabled
1082 * and keep the FP/VMX/VSX state loaded while ever the transaction
1083 * continues. The reason is that if we didn't, and subsequently
1084 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1085 * we don't know whether it's the same transaction, and thus we
1086 * don't know which of the checkpointed state and the transactional
1089 void restore_tm_state(struct pt_regs *regs)
1091 unsigned long msr_diff;
1094 * This is the only moment we should clear TIF_RESTORE_TM as
1095 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1096 * again, anything else could lead to an incorrect ckpt_msr being
1097 * saved and therefore incorrect signal contexts.
1099 clear_thread_flag(TIF_RESTORE_TM);
1100 if (!MSR_TM_ACTIVE(regs->msr))
1103 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1104 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1106 /* Ensure that restore_math() will restore */
1107 if (msr_diff & MSR_FP)
1108 current->thread.load_fp = 1;
1109 #ifdef CONFIG_ALTIVEC
1110 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1111 current->thread.load_vec = 1;
1115 regs_set_return_msr(regs, regs->msr | msr_diff);
1118 #else /* !CONFIG_PPC_TRANSACTIONAL_MEM */
1119 #define tm_recheckpoint_new_task(new)
1120 #define __switch_to_tm(prev, new)
1121 void tm_reclaim_current(uint8_t cause) {}
1122 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1124 static inline void save_sprs(struct thread_struct *t)
1126 #ifdef CONFIG_ALTIVEC
1127 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1128 t->vrsave = mfspr(SPRN_VRSAVE);
1131 if (cpu_has_feature(CPU_FTR_SPE))
1132 t->spefscr = mfspr(SPRN_SPEFSCR);
1134 #ifdef CONFIG_PPC_BOOK3S_64
1135 if (cpu_has_feature(CPU_FTR_DSCR))
1136 t->dscr = mfspr(SPRN_DSCR);
1138 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1139 t->bescr = mfspr(SPRN_BESCR);
1140 t->ebbhr = mfspr(SPRN_EBBHR);
1141 t->ebbrr = mfspr(SPRN_EBBRR);
1143 t->fscr = mfspr(SPRN_FSCR);
1146 * Note that the TAR is not available for use in the kernel.
1147 * (To provide this, the TAR should be backed up/restored on
1148 * exception entry/exit instead, and be in pt_regs. FIXME,
1149 * this should be in pt_regs anyway (for debug).)
1151 t->tar = mfspr(SPRN_TAR);
1156 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
1157 void kvmppc_save_user_regs(void)
1159 unsigned long usermsr;
1161 if (!current->thread.regs)
1164 usermsr = current->thread.regs->msr;
1166 if (usermsr & MSR_FP)
1169 if (usermsr & MSR_VEC)
1170 save_altivec(current);
1172 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1173 if (usermsr & MSR_TM) {
1174 current->thread.tm_tfhar = mfspr(SPRN_TFHAR);
1175 current->thread.tm_tfiar = mfspr(SPRN_TFIAR);
1176 current->thread.tm_texasr = mfspr(SPRN_TEXASR);
1177 current->thread.regs->msr &= ~MSR_TM;
1181 EXPORT_SYMBOL_GPL(kvmppc_save_user_regs);
1183 void kvmppc_save_current_sprs(void)
1185 save_sprs(¤t->thread);
1187 EXPORT_SYMBOL_GPL(kvmppc_save_current_sprs);
1188 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
1190 static inline void restore_sprs(struct thread_struct *old_thread,
1191 struct thread_struct *new_thread)
1193 #ifdef CONFIG_ALTIVEC
1194 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1195 old_thread->vrsave != new_thread->vrsave)
1196 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1199 if (cpu_has_feature(CPU_FTR_SPE) &&
1200 old_thread->spefscr != new_thread->spefscr)
1201 mtspr(SPRN_SPEFSCR, new_thread->spefscr);
1203 #ifdef CONFIG_PPC_BOOK3S_64
1204 if (cpu_has_feature(CPU_FTR_DSCR)) {
1205 u64 dscr = get_paca()->dscr_default;
1206 if (new_thread->dscr_inherit)
1207 dscr = new_thread->dscr;
1209 if (old_thread->dscr != dscr)
1210 mtspr(SPRN_DSCR, dscr);
1213 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1214 if (old_thread->bescr != new_thread->bescr)
1215 mtspr(SPRN_BESCR, new_thread->bescr);
1216 if (old_thread->ebbhr != new_thread->ebbhr)
1217 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1218 if (old_thread->ebbrr != new_thread->ebbrr)
1219 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1221 if (old_thread->fscr != new_thread->fscr)
1222 mtspr(SPRN_FSCR, new_thread->fscr);
1224 if (old_thread->tar != new_thread->tar)
1225 mtspr(SPRN_TAR, new_thread->tar);
1228 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1229 old_thread->tidr != new_thread->tidr)
1230 mtspr(SPRN_TIDR, new_thread->tidr);
1235 struct task_struct *__switch_to(struct task_struct *prev,
1236 struct task_struct *new)
1238 struct thread_struct *new_thread, *old_thread;
1239 struct task_struct *last;
1240 #ifdef CONFIG_PPC_64S_HASH_MMU
1241 struct ppc64_tlb_batch *batch;
1244 new_thread = &new->thread;
1245 old_thread = ¤t->thread;
1247 WARN_ON(!irqs_disabled());
1249 #ifdef CONFIG_PPC_64S_HASH_MMU
1250 batch = this_cpu_ptr(&ppc64_tlb_batch);
1251 if (batch->active) {
1252 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1254 __flush_tlb_pending(batch);
1259 * On POWER9 the copy-paste buffer can only paste into
1260 * foreign real addresses, so unprivileged processes can not
1261 * see the data or use it in any way unless they have
1262 * foreign real mappings. If the new process has the foreign
1263 * real address mappings, we must issue a cp_abort to clear
1264 * any state and prevent snooping, corruption or a covert
1265 * channel. ISA v3.1 supports paste into local memory.
1267 if (new->mm && (cpu_has_feature(CPU_FTR_ARCH_31) ||
1268 atomic_read(&new->mm->context.vas_windows)))
1269 asm volatile(PPC_CP_ABORT);
1270 #endif /* CONFIG_PPC_BOOK3S_64 */
1272 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1273 switch_booke_debug_regs(&new->thread.debug);
1276 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1279 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1280 switch_hw_breakpoint(new);
1281 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1285 * We need to save SPRs before treclaim/trecheckpoint as these will
1286 * change a number of them.
1288 save_sprs(&prev->thread);
1290 /* Save FPU, Altivec, VSX and SPE state */
1293 __switch_to_tm(prev, new);
1295 if (!radix_enabled()) {
1297 * We can't take a PMU exception inside _switch() since there
1298 * is a window where the kernel stack SLB and the kernel stack
1299 * are out of sync. Hard disable here.
1305 * Call restore_sprs() and set_return_regs_changed() before calling
1306 * _switch(). If we move it after _switch() then we miss out on calling
1307 * it for new tasks. The reason for this is we manually create a stack
1308 * frame for new tasks that directly returns through ret_from_fork() or
1309 * ret_from_kernel_thread(). See copy_thread() for details.
1311 restore_sprs(old_thread, new_thread);
1313 set_return_regs_changed(); /* _switch changes stack (and regs) */
1315 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64))
1316 kuap_assert_locked();
1318 last = _switch(old_thread, new_thread);
1321 * Nothing after _switch will be run for newly created tasks,
1322 * because they switch directly to ret_from_fork/ret_from_kernel_thread
1323 * etc. Code added here should have a comment explaining why that is
1327 #ifdef CONFIG_PPC_BOOK3S_64
1328 #ifdef CONFIG_PPC_64S_HASH_MMU
1330 * This applies to a process that was context switched while inside
1331 * arch_enter_lazy_mmu_mode(), to re-activate the batch that was
1332 * deactivated above, before _switch(). This will never be the case
1335 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1336 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1337 batch = this_cpu_ptr(&ppc64_tlb_batch);
1343 * Math facilities are masked out of the child MSR in copy_thread.
1344 * A new task does not need to restore_math because it will
1345 * demand fault them.
1347 if (current->thread.regs)
1348 restore_math(current->thread.regs);
1349 #endif /* CONFIG_PPC_BOOK3S_64 */
1354 #define NR_INSN_TO_PRINT 16
1356 static void show_instructions(struct pt_regs *regs)
1359 unsigned long nip = regs->nip;
1360 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1362 printk("Instruction dump:");
1365 * If we were executing with the MMU off for instructions, adjust pc
1366 * rather than printing XXXXXXXX.
1368 if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) {
1369 pc = (unsigned long)phys_to_virt(pc);
1370 nip = (unsigned long)phys_to_virt(regs->nip);
1373 for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1379 if (!__kernel_text_address(pc) ||
1380 get_kernel_nofault(instr, (const void *)pc)) {
1381 pr_cont("XXXXXXXX ");
1384 pr_cont("<%08x> ", instr);
1386 pr_cont("%08x ", instr);
1395 void show_user_instructions(struct pt_regs *regs)
1398 int n = NR_INSN_TO_PRINT;
1400 char buf[96]; /* enough for 8 times 9 + 2 chars */
1402 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1404 seq_buf_init(&s, buf, sizeof(buf));
1411 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1414 if (copy_from_user_nofault(&instr, (void __user *)pc,
1416 seq_buf_printf(&s, "XXXXXXXX ");
1419 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1422 if (!seq_buf_has_overflowed(&s))
1423 pr_info("%s[%d]: code: %s\n", current->comm,
1424 current->pid, s.buffer);
1433 static struct regbit msr_bits[] = {
1434 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1456 #ifndef CONFIG_BOOKE
1463 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1467 for (; bits->bit; ++bits)
1468 if (val & bits->bit) {
1469 pr_cont("%s%s", s, bits->name);
1474 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1475 static struct regbit msr_tm_bits[] = {
1482 static void print_tm_bits(unsigned long val)
1485 * This only prints something if at least one of the TM bit is set.
1486 * Inside the TM[], the output means:
1487 * E: Enabled (bit 32)
1488 * S: Suspended (bit 33)
1489 * T: Transactional (bit 34)
1491 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1493 print_bits(val, msr_tm_bits, "");
1498 static void print_tm_bits(unsigned long val) {}
1501 static void print_msr_bits(unsigned long val)
1504 print_bits(val, msr_bits, ",");
1510 #define REG "%016lx"
1511 #define REGS_PER_LINE 4
1514 #define REGS_PER_LINE 8
1517 static void __show_regs(struct pt_regs *regs)
1521 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1522 regs->nip, regs->link, regs->ctr);
1523 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1524 regs, regs->trap, print_tainted(), init_utsname()->release);
1525 printk("MSR: "REG" ", regs->msr);
1526 print_msr_bits(regs->msr);
1527 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1529 if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR))
1530 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1531 if (trap == INTERRUPT_MACHINE_CHECK ||
1532 trap == INTERRUPT_DATA_STORAGE ||
1533 trap == INTERRUPT_ALIGNMENT) {
1534 if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
1535 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dear, regs->esr);
1537 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1541 pr_cont("IRQMASK: %lx ", regs->softe);
1543 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1544 if (MSR_TM_ACTIVE(regs->msr))
1545 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1548 for (i = 0; i < 32; i++) {
1549 if ((i % REGS_PER_LINE) == 0)
1550 pr_cont("\nGPR%02d: ", i);
1551 pr_cont(REG " ", regs->gpr[i]);
1555 * Lookup NIP late so we have the best change of getting the
1556 * above info out without failing
1558 if (IS_ENABLED(CONFIG_KALLSYMS)) {
1559 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1560 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1564 void show_regs(struct pt_regs *regs)
1566 show_regs_print_info(KERN_DEFAULT);
1568 show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT);
1569 if (!user_mode(regs))
1570 show_instructions(regs);
1573 void flush_thread(void)
1575 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1576 flush_ptrace_hw_breakpoint(current);
1577 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1578 set_debug_reg_defaults(¤t->thread);
1579 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1582 void arch_setup_new_exec(void)
1585 #ifdef CONFIG_PPC_BOOK3S_64
1586 if (!radix_enabled())
1587 hash__setup_new_exec();
1590 * If we exec out of a kernel thread then thread.regs will not be
1593 if (!current->thread.regs) {
1594 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1595 current->thread.regs = regs - 1;
1598 #ifdef CONFIG_PPC_MEM_KEYS
1599 current->thread.regs->amr = default_amr;
1600 current->thread.regs->iamr = default_iamr;
1606 * Assign a TIDR (thread ID) for task @t and set it in the thread
1607 * structure. For now, we only support setting TIDR for 'current' task.
1609 * Since the TID value is a truncated form of it PID, it is possible
1610 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1611 * that 2 threads share the same TID and are waiting, one of the following
1612 * cases will happen:
1614 * 1. The correct thread is running, the wrong thread is not
1615 * In this situation, the correct thread is woken and proceeds to pass it's
1618 * 2. Neither threads are running
1619 * In this situation, neither thread will be woken. When scheduled, the waiting
1620 * threads will execute either a wait, which will return immediately, followed
1621 * by a condition check, which will pass for the correct thread and fail
1622 * for the wrong thread, or they will execute the condition check immediately.
1624 * 3. The wrong thread is running, the correct thread is not
1625 * The wrong thread will be woken, but will fail it's condition check and
1626 * re-execute wait. The correct thread, when scheduled, will execute either
1627 * it's condition check (which will pass), or wait, which returns immediately
1628 * when called the first time after the thread is scheduled, followed by it's
1629 * condition check (which will pass).
1631 * 4. Both threads are running
1632 * Both threads will be woken. The wrong thread will fail it's condition check
1633 * and execute another wait, while the correct thread will pass it's condition
1636 * @t: the task to set the thread ID for
1638 int set_thread_tidr(struct task_struct *t)
1640 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1649 t->thread.tidr = (u16)task_pid_nr(t);
1650 mtspr(SPRN_TIDR, t->thread.tidr);
1654 EXPORT_SYMBOL_GPL(set_thread_tidr);
1656 #endif /* CONFIG_PPC64 */
1659 * this gets called so that we can store coprocessor state into memory and
1660 * copy the current task into the new thread.
1662 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1664 flush_all_to_thread(src);
1666 * Flush TM state out so we can copy it. __switch_to_tm() does this
1667 * flush but it removes the checkpointed state from the current CPU and
1668 * transitions the CPU out of TM mode. Hence we need to call
1669 * tm_recheckpoint_new_task() (on the same task) to restore the
1670 * checkpointed state back and the TM mode.
1672 * Can't pass dst because it isn't ready. Doesn't matter, passing
1673 * dst is only important for __switch_to()
1675 __switch_to_tm(src, src);
1679 clear_task_ebb(dst);
1684 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1686 #ifdef CONFIG_PPC_64S_HASH_MMU
1687 unsigned long sp_vsid;
1688 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1690 if (radix_enabled())
1693 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1694 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1695 << SLB_VSID_SHIFT_1T;
1697 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1699 sp_vsid |= SLB_VSID_KERNEL | llp;
1700 p->thread.ksp_vsid = sp_vsid;
1709 * Copy architecture-specific thread state
1711 int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
1713 unsigned long clone_flags = args->flags;
1714 unsigned long usp = args->stack;
1715 unsigned long tls = args->tls;
1716 struct pt_regs *childregs, *kregs;
1717 extern void ret_from_fork(void);
1718 extern void ret_from_fork_scv(void);
1719 extern void ret_from_kernel_thread(void);
1721 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1722 struct thread_info *ti = task_thread_info(p);
1723 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1727 klp_init_thread_info(p);
1729 /* Copy registers */
1730 sp -= sizeof(struct pt_regs);
1731 childregs = (struct pt_regs *) sp;
1732 if (unlikely(args->fn)) {
1734 memset(childregs, 0, sizeof(struct pt_regs));
1735 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1738 childregs->gpr[14] = ppc_function_entry((void *)args->fn);
1740 clear_tsk_thread_flag(p, TIF_32BIT);
1741 childregs->softe = IRQS_ENABLED;
1743 childregs->gpr[15] = (unsigned long)args->fn_arg;
1744 p->thread.regs = NULL; /* no user register state */
1745 ti->flags |= _TIF_RESTOREALL;
1746 f = ret_from_kernel_thread;
1749 struct pt_regs *regs = current_pt_regs();
1752 childregs->gpr[1] = usp;
1753 p->thread.regs = childregs;
1754 /* 64s sets this in ret_from_fork */
1755 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64))
1756 childregs->gpr[3] = 0; /* Result from fork() */
1757 if (clone_flags & CLONE_SETTLS) {
1758 if (!is_32bit_task())
1759 childregs->gpr[13] = tls;
1761 childregs->gpr[2] = tls;
1764 if (trap_is_scv(regs))
1765 f = ret_from_fork_scv;
1769 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1770 sp -= STACK_FRAME_OVERHEAD;
1773 * The way this works is that at some point in the future
1774 * some task will call _switch to switch to the new task.
1775 * That will pop off the stack frame created below and start
1776 * the new task running at ret_from_fork. The new task will
1777 * do some house keeping and then return from the fork or clone
1778 * system call, using the stack frame created above.
1780 ((unsigned long *)sp)[0] = 0;
1781 sp -= sizeof(struct pt_regs);
1782 kregs = (struct pt_regs *) sp;
1783 sp -= STACK_FRAME_OVERHEAD;
1785 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1786 for (i = 0; i < nr_wp_slots(); i++)
1787 p->thread.ptrace_bps[i] = NULL;
1790 #ifdef CONFIG_PPC_FPU_REGS
1791 p->thread.fp_save_area = NULL;
1793 #ifdef CONFIG_ALTIVEC
1794 p->thread.vr_save_area = NULL;
1796 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
1797 p->thread.kuap = KUAP_NONE;
1799 #if defined(CONFIG_BOOKE_OR_40x) && defined(CONFIG_PPC_KUAP)
1800 p->thread.pid = MMU_NO_CONTEXT;
1803 setup_ksp_vsid(p, sp);
1806 if (cpu_has_feature(CPU_FTR_DSCR)) {
1807 p->thread.dscr_inherit = current->thread.dscr_inherit;
1808 p->thread.dscr = mfspr(SPRN_DSCR);
1810 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1811 childregs->ppr = DEFAULT_PPR;
1816 * Run with the current AMR value of the kernel
1818 #ifdef CONFIG_PPC_PKEY
1819 if (mmu_has_feature(MMU_FTR_BOOK3S_KUAP))
1820 kregs->amr = AMR_KUAP_BLOCKED;
1822 if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP))
1823 kregs->iamr = AMR_KUEP_BLOCKED;
1825 kregs->nip = ppc_function_entry(f);
1829 void preload_new_slb_context(unsigned long start, unsigned long sp);
1832 * Set up a thread for executing a new program
1834 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1837 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1839 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !radix_enabled())
1840 preload_new_slb_context(start, sp);
1843 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1845 * Clear any transactional state, we're exec()ing. The cause is
1846 * not important as there will never be a recheckpoint so it's not
1849 if (MSR_TM_SUSPENDED(mfmsr()))
1850 tm_reclaim_current(0);
1853 memset(®s->gpr[1], 0, sizeof(regs->gpr) - sizeof(regs->gpr[0]));
1863 regs->msr = MSR_USER;
1865 if (!is_32bit_task()) {
1866 unsigned long entry;
1868 if (is_elf2_task()) {
1869 /* Look ma, no function descriptors! */
1874 * The latest iteration of the ABI requires that when
1875 * calling a function (at its global entry point),
1876 * the caller must ensure r12 holds the entry point
1877 * address (so that the function can quickly
1878 * establish addressability).
1880 regs->gpr[12] = start;
1881 /* Make sure that's restored on entry to userspace. */
1882 set_thread_flag(TIF_RESTOREALL);
1886 /* start is a relocated pointer to the function
1887 * descriptor for the elf _start routine. The first
1888 * entry in the function descriptor is the entry
1889 * address of _start and the second entry is the TOC
1890 * value we need to use.
1892 __get_user(entry, (unsigned long __user *)start);
1893 __get_user(toc, (unsigned long __user *)start+1);
1895 /* Check whether the e_entry function descriptor entries
1896 * need to be relocated before we can use them.
1898 if (load_addr != 0) {
1904 regs_set_return_ip(regs, entry);
1905 regs_set_return_msr(regs, MSR_USER64);
1908 regs_set_return_ip(regs, start);
1909 regs_set_return_msr(regs, MSR_USER32);
1914 current->thread.used_vsr = 0;
1916 current->thread.load_slb = 0;
1917 current->thread.load_fp = 0;
1918 #ifdef CONFIG_PPC_FPU_REGS
1919 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1920 current->thread.fp_save_area = NULL;
1922 #ifdef CONFIG_ALTIVEC
1923 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1924 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1925 current->thread.vr_save_area = NULL;
1926 current->thread.vrsave = 0;
1927 current->thread.used_vr = 0;
1928 current->thread.load_vec = 0;
1929 #endif /* CONFIG_ALTIVEC */
1931 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1932 current->thread.acc = 0;
1933 current->thread.spefscr = 0;
1934 current->thread.used_spe = 0;
1935 #endif /* CONFIG_SPE */
1936 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1937 current->thread.tm_tfhar = 0;
1938 current->thread.tm_texasr = 0;
1939 current->thread.tm_tfiar = 0;
1940 current->thread.load_tm = 0;
1941 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1943 EXPORT_SYMBOL(start_thread);
1945 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1946 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1948 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1950 struct pt_regs *regs = tsk->thread.regs;
1952 /* This is a bit hairy. If we are an SPE enabled processor
1953 * (have embedded fp) we store the IEEE exception enable flags in
1954 * fpexc_mode. fpexc_mode is also used for setting FP exception
1955 * mode (asyn, precise, disabled) for 'Classic' FP. */
1956 if (val & PR_FP_EXC_SW_ENABLE) {
1957 if (cpu_has_feature(CPU_FTR_SPE)) {
1959 * When the sticky exception bits are set
1960 * directly by userspace, it must call prctl
1961 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1962 * in the existing prctl settings) or
1963 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1964 * the bits being set). <fenv.h> functions
1965 * saving and restoring the whole
1966 * floating-point environment need to do so
1967 * anyway to restore the prctl settings from
1968 * the saved environment.
1971 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1972 tsk->thread.fpexc_mode = val &
1973 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1981 /* on a CONFIG_SPE this does not hurt us. The bits that
1982 * __pack_fe01 use do not overlap with bits used for
1983 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1984 * on CONFIG_SPE implementations are reserved so writing to
1985 * them does not change anything */
1986 if (val > PR_FP_EXC_PRECISE)
1988 tsk->thread.fpexc_mode = __pack_fe01(val);
1989 if (regs != NULL && (regs->msr & MSR_FP) != 0) {
1990 regs_set_return_msr(regs, (regs->msr & ~(MSR_FE0|MSR_FE1))
1991 | tsk->thread.fpexc_mode);
1996 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1998 unsigned int val = 0;
2000 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {
2001 if (cpu_has_feature(CPU_FTR_SPE)) {
2003 * When the sticky exception bits are set
2004 * directly by userspace, it must call prctl
2005 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
2006 * in the existing prctl settings) or
2007 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
2008 * the bits being set). <fenv.h> functions
2009 * saving and restoring the whole
2010 * floating-point environment need to do so
2011 * anyway to restore the prctl settings from
2012 * the saved environment.
2015 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
2016 val = tsk->thread.fpexc_mode;
2021 val = __unpack_fe01(tsk->thread.fpexc_mode);
2023 return put_user(val, (unsigned int __user *) adr);
2026 int set_endian(struct task_struct *tsk, unsigned int val)
2028 struct pt_regs *regs = tsk->thread.regs;
2030 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
2031 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
2037 if (val == PR_ENDIAN_BIG)
2038 regs_set_return_msr(regs, regs->msr & ~MSR_LE);
2039 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
2040 regs_set_return_msr(regs, regs->msr | MSR_LE);
2047 int get_endian(struct task_struct *tsk, unsigned long adr)
2049 struct pt_regs *regs = tsk->thread.regs;
2052 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
2053 !cpu_has_feature(CPU_FTR_REAL_LE))
2059 if (regs->msr & MSR_LE) {
2060 if (cpu_has_feature(CPU_FTR_REAL_LE))
2061 val = PR_ENDIAN_LITTLE;
2063 val = PR_ENDIAN_PPC_LITTLE;
2065 val = PR_ENDIAN_BIG;
2067 return put_user(val, (unsigned int __user *)adr);
2070 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
2072 tsk->thread.align_ctl = val;
2076 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
2078 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
2081 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
2082 unsigned long nbytes)
2084 unsigned long stack_page;
2085 unsigned long cpu = task_cpu(p);
2087 stack_page = (unsigned long)hardirq_ctx[cpu];
2088 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2091 stack_page = (unsigned long)softirq_ctx[cpu];
2092 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2098 static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p,
2099 unsigned long nbytes)
2102 unsigned long stack_page;
2103 unsigned long cpu = task_cpu(p);
2108 stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE;
2109 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2112 # ifdef CONFIG_PPC_BOOK3S_64
2113 stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE;
2114 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2117 stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE;
2118 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2127 int validate_sp(unsigned long sp, struct task_struct *p,
2128 unsigned long nbytes)
2130 unsigned long stack_page = (unsigned long)task_stack_page(p);
2132 if (sp < THREAD_SIZE)
2135 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2138 if (valid_irq_stack(sp, p, nbytes))
2141 return valid_emergency_stack(sp, p, nbytes);
2144 EXPORT_SYMBOL(validate_sp);
2146 static unsigned long ___get_wchan(struct task_struct *p)
2148 unsigned long ip, sp;
2152 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2156 sp = READ_ONCE_NOCHECK(*(unsigned long *)sp);
2157 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2161 ip = READ_ONCE_NOCHECK(((unsigned long *)sp)[STACK_FRAME_LR_SAVE]);
2162 if (!in_sched_functions(ip))
2165 } while (count++ < 16);
2169 unsigned long __get_wchan(struct task_struct *p)
2173 if (!try_get_task_stack(p))
2176 ret = ___get_wchan(p);
2183 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2185 void __no_sanitize_address show_stack(struct task_struct *tsk,
2186 unsigned long *stack,
2189 unsigned long sp, ip, lr, newsp;
2192 unsigned long ret_addr;
2198 if (!try_get_task_stack(tsk))
2201 sp = (unsigned long) stack;
2204 sp = current_stack_frame();
2206 sp = tsk->thread.ksp;
2210 printk("%sCall Trace:\n", loglvl);
2212 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2215 stack = (unsigned long *) sp;
2217 ip = stack[STACK_FRAME_LR_SAVE];
2218 if (!firstframe || ip != lr) {
2219 printk("%s["REG"] ["REG"] %pS",
2220 loglvl, sp, ip, (void *)ip);
2221 ret_addr = ftrace_graph_ret_addr(current,
2222 &ftrace_idx, ip, stack);
2224 pr_cont(" (%pS)", (void *)ret_addr);
2226 pr_cont(" (unreliable)");
2232 * See if this is an exception frame.
2233 * We look for the "regshere" marker in the current frame.
2235 if (validate_sp(sp, tsk, STACK_FRAME_WITH_PT_REGS)
2236 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2237 struct pt_regs *regs = (struct pt_regs *)
2238 (sp + STACK_FRAME_OVERHEAD);
2241 printk("%s--- interrupt: %lx at %pS\n",
2242 loglvl, regs->trap, (void *)regs->nip);
2244 printk("%s--- interrupt: %lx\n",
2245 loglvl, regs->trap);
2251 } while (count++ < kstack_depth_to_print);
2253 put_task_stack(tsk);
2257 /* Called with hard IRQs off */
2258 void notrace __ppc64_runlatch_on(void)
2260 struct thread_info *ti = current_thread_info();
2262 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2264 * Least significant bit (RUN) is the only writable bit of
2265 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2266 * earliest ISA where this is the case, but it's convenient.
2268 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2273 * Some architectures (e.g., Cell) have writable fields other
2274 * than RUN, so do the read-modify-write.
2276 ctrl = mfspr(SPRN_CTRLF);
2277 ctrl |= CTRL_RUNLATCH;
2278 mtspr(SPRN_CTRLT, ctrl);
2281 ti->local_flags |= _TLF_RUNLATCH;
2284 /* Called with hard IRQs off */
2285 void notrace __ppc64_runlatch_off(void)
2287 struct thread_info *ti = current_thread_info();
2289 ti->local_flags &= ~_TLF_RUNLATCH;
2291 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2292 mtspr(SPRN_CTRLT, 0);
2296 ctrl = mfspr(SPRN_CTRLF);
2297 ctrl &= ~CTRL_RUNLATCH;
2298 mtspr(SPRN_CTRLT, ctrl);
2301 #endif /* CONFIG_PPC64 */
2303 unsigned long arch_align_stack(unsigned long sp)
2305 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2306 sp -= get_random_int() & ~PAGE_MASK;