arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/debug.h>
  20 #include <linux/sched/task.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mm.h>
  23 #include <linux/smp.h>
  24 #include <linux/stddef.h>
  25 #include <linux/unistd.h>
  26 #include <linux/ptrace.h>
  27 #include <linux/slab.h>
  28 #include <linux/user.h>
  29 #include <linux/elf.h>
  30 #include <linux/prctl.h>
  31 #include <linux/init_task.h>
  32 #include <linux/export.h>
  33 #include <linux/kallsyms.h>
  34 #include <linux/mqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/utsname.h>
  37 #include <linux/ftrace.h>
  38 #include <linux/kernel_stat.h>
  39 #include <linux/personality.h>
  40 #include <linux/random.h>
  41 #include <linux/hw_breakpoint.h>
  42 #include <linux/uaccess.h>
  43 #include <linux/elf-randomize.h>
  44
  45 #include <asm/pgtable.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/prom.h>
  50 #include <asm/machdep.h>
  51 #include <asm/time.h>
  52 #include <asm/runlatch.h>
  53 #include <asm/syscalls.h>
  54 #include <asm/switch_to.h>
  55 #include <asm/tm.h>
  56 #include <asm/debug.h>
  57 #ifdef CONFIG_PPC64
  58 #include <asm/firmware.h>
  59 #endif
  60 #include <asm/code-patching.h>
  61 #include <asm/exec.h>
  62 #include <asm/livepatch.h>
  63 #include <asm/cpu_has_feature.h>
  64 #include <asm/asm-prototypes.h>
  65
  66 #include <linux/kprobes.h>
  67 #include <linux/kdebug.h>
  68
  69 /* Transactional Memory debug */
  70 #ifdef TM_DEBUG_SW
  71 #define TM_DEBUG(x...) printk(KERN_INFO x)
  72 #else
  73 #define TM_DEBUG(x...) do { } while(0)
  74 #endif
  75
  76 extern unsigned long _get_SP(void);
  77
  78 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  79 static void check_if_tm_restore_required(struct task_struct *tsk)
  80 {
  81         /*
  82          * If we are saving the current thread's registers, and the
  83          * thread is in a transactional state, set the TIF_RESTORE_TM
  84          * bit so that we know to restore the registers before
  85          * returning to userspace.
  86          */
  87         if (tsk == current && tsk->thread.regs &&
  88             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  89             !test_thread_flag(TIF_RESTORE_TM)) {
  90                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  91                 set_thread_flag(TIF_RESTORE_TM);
  92         }
  93 }
  94
  95 static inline bool msr_tm_active(unsigned long msr)
  96 {
  97         return MSR_TM_ACTIVE(msr);
  98 }
  99 #else
 100 static inline bool msr_tm_active(unsigned long msr) { return false; }
 101 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 102 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 103
 104 bool strict_msr_control;
 105 EXPORT_SYMBOL(strict_msr_control);
 106
 107 static int __init enable_strict_msr_control(char *str)
 108 {
 109         strict_msr_control = true;
 110         pr_info("Enabling strict facility control\n");
 111
 112         return 0;
 113 }
 114 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 115
 116 unsigned long msr_check_and_set(unsigned long bits)
 117 {
 118         unsigned long oldmsr = mfmsr();
 119         unsigned long newmsr;
 120
 121         newmsr = oldmsr | bits;
 122
 123 #ifdef CONFIG_VSX
 124         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 125                 newmsr |= MSR_VSX;
 126 #endif
 127
 128         if (oldmsr != newmsr)
 129                 mtmsr_isync(newmsr);
 130
 131         return newmsr;
 132 }
 133
 134 void __msr_check_and_clear(unsigned long bits)
 135 {
 136         unsigned long oldmsr = mfmsr();
 137         unsigned long newmsr;
 138
 139         newmsr = oldmsr & ~bits;
 140
 141 #ifdef CONFIG_VSX
 142         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 143                 newmsr &= ~MSR_VSX;
 144 #endif
 145
 146         if (oldmsr != newmsr)
 147                 mtmsr_isync(newmsr);
 148 }
 149 EXPORT_SYMBOL(__msr_check_and_clear);
 150
 151 #ifdef CONFIG_PPC_FPU
 152 void __giveup_fpu(struct task_struct *tsk)
 153 {
 154         unsigned long msr;
 155
 156         save_fpu(tsk);
 157         msr = tsk->thread.regs->msr;
 158         msr &= ~MSR_FP;
 159 #ifdef CONFIG_VSX
 160         if (cpu_has_feature(CPU_FTR_VSX))
 161                 msr &= ~MSR_VSX;
 162 #endif
 163         tsk->thread.regs->msr = msr;
 164 }
 165
 166 void giveup_fpu(struct task_struct *tsk)
 167 {
 168         check_if_tm_restore_required(tsk);
 169
 170         msr_check_and_set(MSR_FP);
 171         __giveup_fpu(tsk);
 172         msr_check_and_clear(MSR_FP);
 173 }
 174 EXPORT_SYMBOL(giveup_fpu);
 175
 176 /*
 177  * Make sure the floating-point register state in the
 178  * the thread_struct is up to date for task tsk.
 179  */
 180 void flush_fp_to_thread(struct task_struct *tsk)
 181 {
 182         if (tsk->thread.regs) {
 183                 /*
 184                  * We need to disable preemption here because if we didn't,
 185                  * another process could get scheduled after the regs->msr
 186                  * test but before we have finished saving the FP registers
 187                  * to the thread_struct.  That process could take over the
 188                  * FPU, and then when we get scheduled again we would store
 189                  * bogus values for the remaining FP registers.
 190                  */
 191                 preempt_disable();
 192                 if (tsk->thread.regs->msr & MSR_FP) {
 193                         /*
 194                          * This should only ever be called for current or
 195                          * for a stopped child process.  Since we save away
 196                          * the FP register state on context switch,
 197                          * there is something wrong if a stopped child appears
 198                          * to still have its FP state in the CPU registers.
 199                          */
 200                         BUG_ON(tsk != current);
 201                         giveup_fpu(tsk);
 202                 }
 203                 preempt_enable();
 204         }
 205 }
 206 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 207
 208 void enable_kernel_fp(void)
 209 {
 210         unsigned long cpumsr;
 211
 212         WARN_ON(preemptible());
 213
 214         cpumsr = msr_check_and_set(MSR_FP);
 215
 216         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 217                 check_if_tm_restore_required(current);
 218                 /*
 219                  * If a thread has already been reclaimed then the
 220                  * checkpointed registers are on the CPU but have definitely
 221                  * been saved by the reclaim code. Don't need to and *cannot*
 222                  * giveup as this would save  to the 'live' structure not the
 223                  * checkpointed structure.
 224                  */
 225                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 226                         return;
 227                 __giveup_fpu(current);
 228         }
 229 }
 230 EXPORT_SYMBOL(enable_kernel_fp);
 231
 232 static int restore_fp(struct task_struct *tsk) {
 233         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 234                 load_fp_state(&current->thread.fp_state);
 235                 current->thread.load_fp++;
 236                 return 1;
 237         }
 238         return 0;
 239 }
 240 #else
 241 static int restore_fp(struct task_struct *tsk) { return 0; }
 242 #endif /* CONFIG_PPC_FPU */
 243
 244 #ifdef CONFIG_ALTIVEC
 245 #define loadvec(thr) ((thr).load_vec)
 246
 247 static void __giveup_altivec(struct task_struct *tsk)
 248 {
 249         unsigned long msr;
 250
 251         save_altivec(tsk);
 252         msr = tsk->thread.regs->msr;
 253         msr &= ~MSR_VEC;
 254 #ifdef CONFIG_VSX
 255         if (cpu_has_feature(CPU_FTR_VSX))
 256                 msr &= ~MSR_VSX;
 257 #endif
 258         tsk->thread.regs->msr = msr;
 259 }
 260
 261 void giveup_altivec(struct task_struct *tsk)
 262 {
 263         check_if_tm_restore_required(tsk);
 264
 265         msr_check_and_set(MSR_VEC);
 266         __giveup_altivec(tsk);
 267         msr_check_and_clear(MSR_VEC);
 268 }
 269 EXPORT_SYMBOL(giveup_altivec);
 270
 271 void enable_kernel_altivec(void)
 272 {
 273         unsigned long cpumsr;
 274
 275         WARN_ON(preemptible());
 276
 277         cpumsr = msr_check_and_set(MSR_VEC);
 278
 279         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 280                 check_if_tm_restore_required(current);
 281                 /*
 282                  * If a thread has already been reclaimed then the
 283                  * checkpointed registers are on the CPU but have definitely
 284                  * been saved by the reclaim code. Don't need to and *cannot*
 285                  * giveup as this would save  to the 'live' structure not the
 286                  * checkpointed structure.
 287                  */
 288                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 289                         return;
 290                 __giveup_altivec(current);
 291         }
 292 }
 293 EXPORT_SYMBOL(enable_kernel_altivec);
 294
 295 /*
 296  * Make sure the VMX/Altivec register state in the
 297  * the thread_struct is up to date for task tsk.
 298  */
 299 void flush_altivec_to_thread(struct task_struct *tsk)
 300 {
 301         if (tsk->thread.regs) {
 302                 preempt_disable();
 303                 if (tsk->thread.regs->msr & MSR_VEC) {
 304                         BUG_ON(tsk != current);
 305                         giveup_altivec(tsk);
 306                 }
 307                 preempt_enable();
 308         }
 309 }
 310 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 311
 312 static int restore_altivec(struct task_struct *tsk)
 313 {
 314         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 315                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 316                 load_vr_state(&tsk->thread.vr_state);
 317                 tsk->thread.used_vr = 1;
 318                 tsk->thread.load_vec++;
 319
 320                 return 1;
 321         }
 322         return 0;
 323 }
 324 #else
 325 #define loadvec(thr) 0
 326 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 327 #endif /* CONFIG_ALTIVEC */
 328
 329 #ifdef CONFIG_VSX
 330 static void __giveup_vsx(struct task_struct *tsk)
 331 {
 332         if (tsk->thread.regs->msr & MSR_FP)
 333                 __giveup_fpu(tsk);
 334         if (tsk->thread.regs->msr & MSR_VEC)
 335                 __giveup_altivec(tsk);
 336         tsk->thread.regs->msr &= ~MSR_VSX;
 337 }
 338
 339 static void giveup_vsx(struct task_struct *tsk)
 340 {
 341         check_if_tm_restore_required(tsk);
 342
 343         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 344         __giveup_vsx(tsk);
 345         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 346 }
 347
 348 static void save_vsx(struct task_struct *tsk)
 349 {
 350         if (tsk->thread.regs->msr & MSR_FP)
 351                 save_fpu(tsk);
 352         if (tsk->thread.regs->msr & MSR_VEC)
 353                 save_altivec(tsk);
 354 }
 355
 356 void enable_kernel_vsx(void)
 357 {
 358         unsigned long cpumsr;
 359
 360         WARN_ON(preemptible());
 361
 362         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 363
 364         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 365                 check_if_tm_restore_required(current);
 366                 /*
 367                  * If a thread has already been reclaimed then the
 368                  * checkpointed registers are on the CPU but have definitely
 369                  * been saved by the reclaim code. Don't need to and *cannot*
 370                  * giveup as this would save  to the 'live' structure not the
 371                  * checkpointed structure.
 372                  */
 373                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 374                         return;
 375                 if (current->thread.regs->msr & MSR_FP)
 376                         __giveup_fpu(current);
 377                 if (current->thread.regs->msr & MSR_VEC)
 378                         __giveup_altivec(current);
 379                 __giveup_vsx(current);
 380         }
 381 }
 382 EXPORT_SYMBOL(enable_kernel_vsx);
 383
 384 void flush_vsx_to_thread(struct task_struct *tsk)
 385 {
 386         if (tsk->thread.regs) {
 387                 preempt_disable();
 388                 if (tsk->thread.regs->msr & MSR_VSX) {
 389                         BUG_ON(tsk != current);
 390                         giveup_vsx(tsk);
 391                 }
 392                 preempt_enable();
 393         }
 394 }
 395 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 396
 397 static int restore_vsx(struct task_struct *tsk)
 398 {
 399         if (cpu_has_feature(CPU_FTR_VSX)) {
 400                 tsk->thread.used_vsr = 1;
 401                 return 1;
 402         }
 403
 404         return 0;
 405 }
 406 #else
 407 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 408 static inline void save_vsx(struct task_struct *tsk) { }
 409 #endif /* CONFIG_VSX */
 410
 411 #ifdef CONFIG_SPE
 412 void giveup_spe(struct task_struct *tsk)
 413 {
 414         check_if_tm_restore_required(tsk);
 415
 416         msr_check_and_set(MSR_SPE);
 417         __giveup_spe(tsk);
 418         msr_check_and_clear(MSR_SPE);
 419 }
 420 EXPORT_SYMBOL(giveup_spe);
 421
 422 void enable_kernel_spe(void)
 423 {
 424         WARN_ON(preemptible());
 425
 426         msr_check_and_set(MSR_SPE);
 427
 428         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 429                 check_if_tm_restore_required(current);
 430                 __giveup_spe(current);
 431         }
 432 }
 433 EXPORT_SYMBOL(enable_kernel_spe);
 434
 435 void flush_spe_to_thread(struct task_struct *tsk)
 436 {
 437         if (tsk->thread.regs) {
 438                 preempt_disable();
 439                 if (tsk->thread.regs->msr & MSR_SPE) {
 440                         BUG_ON(tsk != current);
 441                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 442                         giveup_spe(tsk);
 443                 }
 444                 preempt_enable();
 445         }
 446 }
 447 #endif /* CONFIG_SPE */
 448
 449 static unsigned long msr_all_available;
 450
 451 static int __init init_msr_all_available(void)
 452 {
 453 #ifdef CONFIG_PPC_FPU
 454         msr_all_available |= MSR_FP;
 455 #endif
 456 #ifdef CONFIG_ALTIVEC
 457         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 458                 msr_all_available |= MSR_VEC;
 459 #endif
 460 #ifdef CONFIG_VSX
 461         if (cpu_has_feature(CPU_FTR_VSX))
 462                 msr_all_available |= MSR_VSX;
 463 #endif
 464 #ifdef CONFIG_SPE
 465         if (cpu_has_feature(CPU_FTR_SPE))
 466                 msr_all_available |= MSR_SPE;
 467 #endif
 468
 469         return 0;
 470 }
 471 early_initcall(init_msr_all_available);
 472
 473 void giveup_all(struct task_struct *tsk)
 474 {
 475         unsigned long usermsr;
 476
 477         if (!tsk->thread.regs)
 478                 return;
 479
 480         usermsr = tsk->thread.regs->msr;
 481
 482         if ((usermsr & msr_all_available) == 0)
 483                 return;
 484
 485         msr_check_and_set(msr_all_available);
 486         check_if_tm_restore_required(tsk);
 487
 488 #ifdef CONFIG_PPC_FPU
 489         if (usermsr & MSR_FP)
 490                 __giveup_fpu(tsk);
 491 #endif
 492 #ifdef CONFIG_ALTIVEC
 493         if (usermsr & MSR_VEC)
 494                 __giveup_altivec(tsk);
 495 #endif
 496 #ifdef CONFIG_VSX
 497         if (usermsr & MSR_VSX)
 498                 __giveup_vsx(tsk);
 499 #endif
 500 #ifdef CONFIG_SPE
 501         if (usermsr & MSR_SPE)
 502                 __giveup_spe(tsk);
 503 #endif
 504
 505         msr_check_and_clear(msr_all_available);
 506 }
 507 EXPORT_SYMBOL(giveup_all);
 508
 509 void restore_math(struct pt_regs *regs)
 510 {
 511         unsigned long msr;
 512
 513         if (!msr_tm_active(regs->msr) &&
 514                 !current->thread.load_fp && !loadvec(current->thread))
 515                 return;
 516
 517         msr = regs->msr;
 518         msr_check_and_set(msr_all_available);
 519
 520         /*
 521          * Only reload if the bit is not set in the user MSR, the bit BEING set
 522          * indicates that the registers are hot
 523          */
 524         if ((!(msr & MSR_FP)) && restore_fp(current))
 525                 msr |= MSR_FP | current->thread.fpexc_mode;
 526
 527         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 528                 msr |= MSR_VEC;
 529
 530         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 531                         restore_vsx(current)) {
 532                 msr |= MSR_VSX;
 533         }
 534
 535         msr_check_and_clear(msr_all_available);
 536
 537         regs->msr = msr;
 538 }
 539
 540 void save_all(struct task_struct *tsk)
 541 {
 542         unsigned long usermsr;
 543
 544         if (!tsk->thread.regs)
 545                 return;
 546
 547         usermsr = tsk->thread.regs->msr;
 548
 549         if ((usermsr & msr_all_available) == 0)
 550                 return;
 551
 552         msr_check_and_set(msr_all_available);
 553
 554         /*
 555          * Saving the way the register space is in hardware, save_vsx boils
 556          * down to a save_fpu() and save_altivec()
 557          */
 558         if (usermsr & MSR_VSX) {
 559                 save_vsx(tsk);
 560         } else {
 561                 if (usermsr & MSR_FP)
 562                         save_fpu(tsk);
 563
 564                 if (usermsr & MSR_VEC)
 565                         save_altivec(tsk);
 566         }
 567
 568         if (usermsr & MSR_SPE)
 569                 __giveup_spe(tsk);
 570
 571         msr_check_and_clear(msr_all_available);
 572 }
 573
 574 void flush_all_to_thread(struct task_struct *tsk)
 575 {
 576         if (tsk->thread.regs) {
 577                 preempt_disable();
 578                 BUG_ON(tsk != current);
 579                 save_all(tsk);
 580
 581 #ifdef CONFIG_SPE
 582                 if (tsk->thread.regs->msr & MSR_SPE)
 583                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 584 #endif
 585
 586                 preempt_enable();
 587         }
 588 }
 589 EXPORT_SYMBOL(flush_all_to_thread);
 590
 591 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 592 void do_send_trap(struct pt_regs *regs, unsigned long address,
 593                   unsigned long error_code, int signal_code, int breakpt)
 594 {
 595         siginfo_t info;
 596
 597         current->thread.trap_nr = signal_code;
 598         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 599                         11, SIGSEGV) == NOTIFY_STOP)
 600                 return;
 601
 602         /* Deliver the signal to userspace */
 603         info.si_signo = SIGTRAP;
 604         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 605         info.si_code = signal_code;
 606         info.si_addr = (void __user *)address;
 607         force_sig_info(SIGTRAP, &info, current);
 608 }
 609 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 610 void do_break (struct pt_regs *regs, unsigned long address,
 611                     unsigned long error_code)
 612 {
 613         siginfo_t info;
 614
 615         current->thread.trap_nr = TRAP_HWBKPT;
 616         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 617                         11, SIGSEGV) == NOTIFY_STOP)
 618                 return;
 619
 620         if (debugger_break_match(regs))
 621                 return;
 622
 623         /* Clear the breakpoint */
 624         hw_breakpoint_disable();
 625
 626         /* Deliver the signal to userspace */
 627         info.si_signo = SIGTRAP;
 628         info.si_errno = 0;
 629         info.si_code = TRAP_HWBKPT;
 630         info.si_addr = (void __user *)address;
 631         force_sig_info(SIGTRAP, &info, current);
 632 }
 633 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 634
 635 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 636
 637 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 638 /*
 639  * Set the debug registers back to their default "safe" values.
 640  */
 641 static void set_debug_reg_defaults(struct thread_struct *thread)
 642 {
 643         thread->debug.iac1 = thread->debug.iac2 = 0;
 644 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 645         thread->debug.iac3 = thread->debug.iac4 = 0;
 646 #endif
 647         thread->debug.dac1 = thread->debug.dac2 = 0;
 648 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 649         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 650 #endif
 651         thread->debug.dbcr0 = 0;
 652 #ifdef CONFIG_BOOKE
 653         /*
 654          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 655          */
 656         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 657                         DBCR1_IAC3US | DBCR1_IAC4US;
 658         /*
 659          * Force Data Address Compare User/Supervisor bits to be User-only
 660          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 661          */
 662         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 663 #else
 664         thread->debug.dbcr1 = 0;
 665 #endif
 666 }
 667
 668 static void prime_debug_regs(struct debug_reg *debug)
 669 {
 670         /*
 671          * We could have inherited MSR_DE from userspace, since
 672          * it doesn't get cleared on exception entry.  Make sure
 673          * MSR_DE is clear before we enable any debug events.
 674          */
 675         mtmsr(mfmsr() & ~MSR_DE);
 676
 677         mtspr(SPRN_IAC1, debug->iac1);
 678         mtspr(SPRN_IAC2, debug->iac2);
 679 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 680         mtspr(SPRN_IAC3, debug->iac3);
 681         mtspr(SPRN_IAC4, debug->iac4);
 682 #endif
 683         mtspr(SPRN_DAC1, debug->dac1);
 684         mtspr(SPRN_DAC2, debug->dac2);
 685 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 686         mtspr(SPRN_DVC1, debug->dvc1);
 687         mtspr(SPRN_DVC2, debug->dvc2);
 688 #endif
 689         mtspr(SPRN_DBCR0, debug->dbcr0);
 690         mtspr(SPRN_DBCR1, debug->dbcr1);
 691 #ifdef CONFIG_BOOKE
 692         mtspr(SPRN_DBCR2, debug->dbcr2);
 693 #endif
 694 }
 695 /*
 696  * Unless neither the old or new thread are making use of the
 697  * debug registers, set the debug registers from the values
 698  * stored in the new thread.
 699  */
 700 void switch_booke_debug_regs(struct debug_reg *new_debug)
 701 {
 702         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 703                 || (new_debug->dbcr0 & DBCR0_IDM))
 704                         prime_debug_regs(new_debug);
 705 }
 706 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 707 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 708 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 709 static void set_debug_reg_defaults(struct thread_struct *thread)
 710 {
 711         thread->hw_brk.address = 0;
 712         thread->hw_brk.type = 0;
 713         set_breakpoint(&thread->hw_brk);
 714 }
 715 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 716 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 717
 718 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 719 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 720 {
 721         mtspr(SPRN_DAC1, dabr);
 722 #ifdef CONFIG_PPC_47x
 723         isync();
 724 #endif
 725         return 0;
 726 }
 727 #elif defined(CONFIG_PPC_BOOK3S)
 728 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 729 {
 730         mtspr(SPRN_DABR, dabr);
 731         if (cpu_has_feature(CPU_FTR_DABRX))
 732                 mtspr(SPRN_DABRX, dabrx);
 733         return 0;
 734 }
 735 #elif defined(CONFIG_PPC_8xx)
 736 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 737 {
 738         unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
 739         unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
 740         unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
 741
 742         if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
 743                 lctrl1 |= 0xa0000;
 744         else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
 745                 lctrl1 |= 0xf0000;
 746         else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
 747                 lctrl2 = 0;
 748
 749         mtspr(SPRN_LCTRL2, 0);
 750         mtspr(SPRN_CMPE, addr);
 751         mtspr(SPRN_CMPF, addr + 4);
 752         mtspr(SPRN_LCTRL1, lctrl1);
 753         mtspr(SPRN_LCTRL2, lctrl2);
 754
 755         return 0;
 756 }
 757 #else
 758 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 759 {
 760         return -EINVAL;
 761 }
 762 #endif
 763
 764 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 765 {
 766         unsigned long dabr, dabrx;
 767
 768         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 769         dabrx = ((brk->type >> 3) & 0x7);
 770
 771         if (ppc_md.set_dabr)
 772                 return ppc_md.set_dabr(dabr, dabrx);
 773
 774         return __set_dabr(dabr, dabrx);
 775 }
 776
 777 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 778 {
 779         unsigned long dawr, dawrx, mrd;
 780
 781         dawr = brk->address;
 782
 783         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 784                                    << (63 - 58); //* read/write bits */
 785         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 786                                    << (63 - 59); //* translate */
 787         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 788                                    >> 3; //* PRIM bits */
 789         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 790            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 791            0b111111=64DW.
 792            brk->len is in bytes.
 793            This aligns up to double word size, shifts and does the bias.
 794         */
 795         mrd = ((brk->len + 7) >> 3) - 1;
 796         dawrx |= (mrd & 0x3f) << (63 - 53);
 797
 798         if (ppc_md.set_dawr)
 799                 return ppc_md.set_dawr(dawr, dawrx);
 800         mtspr(SPRN_DAWR, dawr);
 801         mtspr(SPRN_DAWRX, dawrx);
 802         return 0;
 803 }
 804
 805 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 806 {
 807         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 808
 809         if (cpu_has_feature(CPU_FTR_DAWR))
 810                 set_dawr(brk);
 811         else
 812                 set_dabr(brk);
 813 }
 814
 815 void set_breakpoint(struct arch_hw_breakpoint *brk)
 816 {
 817         preempt_disable();
 818         __set_breakpoint(brk);
 819         preempt_enable();
 820 }
 821
 822 #ifdef CONFIG_PPC64
 823 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 824 #endif
 825
 826 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 827                               struct arch_hw_breakpoint *b)
 828 {
 829         if (a->address != b->address)
 830                 return false;
 831         if (a->type != b->type)
 832                 return false;
 833         if (a->len != b->len)
 834                 return false;
 835         return true;
 836 }
 837
 838 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 839
 840 static inline bool tm_enabled(struct task_struct *tsk)
 841 {
 842         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 843 }
 844
 845 static void tm_reclaim_thread(struct thread_struct *thr,
 846                               struct thread_info *ti, uint8_t cause)
 847 {
 848         /*
 849          * Use the current MSR TM suspended bit to track if we have
 850          * checkpointed state outstanding.
 851          * On signal delivery, we'd normally reclaim the checkpointed
 852          * state to obtain stack pointer (see:get_tm_stackpointer()).
 853          * This will then directly return to userspace without going
 854          * through __switch_to(). However, if the stack frame is bad,
 855          * we need to exit this thread which calls __switch_to() which
 856          * will again attempt to reclaim the already saved tm state.
 857          * Hence we need to check that we've not already reclaimed
 858          * this state.
 859          * We do this using the current MSR, rather tracking it in
 860          * some specific thread_struct bit, as it has the additional
 861          * benefit of checking for a potential TM bad thing exception.
 862          */
 863         if (!MSR_TM_SUSPENDED(mfmsr()))
 864                 return;
 865
 866         giveup_all(container_of(thr, struct task_struct, thread));
 867
 868         tm_reclaim(thr, thr->ckpt_regs.msr, cause);
 869 }
 870
 871 void tm_reclaim_current(uint8_t cause)
 872 {
 873         tm_enable();
 874         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 875 }
 876
 877 static inline void tm_reclaim_task(struct task_struct *tsk)
 878 {
 879         /* We have to work out if we're switching from/to a task that's in the
 880          * middle of a transaction.
 881          *
 882          * In switching we need to maintain a 2nd register state as
 883          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 884          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 885          * ckvr_state
 886          *
 887          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 888          */
 889         struct thread_struct *thr = &tsk->thread;
 890
 891         if (!thr->regs)
 892                 return;
 893
 894         if (!MSR_TM_ACTIVE(thr->regs->msr))
 895                 goto out_and_saveregs;
 896
 897         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 898                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 899                  tsk->pid, thr->regs->nip,
 900                  thr->regs->ccr, thr->regs->msr,
 901                  thr->regs->trap);
 902
 903         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 904
 905         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 906                  tsk->pid);
 907
 908 out_and_saveregs:
 909         /* Always save the regs here, even if a transaction's not active.
 910          * This context-switches a thread's TM info SPRs.  We do it here to
 911          * be consistent with the restore path (in recheckpoint) which
 912          * cannot happen later in _switch().
 913          */
 914         tm_save_sprs(thr);
 915 }
 916
 917 extern void __tm_recheckpoint(struct thread_struct *thread,
 918                               unsigned long orig_msr);
 919
 920 void tm_recheckpoint(struct thread_struct *thread,
 921                      unsigned long orig_msr)
 922 {
 923         unsigned long flags;
 924
 925         if (!(thread->regs->msr & MSR_TM))
 926                 return;
 927
 928         /* We really can't be interrupted here as the TEXASR registers can't
 929          * change and later in the trecheckpoint code, we have a userspace R1.
 930          * So let's hard disable over this region.
 931          */
 932         local_irq_save(flags);
 933         hard_irq_disable();
 934
 935         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 936          * before the trecheckpoint and no explosion occurs.
 937          */
 938         tm_restore_sprs(thread);
 939
 940         __tm_recheckpoint(thread, orig_msr);
 941
 942         local_irq_restore(flags);
 943 }
 944
 945 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 946 {
 947         unsigned long msr;
 948
 949         if (!cpu_has_feature(CPU_FTR_TM))
 950                 return;
 951
 952         /* Recheckpoint the registers of the thread we're about to switch to.
 953          *
 954          * If the task was using FP, we non-lazily reload both the original and
 955          * the speculative FP register states.  This is because the kernel
 956          * doesn't see if/when a TM rollback occurs, so if we take an FP
 957          * unavailable later, we are unable to determine which set of FP regs
 958          * need to be restored.
 959          */
 960         if (!tm_enabled(new))
 961                 return;
 962
 963         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 964                 tm_restore_sprs(&new->thread);
 965                 return;
 966         }
 967         msr = new->thread.ckpt_regs.msr;
 968         /* Recheckpoint to restore original checkpointed register state. */
 969         TM_DEBUG("*** tm_recheckpoint of pid %d "
 970                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 971                  new->pid, new->thread.regs->msr, msr);
 972
 973         tm_recheckpoint(&new->thread, msr);
 974
 975         /*
 976          * The checkpointed state has been restored but the live state has
 977          * not, ensure all the math functionality is turned off to trigger
 978          * restore_math() to reload.
 979          */
 980         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
 981
 982         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 983                  "(kernel msr 0x%lx)\n",
 984                  new->pid, mfmsr());
 985 }
 986
 987 static inline void __switch_to_tm(struct task_struct *prev,
 988                 struct task_struct *new)
 989 {
 990         if (cpu_has_feature(CPU_FTR_TM)) {
 991                 if (tm_enabled(prev) || tm_enabled(new))
 992                         tm_enable();
 993
 994                 if (tm_enabled(prev)) {
 995                         prev->thread.load_tm++;
 996                         tm_reclaim_task(prev);
 997                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
 998                                 prev->thread.regs->msr &= ~MSR_TM;
 999                 }
1000
1001                 tm_recheckpoint_new_task(new);
1002         }
1003 }
1004
1005 /*
1006  * This is called if we are on the way out to userspace and the
1007  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1008  * FP and/or vector state and does so if necessary.
1009  * If userspace is inside a transaction (whether active or
1010  * suspended) and FP/VMX/VSX instructions have ever been enabled
1011  * inside that transaction, then we have to keep them enabled
1012  * and keep the FP/VMX/VSX state loaded while ever the transaction
1013  * continues.  The reason is that if we didn't, and subsequently
1014  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1015  * we don't know whether it's the same transaction, and thus we
1016  * don't know which of the checkpointed state and the transactional
1017  * state to use.
1018  */
1019 void restore_tm_state(struct pt_regs *regs)
1020 {
1021         unsigned long msr_diff;
1022
1023         /*
1024          * This is the only moment we should clear TIF_RESTORE_TM as
1025          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1026          * again, anything else could lead to an incorrect ckpt_msr being
1027          * saved and therefore incorrect signal contexts.
1028          */
1029         clear_thread_flag(TIF_RESTORE_TM);
1030         if (!MSR_TM_ACTIVE(regs->msr))
1031                 return;
1032
1033         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1034         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1035
1036         /* Ensure that restore_math() will restore */
1037         if (msr_diff & MSR_FP)
1038                 current->thread.load_fp = 1;
1039 #ifdef CONFIG_ALTIVEC
1040         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1041                 current->thread.load_vec = 1;
1042 #endif
1043         restore_math(regs);
1044
1045         regs->msr |= msr_diff;
1046 }
1047
1048 #else
1049 #define tm_recheckpoint_new_task(new)
1050 #define __switch_to_tm(prev, new)
1051 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1052
1053 static inline void save_sprs(struct thread_struct *t)
1054 {
1055 #ifdef CONFIG_ALTIVEC
1056         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1057                 t->vrsave = mfspr(SPRN_VRSAVE);
1058 #endif
1059 #ifdef CONFIG_PPC_BOOK3S_64
1060         if (cpu_has_feature(CPU_FTR_DSCR))
1061                 t->dscr = mfspr(SPRN_DSCR);
1062
1063         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1064                 t->bescr = mfspr(SPRN_BESCR);
1065                 t->ebbhr = mfspr(SPRN_EBBHR);
1066                 t->ebbrr = mfspr(SPRN_EBBRR);
1067
1068                 t->fscr = mfspr(SPRN_FSCR);
1069
1070                 /*
1071                  * Note that the TAR is not available for use in the kernel.
1072                  * (To provide this, the TAR should be backed up/restored on
1073                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1074                  * this should be in pt_regs anyway (for debug).)
1075                  */
1076                 t->tar = mfspr(SPRN_TAR);
1077         }
1078 #endif
1079 }
1080
1081 static inline void restore_sprs(struct thread_struct *old_thread,
1082                                 struct thread_struct *new_thread)
1083 {
1084 #ifdef CONFIG_ALTIVEC
1085         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1086             old_thread->vrsave != new_thread->vrsave)
1087                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1088 #endif
1089 #ifdef CONFIG_PPC_BOOK3S_64
1090         if (cpu_has_feature(CPU_FTR_DSCR)) {
1091                 u64 dscr = get_paca()->dscr_default;
1092                 if (new_thread->dscr_inherit)
1093                         dscr = new_thread->dscr;
1094
1095                 if (old_thread->dscr != dscr)
1096                         mtspr(SPRN_DSCR, dscr);
1097         }
1098
1099         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1100                 if (old_thread->bescr != new_thread->bescr)
1101                         mtspr(SPRN_BESCR, new_thread->bescr);
1102                 if (old_thread->ebbhr != new_thread->ebbhr)
1103                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1104                 if (old_thread->ebbrr != new_thread->ebbrr)
1105                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1106
1107                 if (old_thread->fscr != new_thread->fscr)
1108                         mtspr(SPRN_FSCR, new_thread->fscr);
1109
1110                 if (old_thread->tar != new_thread->tar)
1111                         mtspr(SPRN_TAR, new_thread->tar);
1112         }
1113 #endif
1114 }
1115
1116 struct task_struct *__switch_to(struct task_struct *prev,
1117         struct task_struct *new)
1118 {
1119         struct thread_struct *new_thread, *old_thread;
1120         struct task_struct *last;
1121 #ifdef CONFIG_PPC_BOOK3S_64
1122         struct ppc64_tlb_batch *batch;
1123 #endif
1124
1125         new_thread = &new->thread;
1126         old_thread = &current->thread;
1127
1128         WARN_ON(!irqs_disabled());
1129
1130 #ifdef CONFIG_PPC64
1131         /*
1132          * Collect processor utilization data per process
1133          */
1134         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1135                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1136                 long unsigned start_tb, current_tb;
1137                 start_tb = old_thread->start_tb;
1138                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1139                 old_thread->accum_tb += (current_tb - start_tb);
1140                 new_thread->start_tb = current_tb;
1141         }
1142 #endif /* CONFIG_PPC64 */
1143
1144 #ifdef CONFIG_PPC_STD_MMU_64
1145         batch = this_cpu_ptr(&ppc64_tlb_batch);
1146         if (batch->active) {
1147                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1148                 if (batch->index)
1149                         __flush_tlb_pending(batch);
1150                 batch->active = 0;
1151         }
1152 #endif /* CONFIG_PPC_STD_MMU_64 */
1153
1154 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1155         switch_booke_debug_regs(&new->thread.debug);
1156 #else
1157 /*
1158  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1159  * schedule DABR
1160  */
1161 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1162         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1163                 __set_breakpoint(&new->thread.hw_brk);
1164 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1165 #endif
1166
1167         /*
1168          * We need to save SPRs before treclaim/trecheckpoint as these will
1169          * change a number of them.
1170          */
1171         save_sprs(&prev->thread);
1172
1173         /* Save FPU, Altivec, VSX and SPE state */
1174         giveup_all(prev);
1175
1176         __switch_to_tm(prev, new);
1177
1178         /*
1179          * We can't take a PMU exception inside _switch() since there is a
1180          * window where the kernel stack SLB and the kernel stack are out
1181          * of sync. Hard disable here.
1182          */
1183         hard_irq_disable();
1184
1185         /*
1186          * Call restore_sprs() before calling _switch(). If we move it after
1187          * _switch() then we miss out on calling it for new tasks. The reason
1188          * for this is we manually create a stack frame for new tasks that
1189          * directly returns through ret_from_fork() or
1190          * ret_from_kernel_thread(). See copy_thread() for details.
1191          */
1192         restore_sprs(old_thread, new_thread);
1193
1194         last = _switch(old_thread, new_thread);
1195
1196 #ifdef CONFIG_PPC_STD_MMU_64
1197         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1198                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1199                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1200                 batch->active = 1;
1201         }
1202
1203         if (current_thread_info()->task->thread.regs)
1204                 restore_math(current_thread_info()->task->thread.regs);
1205 #endif /* CONFIG_PPC_STD_MMU_64 */
1206
1207         return last;
1208 }
1209
1210 static int instructions_to_print = 16;
1211
1212 static void show_instructions(struct pt_regs *regs)
1213 {
1214         int i;
1215         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1216                         sizeof(int));
1217
1218         printk("Instruction dump:");
1219
1220         for (i = 0; i < instructions_to_print; i++) {
1221                 int instr;
1222
1223                 if (!(i % 8))
1224                         pr_cont("\n");
1225
1226 #if !defined(CONFIG_BOOKE)
1227                 /* If executing with the IMMU off, adjust pc rather
1228                  * than print XXXXXXXX.
1229                  */
1230                 if (!(regs->msr & MSR_IR))
1231                         pc = (unsigned long)phys_to_virt(pc);
1232 #endif
1233
1234                 if (!__kernel_text_address(pc) ||
1235                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1236                         pr_cont("XXXXXXXX ");
1237                 } else {
1238                         if (regs->nip == pc)
1239                                 pr_cont("<%08x> ", instr);
1240                         else
1241                                 pr_cont("%08x ", instr);
1242                 }
1243
1244                 pc += sizeof(int);
1245         }
1246
1247         pr_cont("\n");
1248 }
1249
1250 struct regbit {
1251         unsigned long bit;
1252         const char *name;
1253 };
1254
1255 static struct regbit msr_bits[] = {
1256 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1257         {MSR_SF,        "SF"},
1258         {MSR_HV,        "HV"},
1259 #endif
1260         {MSR_VEC,       "VEC"},
1261         {MSR_VSX,       "VSX"},
1262 #ifdef CONFIG_BOOKE
1263         {MSR_CE,        "CE"},
1264 #endif
1265         {MSR_EE,        "EE"},
1266         {MSR_PR,        "PR"},
1267         {MSR_FP,        "FP"},
1268         {MSR_ME,        "ME"},
1269 #ifdef CONFIG_BOOKE
1270         {MSR_DE,        "DE"},
1271 #else
1272         {MSR_SE,        "SE"},
1273         {MSR_BE,        "BE"},
1274 #endif
1275         {MSR_IR,        "IR"},
1276         {MSR_DR,        "DR"},
1277         {MSR_PMM,       "PMM"},
1278 #ifndef CONFIG_BOOKE
1279         {MSR_RI,        "RI"},
1280         {MSR_LE,        "LE"},
1281 #endif
1282         {0,             NULL}
1283 };
1284
1285 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1286 {
1287         const char *s = "";
1288
1289         for (; bits->bit; ++bits)
1290                 if (val & bits->bit) {
1291                         pr_cont("%s%s", s, bits->name);
1292                         s = sep;
1293                 }
1294 }
1295
1296 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1297 static struct regbit msr_tm_bits[] = {
1298         {MSR_TS_T,      "T"},
1299         {MSR_TS_S,      "S"},
1300         {MSR_TM,        "E"},
1301         {0,             NULL}
1302 };
1303
1304 static void print_tm_bits(unsigned long val)
1305 {
1306 /*
1307  * This only prints something if at least one of the TM bit is set.
1308  * Inside the TM[], the output means:
1309  *   E: Enabled         (bit 32)
1310  *   S: Suspended       (bit 33)
1311  *   T: Transactional   (bit 34)
1312  */
1313         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1314                 pr_cont(",TM[");
1315                 print_bits(val, msr_tm_bits, "");
1316                 pr_cont("]");
1317         }
1318 }
1319 #else
1320 static void print_tm_bits(unsigned long val) {}
1321 #endif
1322
1323 static void print_msr_bits(unsigned long val)
1324 {
1325         pr_cont("<");
1326         print_bits(val, msr_bits, ",");
1327         print_tm_bits(val);
1328         pr_cont(">");
1329 }
1330
1331 #ifdef CONFIG_PPC64
1332 #define REG             "%016lx"
1333 #define REGS_PER_LINE   4
1334 #define LAST_VOLATILE   13
1335 #else
1336 #define REG             "%08lx"
1337 #define REGS_PER_LINE   8
1338 #define LAST_VOLATILE   12
1339 #endif
1340
1341 void show_regs(struct pt_regs * regs)
1342 {
1343         int i, trap;
1344
1345         show_regs_print_info(KERN_DEFAULT);
1346
1347         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1348                regs->nip, regs->link, regs->ctr);
1349         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1350                regs, regs->trap, print_tainted(), init_utsname()->release);
1351         printk("MSR: "REG" ", regs->msr);
1352         print_msr_bits(regs->msr);
1353         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1354         trap = TRAP(regs);
1355         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1356                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1357         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1358 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1359                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1360 #else
1361                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1362 #endif
1363 #ifdef CONFIG_PPC64
1364         pr_cont("SOFTE: %ld ", regs->softe);
1365 #endif
1366 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1367         if (MSR_TM_ACTIVE(regs->msr))
1368                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1369 #endif
1370
1371         for (i = 0;  i < 32;  i++) {
1372                 if ((i % REGS_PER_LINE) == 0)
1373                         pr_cont("\nGPR%02d: ", i);
1374                 pr_cont(REG " ", regs->gpr[i]);
1375                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1376                         break;
1377         }
1378         pr_cont("\n");
1379 #ifdef CONFIG_KALLSYMS
1380         /*
1381          * Lookup NIP late so we have the best change of getting the
1382          * above info out without failing
1383          */
1384         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1385         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1386 #endif
1387         show_stack(current, (unsigned long *) regs->gpr[1]);
1388         if (!user_mode(regs))
1389                 show_instructions(regs);
1390 }
1391
1392 void flush_thread(void)
1393 {
1394 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1395         flush_ptrace_hw_breakpoint(current);
1396 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1397         set_debug_reg_defaults(&current->thread);
1398 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1399 }
1400
1401 void
1402 release_thread(struct task_struct *t)
1403 {
1404 }
1405
1406 /*
1407  * this gets called so that we can store coprocessor state into memory and
1408  * copy the current task into the new thread.
1409  */
1410 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1411 {
1412         flush_all_to_thread(src);
1413         /*
1414          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1415          * flush but it removes the checkpointed state from the current CPU and
1416          * transitions the CPU out of TM mode.  Hence we need to call
1417          * tm_recheckpoint_new_task() (on the same task) to restore the
1418          * checkpointed state back and the TM mode.
1419          *
1420          * Can't pass dst because it isn't ready. Doesn't matter, passing
1421          * dst is only important for __switch_to()
1422          */
1423         __switch_to_tm(src, src);
1424
1425         *dst = *src;
1426
1427         clear_task_ebb(dst);
1428
1429         return 0;
1430 }
1431
1432 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1433 {
1434 #ifdef CONFIG_PPC_STD_MMU_64
1435         unsigned long sp_vsid;
1436         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1437
1438         if (radix_enabled())
1439                 return;
1440
1441         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1442                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1443                         << SLB_VSID_SHIFT_1T;
1444         else
1445                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1446                         << SLB_VSID_SHIFT;
1447         sp_vsid |= SLB_VSID_KERNEL | llp;
1448         p->thread.ksp_vsid = sp_vsid;
1449 #endif
1450 }
1451
1452 /*
1453  * Copy a thread..
1454  */
1455
1456 /*
1457  * Copy architecture-specific thread state
1458  */
1459 int copy_thread(unsigned long clone_flags, unsigned long usp,
1460                 unsigned long kthread_arg, struct task_struct *p)
1461 {
1462         struct pt_regs *childregs, *kregs;
1463         extern void ret_from_fork(void);
1464         extern void ret_from_kernel_thread(void);
1465         void (*f)(void);
1466         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1467         struct thread_info *ti = task_thread_info(p);
1468
1469         klp_init_thread_info(ti);
1470
1471         /* Copy registers */
1472         sp -= sizeof(struct pt_regs);
1473         childregs = (struct pt_regs *) sp;
1474         if (unlikely(p->flags & PF_KTHREAD)) {
1475                 /* kernel thread */
1476                 memset(childregs, 0, sizeof(struct pt_regs));
1477                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1478                 /* function */
1479                 if (usp)
1480                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1481 #ifdef CONFIG_PPC64
1482                 clear_tsk_thread_flag(p, TIF_32BIT);
1483                 childregs->softe = 1;
1484 #endif
1485                 childregs->gpr[15] = kthread_arg;
1486                 p->thread.regs = NULL;  /* no user register state */
1487                 ti->flags |= _TIF_RESTOREALL;
1488                 f = ret_from_kernel_thread;
1489         } else {
1490                 /* user thread */
1491                 struct pt_regs *regs = current_pt_regs();
1492                 CHECK_FULL_REGS(regs);
1493                 *childregs = *regs;
1494                 if (usp)
1495                         childregs->gpr[1] = usp;
1496                 p->thread.regs = childregs;
1497                 childregs->gpr[3] = 0;  /* Result from fork() */
1498                 if (clone_flags & CLONE_SETTLS) {
1499 #ifdef CONFIG_PPC64
1500                         if (!is_32bit_task())
1501                                 childregs->gpr[13] = childregs->gpr[6];
1502                         else
1503 #endif
1504                                 childregs->gpr[2] = childregs->gpr[6];
1505                 }
1506
1507                 f = ret_from_fork;
1508         }
1509         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1510         sp -= STACK_FRAME_OVERHEAD;
1511
1512         /*
1513          * The way this works is that at some point in the future
1514          * some task will call _switch to switch to the new task.
1515          * That will pop off the stack frame created below and start
1516          * the new task running at ret_from_fork.  The new task will
1517          * do some house keeping and then return from the fork or clone
1518          * system call, using the stack frame created above.
1519          */
1520         ((unsigned long *)sp)[0] = 0;
1521         sp -= sizeof(struct pt_regs);
1522         kregs = (struct pt_regs *) sp;
1523         sp -= STACK_FRAME_OVERHEAD;
1524         p->thread.ksp = sp;
1525 #ifdef CONFIG_PPC32
1526         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1527                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1528 #endif
1529 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1530         p->thread.ptrace_bps[0] = NULL;
1531 #endif
1532
1533         p->thread.fp_save_area = NULL;
1534 #ifdef CONFIG_ALTIVEC
1535         p->thread.vr_save_area = NULL;
1536 #endif
1537
1538         setup_ksp_vsid(p, sp);
1539
1540 #ifdef CONFIG_PPC64
1541         if (cpu_has_feature(CPU_FTR_DSCR)) {
1542                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1543                 p->thread.dscr = mfspr(SPRN_DSCR);
1544         }
1545         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1546                 p->thread.ppr = INIT_PPR;
1547 #endif
1548         kregs->nip = ppc_function_entry(f);
1549         return 0;
1550 }
1551
1552 /*
1553  * Set up a thread for executing a new program
1554  */
1555 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1556 {
1557 #ifdef CONFIG_PPC64
1558         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1559 #endif
1560
1561         /*
1562          * If we exec out of a kernel thread then thread.regs will not be
1563          * set.  Do it now.
1564          */
1565         if (!current->thread.regs) {
1566                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1567                 current->thread.regs = regs - 1;
1568         }
1569
1570 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1571         /*
1572          * Clear any transactional state, we're exec()ing. The cause is
1573          * not important as there will never be a recheckpoint so it's not
1574          * user visible.
1575          */
1576         if (MSR_TM_SUSPENDED(mfmsr()))
1577                 tm_reclaim_current(0);
1578 #endif
1579
1580         memset(regs->gpr, 0, sizeof(regs->gpr));
1581         regs->ctr = 0;
1582         regs->link = 0;
1583         regs->xer = 0;
1584         regs->ccr = 0;
1585         regs->gpr[1] = sp;
1586
1587         /*
1588          * We have just cleared all the nonvolatile GPRs, so make
1589          * FULL_REGS(regs) return true.  This is necessary to allow
1590          * ptrace to examine the thread immediately after exec.
1591          */
1592         regs->trap &= ~1UL;
1593
1594 #ifdef CONFIG_PPC32
1595         regs->mq = 0;
1596         regs->nip = start;
1597         regs->msr = MSR_USER;
1598 #else
1599         if (!is_32bit_task()) {
1600                 unsigned long entry;
1601
1602                 if (is_elf2_task()) {
1603                         /* Look ma, no function descriptors! */
1604                         entry = start;
1605
1606                         /*
1607                          * Ulrich says:
1608                          *   The latest iteration of the ABI requires that when
1609                          *   calling a function (at its global entry point),
1610                          *   the caller must ensure r12 holds the entry point
1611                          *   address (so that the function can quickly
1612                          *   establish addressability).
1613                          */
1614                         regs->gpr[12] = start;
1615                         /* Make sure that's restored on entry to userspace. */
1616                         set_thread_flag(TIF_RESTOREALL);
1617                 } else {
1618                         unsigned long toc;
1619
1620                         /* start is a relocated pointer to the function
1621                          * descriptor for the elf _start routine.  The first
1622                          * entry in the function descriptor is the entry
1623                          * address of _start and the second entry is the TOC
1624                          * value we need to use.
1625                          */
1626                         __get_user(entry, (unsigned long __user *)start);
1627                         __get_user(toc, (unsigned long __user *)start+1);
1628
1629                         /* Check whether the e_entry function descriptor entries
1630                          * need to be relocated before we can use them.
1631                          */
1632                         if (load_addr != 0) {
1633                                 entry += load_addr;
1634                                 toc   += load_addr;
1635                         }
1636                         regs->gpr[2] = toc;
1637                 }
1638                 regs->nip = entry;
1639                 regs->msr = MSR_USER64;
1640         } else {
1641                 regs->nip = start;
1642                 regs->gpr[2] = 0;
1643                 regs->msr = MSR_USER32;
1644         }
1645 #endif
1646 #ifdef CONFIG_VSX
1647         current->thread.used_vsr = 0;
1648 #endif
1649         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1650         current->thread.fp_save_area = NULL;
1651 #ifdef CONFIG_ALTIVEC
1652         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1653         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1654         current->thread.vr_save_area = NULL;
1655         current->thread.vrsave = 0;
1656         current->thread.used_vr = 0;
1657 #endif /* CONFIG_ALTIVEC */
1658 #ifdef CONFIG_SPE
1659         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1660         current->thread.acc = 0;
1661         current->thread.spefscr = 0;
1662         current->thread.used_spe = 0;
1663 #endif /* CONFIG_SPE */
1664 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1665         current->thread.tm_tfhar = 0;
1666         current->thread.tm_texasr = 0;
1667         current->thread.tm_tfiar = 0;
1668 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1669 }
1670 EXPORT_SYMBOL(start_thread);
1671
1672 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1673                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1674
1675 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1676 {
1677         struct pt_regs *regs = tsk->thread.regs;
1678
1679         /* This is a bit hairy.  If we are an SPE enabled  processor
1680          * (have embedded fp) we store the IEEE exception enable flags in
1681          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1682          * mode (asyn, precise, disabled) for 'Classic' FP. */
1683         if (val & PR_FP_EXC_SW_ENABLE) {
1684 #ifdef CONFIG_SPE
1685                 if (cpu_has_feature(CPU_FTR_SPE)) {
1686                         /*
1687                          * When the sticky exception bits are set
1688                          * directly by userspace, it must call prctl
1689                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1690                          * in the existing prctl settings) or
1691                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1692                          * the bits being set).  <fenv.h> functions
1693                          * saving and restoring the whole
1694                          * floating-point environment need to do so
1695                          * anyway to restore the prctl settings from
1696                          * the saved environment.
1697                          */
1698                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1699                         tsk->thread.fpexc_mode = val &
1700                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1701                         return 0;
1702                 } else {
1703                         return -EINVAL;
1704                 }
1705 #else
1706                 return -EINVAL;
1707 #endif
1708         }
1709
1710         /* on a CONFIG_SPE this does not hurt us.  The bits that
1711          * __pack_fe01 use do not overlap with bits used for
1712          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1713          * on CONFIG_SPE implementations are reserved so writing to
1714          * them does not change anything */
1715         if (val > PR_FP_EXC_PRECISE)
1716                 return -EINVAL;
1717         tsk->thread.fpexc_mode = __pack_fe01(val);
1718         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1719                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1720                         | tsk->thread.fpexc_mode;
1721         return 0;
1722 }
1723
1724 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1725 {
1726         unsigned int val;
1727
1728         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1729 #ifdef CONFIG_SPE
1730                 if (cpu_has_feature(CPU_FTR_SPE)) {
1731                         /*
1732                          * When the sticky exception bits are set
1733                          * directly by userspace, it must call prctl
1734                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1735                          * in the existing prctl settings) or
1736                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1737                          * the bits being set).  <fenv.h> functions
1738                          * saving and restoring the whole
1739                          * floating-point environment need to do so
1740                          * anyway to restore the prctl settings from
1741                          * the saved environment.
1742                          */
1743                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1744                         val = tsk->thread.fpexc_mode;
1745                 } else
1746                         return -EINVAL;
1747 #else
1748                 return -EINVAL;
1749 #endif
1750         else
1751                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1752         return put_user(val, (unsigned int __user *) adr);
1753 }
1754
1755 int set_endian(struct task_struct *tsk, unsigned int val)
1756 {
1757         struct pt_regs *regs = tsk->thread.regs;
1758
1759         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1760             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1761                 return -EINVAL;
1762
1763         if (regs == NULL)
1764                 return -EINVAL;
1765
1766         if (val == PR_ENDIAN_BIG)
1767                 regs->msr &= ~MSR_LE;
1768         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1769                 regs->msr |= MSR_LE;
1770         else
1771                 return -EINVAL;
1772
1773         return 0;
1774 }
1775
1776 int get_endian(struct task_struct *tsk, unsigned long adr)
1777 {
1778         struct pt_regs *regs = tsk->thread.regs;
1779         unsigned int val;
1780
1781         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1782             !cpu_has_feature(CPU_FTR_REAL_LE))
1783                 return -EINVAL;
1784
1785         if (regs == NULL)
1786                 return -EINVAL;
1787
1788         if (regs->msr & MSR_LE) {
1789                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1790                         val = PR_ENDIAN_LITTLE;
1791                 else
1792                         val = PR_ENDIAN_PPC_LITTLE;
1793         } else
1794                 val = PR_ENDIAN_BIG;
1795
1796         return put_user(val, (unsigned int __user *)adr);
1797 }
1798
1799 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1800 {
1801         tsk->thread.align_ctl = val;
1802         return 0;
1803 }
1804
1805 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1806 {
1807         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1808 }
1809
1810 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1811                                   unsigned long nbytes)
1812 {
1813         unsigned long stack_page;
1814         unsigned long cpu = task_cpu(p);
1815
1816         /*
1817          * Avoid crashing if the stack has overflowed and corrupted
1818          * task_cpu(p), which is in the thread_info struct.
1819          */
1820         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1821                 stack_page = (unsigned long) hardirq_ctx[cpu];
1822                 if (sp >= stack_page + sizeof(struct thread_struct)
1823                     && sp <= stack_page + THREAD_SIZE - nbytes)
1824                         return 1;
1825
1826                 stack_page = (unsigned long) softirq_ctx[cpu];
1827                 if (sp >= stack_page + sizeof(struct thread_struct)
1828                     && sp <= stack_page + THREAD_SIZE - nbytes)
1829                         return 1;
1830         }
1831         return 0;
1832 }
1833
1834 int validate_sp(unsigned long sp, struct task_struct *p,
1835                        unsigned long nbytes)
1836 {
1837         unsigned long stack_page = (unsigned long)task_stack_page(p);
1838
1839         if (sp >= stack_page + sizeof(struct thread_struct)
1840             && sp <= stack_page + THREAD_SIZE - nbytes)
1841                 return 1;
1842
1843         return valid_irq_stack(sp, p, nbytes);
1844 }
1845
1846 EXPORT_SYMBOL(validate_sp);
1847
1848 unsigned long get_wchan(struct task_struct *p)
1849 {
1850         unsigned long ip, sp;
1851         int count = 0;
1852
1853         if (!p || p == current || p->state == TASK_RUNNING)
1854                 return 0;
1855
1856         sp = p->thread.ksp;
1857         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1858                 return 0;
1859
1860         do {
1861                 sp = *(unsigned long *)sp;
1862                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1863                         return 0;
1864                 if (count > 0) {
1865                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1866                         if (!in_sched_functions(ip))
1867                                 return ip;
1868                 }
1869         } while (count++ < 16);
1870         return 0;
1871 }
1872
1873 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1874
1875 void show_stack(struct task_struct *tsk, unsigned long *stack)
1876 {
1877         unsigned long sp, ip, lr, newsp;
1878         int count = 0;
1879         int firstframe = 1;
1880 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1881         int curr_frame = current->curr_ret_stack;
1882         extern void return_to_handler(void);
1883         unsigned long rth = (unsigned long)return_to_handler;
1884 #endif
1885
1886         sp = (unsigned long) stack;
1887         if (tsk == NULL)
1888                 tsk = current;
1889         if (sp == 0) {
1890                 if (tsk == current)
1891                         sp = current_stack_pointer();
1892                 else
1893                         sp = tsk->thread.ksp;
1894         }
1895
1896         lr = 0;
1897         printk("Call Trace:\n");
1898         do {
1899                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1900                         return;
1901
1902                 stack = (unsigned long *) sp;
1903                 newsp = stack[0];
1904                 ip = stack[STACK_FRAME_LR_SAVE];
1905                 if (!firstframe || ip != lr) {
1906                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1907 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1908                         if ((ip == rth) && curr_frame >= 0) {
1909                                 pr_cont(" (%pS)",
1910                                        (void *)current->ret_stack[curr_frame].ret);
1911                                 curr_frame--;
1912                         }
1913 #endif
1914                         if (firstframe)
1915                                 pr_cont(" (unreliable)");
1916                         pr_cont("\n");
1917                 }
1918                 firstframe = 0;
1919
1920                 /*
1921                  * See if this is an exception frame.
1922                  * We look for the "regshere" marker in the current frame.
1923                  */
1924                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1925                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1926                         struct pt_regs *regs = (struct pt_regs *)
1927                                 (sp + STACK_FRAME_OVERHEAD);
1928                         lr = regs->link;
1929                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1930                                regs->trap, (void *)regs->nip, (void *)lr);
1931                         firstframe = 1;
1932                 }
1933
1934                 sp = newsp;
1935         } while (count++ < kstack_depth_to_print);
1936 }
1937
1938 #ifdef CONFIG_PPC64
1939 /* Called with hard IRQs off */
1940 void notrace __ppc64_runlatch_on(void)
1941 {
1942         struct thread_info *ti = current_thread_info();
1943         unsigned long ctrl;
1944
1945         ctrl = mfspr(SPRN_CTRLF);
1946         ctrl |= CTRL_RUNLATCH;
1947         mtspr(SPRN_CTRLT, ctrl);
1948
1949         ti->local_flags |= _TLF_RUNLATCH;
1950 }
1951
1952 /* Called with hard IRQs off */
1953 void notrace __ppc64_runlatch_off(void)
1954 {
1955         struct thread_info *ti = current_thread_info();
1956         unsigned long ctrl;
1957
1958         ti->local_flags &= ~_TLF_RUNLATCH;
1959
1960         ctrl = mfspr(SPRN_CTRLF);
1961         ctrl &= ~CTRL_RUNLATCH;
1962         mtspr(SPRN_CTRLT, ctrl);
1963 }
1964 #endif /* CONFIG_PPC64 */
1965
1966 unsigned long arch_align_stack(unsigned long sp)
1967 {
1968         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1969                 sp -= get_random_int() & ~PAGE_MASK;
1970         return sp & ~0xf;
1971 }
1972
1973 static inline unsigned long brk_rnd(void)
1974 {
1975         unsigned long rnd = 0;
1976
1977         /* 8MB for 32bit, 1GB for 64bit */
1978         if (is_32bit_task())
1979                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1980         else
1981                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1982
1983         return rnd << PAGE_SHIFT;
1984 }
1985
1986 unsigned long arch_randomize_brk(struct mm_struct *mm)
1987 {
1988         unsigned long base = mm->brk;
1989         unsigned long ret;
1990
1991 #ifdef CONFIG_PPC_STD_MMU_64
1992         /*
1993          * If we are using 1TB segments and we are allowed to randomise
1994          * the heap, we can put it above 1TB so it is backed by a 1TB
1995          * segment. Otherwise the heap will be in the bottom 1TB
1996          * which always uses 256MB segments and this may result in a
1997          * performance penalty. We don't need to worry about radix. For
1998          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1999          */
2000         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2001                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2002 #endif
2003
2004         ret = PAGE_ALIGN(base + brk_rnd());
2005
2006         if (ret < mm->brk)
2007                 return mm->brk;
2008
2009         return ret;
2010 }
2011