arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41
  42 #include <asm/pgtable.h>
  43 #include <asm/io.h>
  44 #include <asm/processor.h>
  45 #include <asm/mmu.h>
  46 #include <asm/prom.h>
  47 #include <asm/machdep.h>
  48 #include <asm/time.h>
  49 #include <asm/runlatch.h>
  50 #include <asm/syscalls.h>
  51 #include <asm/switch_to.h>
  52 #include <asm/tm.h>
  53 #include <asm/debug.h>
  54 #ifdef CONFIG_PPC64
  55 #include <asm/firmware.h>
  56 #endif
  57 #include <asm/code-patching.h>
  58 #include <linux/kprobes.h>
  59 #include <linux/kdebug.h>
  60
  61 /* Transactional Memory debug */
  62 #ifdef TM_DEBUG_SW
  63 #define TM_DEBUG(x...) printk(KERN_INFO x)
  64 #else
  65 #define TM_DEBUG(x...) do { } while(0)
  66 #endif
  67
  68 extern unsigned long _get_SP(void);
  69
  70 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  71 static void check_if_tm_restore_required(struct task_struct *tsk)
  72 {
  73         /*
  74          * If we are saving the current thread's registers, and the
  75          * thread is in a transactional state, set the TIF_RESTORE_TM
  76          * bit so that we know to restore the registers before
  77          * returning to userspace.
  78          */
  79         if (tsk == current && tsk->thread.regs &&
  80             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  81             !test_thread_flag(TIF_RESTORE_TM)) {
  82                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  83                 set_thread_flag(TIF_RESTORE_TM);
  84         }
  85 }
  86 #else
  87 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
  88 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  89
  90 bool strict_msr_control;
  91 EXPORT_SYMBOL(strict_msr_control);
  92
  93 static int __init enable_strict_msr_control(char *str)
  94 {
  95         strict_msr_control = true;
  96         pr_info("Enabling strict facility control\n");
  97
  98         return 0;
  99 }
 100 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 101
 102 void msr_check_and_set(unsigned long bits)
 103 {
 104         unsigned long oldmsr = mfmsr();
 105         unsigned long newmsr;
 106
 107         newmsr = oldmsr | bits;
 108
 109 #ifdef CONFIG_VSX
 110         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 111                 newmsr |= MSR_VSX;
 112 #endif
 113
 114         if (oldmsr != newmsr)
 115                 mtmsr_isync(newmsr);
 116 }
 117
 118 void __msr_check_and_clear(unsigned long bits)
 119 {
 120         unsigned long oldmsr = mfmsr();
 121         unsigned long newmsr;
 122
 123         newmsr = oldmsr & ~bits;
 124
 125 #ifdef CONFIG_VSX
 126         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 127                 newmsr &= ~MSR_VSX;
 128 #endif
 129
 130         if (oldmsr != newmsr)
 131                 mtmsr_isync(newmsr);
 132 }
 133 EXPORT_SYMBOL(__msr_check_and_clear);
 134
 135 #ifdef CONFIG_PPC_FPU
 136 void giveup_fpu(struct task_struct *tsk)
 137 {
 138         check_if_tm_restore_required(tsk);
 139
 140         msr_check_and_set(MSR_FP);
 141         __giveup_fpu(tsk);
 142         msr_check_and_clear(MSR_FP);
 143 }
 144 EXPORT_SYMBOL(giveup_fpu);
 145
 146 /*
 147  * Make sure the floating-point register state in the
 148  * the thread_struct is up to date for task tsk.
 149  */
 150 void flush_fp_to_thread(struct task_struct *tsk)
 151 {
 152         if (tsk->thread.regs) {
 153                 /*
 154                  * We need to disable preemption here because if we didn't,
 155                  * another process could get scheduled after the regs->msr
 156                  * test but before we have finished saving the FP registers
 157                  * to the thread_struct.  That process could take over the
 158                  * FPU, and then when we get scheduled again we would store
 159                  * bogus values for the remaining FP registers.
 160                  */
 161                 preempt_disable();
 162                 if (tsk->thread.regs->msr & MSR_FP) {
 163                         /*
 164                          * This should only ever be called for current or
 165                          * for a stopped child process.  Since we save away
 166                          * the FP register state on context switch,
 167                          * there is something wrong if a stopped child appears
 168                          * to still have its FP state in the CPU registers.
 169                          */
 170                         BUG_ON(tsk != current);
 171                         giveup_fpu(tsk);
 172                 }
 173                 preempt_enable();
 174         }
 175 }
 176 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 177
 178 void enable_kernel_fp(void)
 179 {
 180         WARN_ON(preemptible());
 181
 182         msr_check_and_set(MSR_FP);
 183
 184         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 185                 check_if_tm_restore_required(current);
 186                 __giveup_fpu(current);
 187         }
 188 }
 189 EXPORT_SYMBOL(enable_kernel_fp);
 190 #endif /* CONFIG_PPC_FPU */
 191
 192 #ifdef CONFIG_ALTIVEC
 193 void giveup_altivec(struct task_struct *tsk)
 194 {
 195         check_if_tm_restore_required(tsk);
 196
 197         msr_check_and_set(MSR_VEC);
 198         __giveup_altivec(tsk);
 199         msr_check_and_clear(MSR_VEC);
 200 }
 201 EXPORT_SYMBOL(giveup_altivec);
 202
 203 void enable_kernel_altivec(void)
 204 {
 205         WARN_ON(preemptible());
 206
 207         msr_check_and_set(MSR_VEC);
 208
 209         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 210                 check_if_tm_restore_required(current);
 211                 __giveup_altivec(current);
 212         }
 213 }
 214 EXPORT_SYMBOL(enable_kernel_altivec);
 215
 216 /*
 217  * Make sure the VMX/Altivec register state in the
 218  * the thread_struct is up to date for task tsk.
 219  */
 220 void flush_altivec_to_thread(struct task_struct *tsk)
 221 {
 222         if (tsk->thread.regs) {
 223                 preempt_disable();
 224                 if (tsk->thread.regs->msr & MSR_VEC) {
 225                         BUG_ON(tsk != current);
 226                         giveup_altivec(tsk);
 227                 }
 228                 preempt_enable();
 229         }
 230 }
 231 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 232 #endif /* CONFIG_ALTIVEC */
 233
 234 #ifdef CONFIG_VSX
 235 void giveup_vsx(struct task_struct *tsk)
 236 {
 237         check_if_tm_restore_required(tsk);
 238
 239         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 240         if (tsk->thread.regs->msr & MSR_FP)
 241                 __giveup_fpu(tsk);
 242         if (tsk->thread.regs->msr & MSR_VEC)
 243                 __giveup_altivec(tsk);
 244         __giveup_vsx(tsk);
 245         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 246 }
 247 EXPORT_SYMBOL(giveup_vsx);
 248
 249 void enable_kernel_vsx(void)
 250 {
 251         WARN_ON(preemptible());
 252
 253         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 254
 255         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 256                 check_if_tm_restore_required(current);
 257                 if (current->thread.regs->msr & MSR_FP)
 258                         __giveup_fpu(current);
 259                 if (current->thread.regs->msr & MSR_VEC)
 260                         __giveup_altivec(current);
 261                 __giveup_vsx(current);
 262         }
 263 }
 264 EXPORT_SYMBOL(enable_kernel_vsx);
 265
 266 void flush_vsx_to_thread(struct task_struct *tsk)
 267 {
 268         if (tsk->thread.regs) {
 269                 preempt_disable();
 270                 if (tsk->thread.regs->msr & MSR_VSX) {
 271                         BUG_ON(tsk != current);
 272                         giveup_vsx(tsk);
 273                 }
 274                 preempt_enable();
 275         }
 276 }
 277 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 278 #endif /* CONFIG_VSX */
 279
 280 #ifdef CONFIG_SPE
 281 void giveup_spe(struct task_struct *tsk)
 282 {
 283         check_if_tm_restore_required(tsk);
 284
 285         msr_check_and_set(MSR_SPE);
 286         __giveup_spe(tsk);
 287         msr_check_and_clear(MSR_SPE);
 288 }
 289 EXPORT_SYMBOL(giveup_spe);
 290
 291 void enable_kernel_spe(void)
 292 {
 293         WARN_ON(preemptible());
 294
 295         msr_check_and_set(MSR_SPE);
 296
 297         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 298                 check_if_tm_restore_required(current);
 299                 __giveup_spe(current);
 300         }
 301 }
 302 EXPORT_SYMBOL(enable_kernel_spe);
 303
 304 void flush_spe_to_thread(struct task_struct *tsk)
 305 {
 306         if (tsk->thread.regs) {
 307                 preempt_disable();
 308                 if (tsk->thread.regs->msr & MSR_SPE) {
 309                         BUG_ON(tsk != current);
 310                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 311                         giveup_spe(tsk);
 312                 }
 313                 preempt_enable();
 314         }
 315 }
 316 #endif /* CONFIG_SPE */
 317
 318 static unsigned long msr_all_available;
 319
 320 static int __init init_msr_all_available(void)
 321 {
 322 #ifdef CONFIG_PPC_FPU
 323         msr_all_available |= MSR_FP;
 324 #endif
 325 #ifdef CONFIG_ALTIVEC
 326         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 327                 msr_all_available |= MSR_VEC;
 328 #endif
 329 #ifdef CONFIG_VSX
 330         if (cpu_has_feature(CPU_FTR_VSX))
 331                 msr_all_available |= MSR_VSX;
 332 #endif
 333 #ifdef CONFIG_SPE
 334         if (cpu_has_feature(CPU_FTR_SPE))
 335                 msr_all_available |= MSR_SPE;
 336 #endif
 337
 338         return 0;
 339 }
 340 early_initcall(init_msr_all_available);
 341
 342 void giveup_all(struct task_struct *tsk)
 343 {
 344         unsigned long usermsr;
 345
 346         if (!tsk->thread.regs)
 347                 return;
 348
 349         usermsr = tsk->thread.regs->msr;
 350
 351         if ((usermsr & msr_all_available) == 0)
 352                 return;
 353
 354         msr_check_and_set(msr_all_available);
 355
 356 #ifdef CONFIG_PPC_FPU
 357         if (usermsr & MSR_FP)
 358                 __giveup_fpu(tsk);
 359 #endif
 360 #ifdef CONFIG_ALTIVEC
 361         if (usermsr & MSR_VEC)
 362                 __giveup_altivec(tsk);
 363 #endif
 364 #ifdef CONFIG_VSX
 365         if (usermsr & MSR_VSX)
 366                 __giveup_vsx(tsk);
 367 #endif
 368 #ifdef CONFIG_SPE
 369         if (usermsr & MSR_SPE)
 370                 __giveup_spe(tsk);
 371 #endif
 372
 373         msr_check_and_clear(msr_all_available);
 374 }
 375 EXPORT_SYMBOL(giveup_all);
 376
 377 void flush_all_to_thread(struct task_struct *tsk)
 378 {
 379         if (tsk->thread.regs) {
 380                 preempt_disable();
 381                 BUG_ON(tsk != current);
 382                 giveup_all(tsk);
 383
 384 #ifdef CONFIG_SPE
 385                 if (tsk->thread.regs->msr & MSR_SPE)
 386                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 387 #endif
 388
 389                 preempt_enable();
 390         }
 391 }
 392 EXPORT_SYMBOL(flush_all_to_thread);
 393
 394 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 395 void do_send_trap(struct pt_regs *regs, unsigned long address,
 396                   unsigned long error_code, int signal_code, int breakpt)
 397 {
 398         siginfo_t info;
 399
 400         current->thread.trap_nr = signal_code;
 401         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 402                         11, SIGSEGV) == NOTIFY_STOP)
 403                 return;
 404
 405         /* Deliver the signal to userspace */
 406         info.si_signo = SIGTRAP;
 407         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 408         info.si_code = signal_code;
 409         info.si_addr = (void __user *)address;
 410         force_sig_info(SIGTRAP, &info, current);
 411 }
 412 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 413 void do_break (struct pt_regs *regs, unsigned long address,
 414                     unsigned long error_code)
 415 {
 416         siginfo_t info;
 417
 418         current->thread.trap_nr = TRAP_HWBKPT;
 419         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 420                         11, SIGSEGV) == NOTIFY_STOP)
 421                 return;
 422
 423         if (debugger_break_match(regs))
 424                 return;
 425
 426         /* Clear the breakpoint */
 427         hw_breakpoint_disable();
 428
 429         /* Deliver the signal to userspace */
 430         info.si_signo = SIGTRAP;
 431         info.si_errno = 0;
 432         info.si_code = TRAP_HWBKPT;
 433         info.si_addr = (void __user *)address;
 434         force_sig_info(SIGTRAP, &info, current);
 435 }
 436 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 437
 438 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 439
 440 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 441 /*
 442  * Set the debug registers back to their default "safe" values.
 443  */
 444 static void set_debug_reg_defaults(struct thread_struct *thread)
 445 {
 446         thread->debug.iac1 = thread->debug.iac2 = 0;
 447 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 448         thread->debug.iac3 = thread->debug.iac4 = 0;
 449 #endif
 450         thread->debug.dac1 = thread->debug.dac2 = 0;
 451 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 452         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 453 #endif
 454         thread->debug.dbcr0 = 0;
 455 #ifdef CONFIG_BOOKE
 456         /*
 457          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 458          */
 459         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 460                         DBCR1_IAC3US | DBCR1_IAC4US;
 461         /*
 462          * Force Data Address Compare User/Supervisor bits to be User-only
 463          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 464          */
 465         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 466 #else
 467         thread->debug.dbcr1 = 0;
 468 #endif
 469 }
 470
 471 static void prime_debug_regs(struct debug_reg *debug)
 472 {
 473         /*
 474          * We could have inherited MSR_DE from userspace, since
 475          * it doesn't get cleared on exception entry.  Make sure
 476          * MSR_DE is clear before we enable any debug events.
 477          */
 478         mtmsr(mfmsr() & ~MSR_DE);
 479
 480         mtspr(SPRN_IAC1, debug->iac1);
 481         mtspr(SPRN_IAC2, debug->iac2);
 482 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 483         mtspr(SPRN_IAC3, debug->iac3);
 484         mtspr(SPRN_IAC4, debug->iac4);
 485 #endif
 486         mtspr(SPRN_DAC1, debug->dac1);
 487         mtspr(SPRN_DAC2, debug->dac2);
 488 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 489         mtspr(SPRN_DVC1, debug->dvc1);
 490         mtspr(SPRN_DVC2, debug->dvc2);
 491 #endif
 492         mtspr(SPRN_DBCR0, debug->dbcr0);
 493         mtspr(SPRN_DBCR1, debug->dbcr1);
 494 #ifdef CONFIG_BOOKE
 495         mtspr(SPRN_DBCR2, debug->dbcr2);
 496 #endif
 497 }
 498 /*
 499  * Unless neither the old or new thread are making use of the
 500  * debug registers, set the debug registers from the values
 501  * stored in the new thread.
 502  */
 503 void switch_booke_debug_regs(struct debug_reg *new_debug)
 504 {
 505         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 506                 || (new_debug->dbcr0 & DBCR0_IDM))
 507                         prime_debug_regs(new_debug);
 508 }
 509 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 510 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 511 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 512 static void set_debug_reg_defaults(struct thread_struct *thread)
 513 {
 514         thread->hw_brk.address = 0;
 515         thread->hw_brk.type = 0;
 516         set_breakpoint(&thread->hw_brk);
 517 }
 518 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 519 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 520
 521 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 522 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 523 {
 524         mtspr(SPRN_DAC1, dabr);
 525 #ifdef CONFIG_PPC_47x
 526         isync();
 527 #endif
 528         return 0;
 529 }
 530 #elif defined(CONFIG_PPC_BOOK3S)
 531 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 532 {
 533         mtspr(SPRN_DABR, dabr);
 534         if (cpu_has_feature(CPU_FTR_DABRX))
 535                 mtspr(SPRN_DABRX, dabrx);
 536         return 0;
 537 }
 538 #else
 539 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 540 {
 541         return -EINVAL;
 542 }
 543 #endif
 544
 545 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 546 {
 547         unsigned long dabr, dabrx;
 548
 549         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 550         dabrx = ((brk->type >> 3) & 0x7);
 551
 552         if (ppc_md.set_dabr)
 553                 return ppc_md.set_dabr(dabr, dabrx);
 554
 555         return __set_dabr(dabr, dabrx);
 556 }
 557
 558 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 559 {
 560         unsigned long dawr, dawrx, mrd;
 561
 562         dawr = brk->address;
 563
 564         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 565                                    << (63 - 58); //* read/write bits */
 566         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 567                                    << (63 - 59); //* translate */
 568         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 569                                    >> 3; //* PRIM bits */
 570         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 571            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 572            0b111111=64DW.
 573            brk->len is in bytes.
 574            This aligns up to double word size, shifts and does the bias.
 575         */
 576         mrd = ((brk->len + 7) >> 3) - 1;
 577         dawrx |= (mrd & 0x3f) << (63 - 53);
 578
 579         if (ppc_md.set_dawr)
 580                 return ppc_md.set_dawr(dawr, dawrx);
 581         mtspr(SPRN_DAWR, dawr);
 582         mtspr(SPRN_DAWRX, dawrx);
 583         return 0;
 584 }
 585
 586 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 587 {
 588         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 589
 590         if (cpu_has_feature(CPU_FTR_DAWR))
 591                 set_dawr(brk);
 592         else
 593                 set_dabr(brk);
 594 }
 595
 596 void set_breakpoint(struct arch_hw_breakpoint *brk)
 597 {
 598         preempt_disable();
 599         __set_breakpoint(brk);
 600         preempt_enable();
 601 }
 602
 603 #ifdef CONFIG_PPC64
 604 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 605 #endif
 606
 607 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 608                               struct arch_hw_breakpoint *b)
 609 {
 610         if (a->address != b->address)
 611                 return false;
 612         if (a->type != b->type)
 613                 return false;
 614         if (a->len != b->len)
 615                 return false;
 616         return true;
 617 }
 618
 619 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 620 static void tm_reclaim_thread(struct thread_struct *thr,
 621                               struct thread_info *ti, uint8_t cause)
 622 {
 623         unsigned long msr_diff = 0;
 624
 625         /*
 626          * If FP/VSX registers have been already saved to the
 627          * thread_struct, move them to the transact_fp array.
 628          * We clear the TIF_RESTORE_TM bit since after the reclaim
 629          * the thread will no longer be transactional.
 630          */
 631         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
 632                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
 633                 if (msr_diff & MSR_FP)
 634                         memcpy(&thr->transact_fp, &thr->fp_state,
 635                                sizeof(struct thread_fp_state));
 636                 if (msr_diff & MSR_VEC)
 637                         memcpy(&thr->transact_vr, &thr->vr_state,
 638                                sizeof(struct thread_vr_state));
 639                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
 640                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
 641         }
 642
 643         tm_reclaim(thr, thr->regs->msr, cause);
 644
 645         /* Having done the reclaim, we now have the checkpointed
 646          * FP/VSX values in the registers.  These might be valid
 647          * even if we have previously called enable_kernel_fp() or
 648          * flush_fp_to_thread(), so update thr->regs->msr to
 649          * indicate their current validity.
 650          */
 651         thr->regs->msr |= msr_diff;
 652 }
 653
 654 void tm_reclaim_current(uint8_t cause)
 655 {
 656         tm_enable();
 657         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 658 }
 659
 660 static inline void tm_reclaim_task(struct task_struct *tsk)
 661 {
 662         /* We have to work out if we're switching from/to a task that's in the
 663          * middle of a transaction.
 664          *
 665          * In switching we need to maintain a 2nd register state as
 666          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 667          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
 668          * (current) FPRs into oldtask->thread.transact_fpr[].
 669          *
 670          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 671          */
 672         struct thread_struct *thr = &tsk->thread;
 673
 674         if (!thr->regs)
 675                 return;
 676
 677         if (!MSR_TM_ACTIVE(thr->regs->msr))
 678                 goto out_and_saveregs;
 679
 680         /* Stash the original thread MSR, as giveup_fpu et al will
 681          * modify it.  We hold onto it to see whether the task used
 682          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
 683          * ckpt_regs.msr is already set.
 684          */
 685         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
 686                 thr->ckpt_regs.msr = thr->regs->msr;
 687
 688         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 689                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 690                  tsk->pid, thr->regs->nip,
 691                  thr->regs->ccr, thr->regs->msr,
 692                  thr->regs->trap);
 693
 694         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 695
 696         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 697                  tsk->pid);
 698
 699 out_and_saveregs:
 700         /* Always save the regs here, even if a transaction's not active.
 701          * This context-switches a thread's TM info SPRs.  We do it here to
 702          * be consistent with the restore path (in recheckpoint) which
 703          * cannot happen later in _switch().
 704          */
 705         tm_save_sprs(thr);
 706 }
 707
 708 extern void __tm_recheckpoint(struct thread_struct *thread,
 709                               unsigned long orig_msr);
 710
 711 void tm_recheckpoint(struct thread_struct *thread,
 712                      unsigned long orig_msr)
 713 {
 714         unsigned long flags;
 715
 716         /* We really can't be interrupted here as the TEXASR registers can't
 717          * change and later in the trecheckpoint code, we have a userspace R1.
 718          * So let's hard disable over this region.
 719          */
 720         local_irq_save(flags);
 721         hard_irq_disable();
 722
 723         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 724          * before the trecheckpoint and no explosion occurs.
 725          */
 726         tm_restore_sprs(thread);
 727
 728         __tm_recheckpoint(thread, orig_msr);
 729
 730         local_irq_restore(flags);
 731 }
 732
 733 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 734 {
 735         unsigned long msr;
 736
 737         if (!cpu_has_feature(CPU_FTR_TM))
 738                 return;
 739
 740         /* Recheckpoint the registers of the thread we're about to switch to.
 741          *
 742          * If the task was using FP, we non-lazily reload both the original and
 743          * the speculative FP register states.  This is because the kernel
 744          * doesn't see if/when a TM rollback occurs, so if we take an FP
 745          * unavoidable later, we are unable to determine which set of FP regs
 746          * need to be restored.
 747          */
 748         if (!new->thread.regs)
 749                 return;
 750
 751         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 752                 tm_restore_sprs(&new->thread);
 753                 return;
 754         }
 755         msr = new->thread.ckpt_regs.msr;
 756         /* Recheckpoint to restore original checkpointed register state. */
 757         TM_DEBUG("*** tm_recheckpoint of pid %d "
 758                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 759                  new->pid, new->thread.regs->msr, msr);
 760
 761         /* This loads the checkpointed FP/VEC state, if used */
 762         tm_recheckpoint(&new->thread, msr);
 763
 764         /* This loads the speculative FP/VEC state, if used */
 765         if (msr & MSR_FP) {
 766                 do_load_up_transact_fpu(&new->thread);
 767                 new->thread.regs->msr |=
 768                         (MSR_FP | new->thread.fpexc_mode);
 769         }
 770 #ifdef CONFIG_ALTIVEC
 771         if (msr & MSR_VEC) {
 772                 do_load_up_transact_altivec(&new->thread);
 773                 new->thread.regs->msr |= MSR_VEC;
 774         }
 775 #endif
 776         /* We may as well turn on VSX too since all the state is restored now */
 777         if (msr & MSR_VSX)
 778                 new->thread.regs->msr |= MSR_VSX;
 779
 780         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 781                  "(kernel msr 0x%lx)\n",
 782                  new->pid, mfmsr());
 783 }
 784
 785 static inline void __switch_to_tm(struct task_struct *prev)
 786 {
 787         if (cpu_has_feature(CPU_FTR_TM)) {
 788                 tm_enable();
 789                 tm_reclaim_task(prev);
 790         }
 791 }
 792
 793 /*
 794  * This is called if we are on the way out to userspace and the
 795  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 796  * FP and/or vector state and does so if necessary.
 797  * If userspace is inside a transaction (whether active or
 798  * suspended) and FP/VMX/VSX instructions have ever been enabled
 799  * inside that transaction, then we have to keep them enabled
 800  * and keep the FP/VMX/VSX state loaded while ever the transaction
 801  * continues.  The reason is that if we didn't, and subsequently
 802  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 803  * we don't know whether it's the same transaction, and thus we
 804  * don't know which of the checkpointed state and the transactional
 805  * state to use.
 806  */
 807 void restore_tm_state(struct pt_regs *regs)
 808 {
 809         unsigned long msr_diff;
 810
 811         clear_thread_flag(TIF_RESTORE_TM);
 812         if (!MSR_TM_ACTIVE(regs->msr))
 813                 return;
 814
 815         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
 816         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
 817         if (msr_diff & MSR_FP) {
 818                 msr_check_and_set(MSR_FP);
 819                 load_fp_state(&current->thread.fp_state);
 820                 msr_check_and_clear(MSR_FP);
 821                 regs->msr |= current->thread.fpexc_mode;
 822         }
 823         if (msr_diff & MSR_VEC) {
 824                 msr_check_and_set(MSR_VEC);
 825                 load_vr_state(&current->thread.vr_state);
 826                 msr_check_and_clear(MSR_VEC);
 827         }
 828         regs->msr |= msr_diff;
 829 }
 830
 831 #else
 832 #define tm_recheckpoint_new_task(new)
 833 #define __switch_to_tm(prev)
 834 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 835
 836 static inline void save_sprs(struct thread_struct *t)
 837 {
 838 #ifdef CONFIG_ALTIVEC
 839         if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
 840                 t->vrsave = mfspr(SPRN_VRSAVE);
 841 #endif
 842 #ifdef CONFIG_PPC_BOOK3S_64
 843         if (cpu_has_feature(CPU_FTR_DSCR))
 844                 t->dscr = mfspr(SPRN_DSCR);
 845
 846         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
 847                 t->bescr = mfspr(SPRN_BESCR);
 848                 t->ebbhr = mfspr(SPRN_EBBHR);
 849                 t->ebbrr = mfspr(SPRN_EBBRR);
 850
 851                 t->fscr = mfspr(SPRN_FSCR);
 852
 853                 /*
 854                  * Note that the TAR is not available for use in the kernel.
 855                  * (To provide this, the TAR should be backed up/restored on
 856                  * exception entry/exit instead, and be in pt_regs.  FIXME,
 857                  * this should be in pt_regs anyway (for debug).)
 858                  */
 859                 t->tar = mfspr(SPRN_TAR);
 860         }
 861 #endif
 862 }
 863
 864 static inline void restore_sprs(struct thread_struct *old_thread,
 865                                 struct thread_struct *new_thread)
 866 {
 867 #ifdef CONFIG_ALTIVEC
 868         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 869             old_thread->vrsave != new_thread->vrsave)
 870                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
 871 #endif
 872 #ifdef CONFIG_PPC_BOOK3S_64
 873         if (cpu_has_feature(CPU_FTR_DSCR)) {
 874                 u64 dscr = get_paca()->dscr_default;
 875                 u64 fscr = old_thread->fscr & ~FSCR_DSCR;
 876
 877                 if (new_thread->dscr_inherit) {
 878                         dscr = new_thread->dscr;
 879                         fscr |= FSCR_DSCR;
 880                 }
 881
 882                 if (old_thread->dscr != dscr)
 883                         mtspr(SPRN_DSCR, dscr);
 884
 885                 if (old_thread->fscr != fscr)
 886                         mtspr(SPRN_FSCR, fscr);
 887         }
 888
 889         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
 890                 if (old_thread->bescr != new_thread->bescr)
 891                         mtspr(SPRN_BESCR, new_thread->bescr);
 892                 if (old_thread->ebbhr != new_thread->ebbhr)
 893                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
 894                 if (old_thread->ebbrr != new_thread->ebbrr)
 895                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
 896
 897                 if (old_thread->tar != new_thread->tar)
 898                         mtspr(SPRN_TAR, new_thread->tar);
 899         }
 900 #endif
 901 }
 902
 903 struct task_struct *__switch_to(struct task_struct *prev,
 904         struct task_struct *new)
 905 {
 906         struct thread_struct *new_thread, *old_thread;
 907         struct task_struct *last;
 908 #ifdef CONFIG_PPC_BOOK3S_64
 909         struct ppc64_tlb_batch *batch;
 910 #endif
 911
 912         new_thread = &new->thread;
 913         old_thread = &current->thread;
 914
 915         WARN_ON(!irqs_disabled());
 916
 917 #ifdef CONFIG_PPC64
 918         /*
 919          * Collect processor utilization data per process
 920          */
 921         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
 922                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
 923                 long unsigned start_tb, current_tb;
 924                 start_tb = old_thread->start_tb;
 925                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
 926                 old_thread->accum_tb += (current_tb - start_tb);
 927                 new_thread->start_tb = current_tb;
 928         }
 929 #endif /* CONFIG_PPC64 */
 930
 931 #ifdef CONFIG_PPC_BOOK3S_64
 932         batch = this_cpu_ptr(&ppc64_tlb_batch);
 933         if (batch->active) {
 934                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
 935                 if (batch->index)
 936                         __flush_tlb_pending(batch);
 937                 batch->active = 0;
 938         }
 939 #endif /* CONFIG_PPC_BOOK3S_64 */
 940
 941 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 942         switch_booke_debug_regs(&new->thread.debug);
 943 #else
 944 /*
 945  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
 946  * schedule DABR
 947  */
 948 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 949         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
 950                 __set_breakpoint(&new->thread.hw_brk);
 951 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 952 #endif
 953
 954         /*
 955          * We need to save SPRs before treclaim/trecheckpoint as these will
 956          * change a number of them.
 957          */
 958         save_sprs(&prev->thread);
 959
 960         __switch_to_tm(prev);
 961
 962         /* Save FPU, Altivec, VSX and SPE state */
 963         giveup_all(prev);
 964
 965         /*
 966          * We can't take a PMU exception inside _switch() since there is a
 967          * window where the kernel stack SLB and the kernel stack are out
 968          * of sync. Hard disable here.
 969          */
 970         hard_irq_disable();
 971
 972         tm_recheckpoint_new_task(new);
 973
 974         /*
 975          * Call restore_sprs() before calling _switch(). If we move it after
 976          * _switch() then we miss out on calling it for new tasks. The reason
 977          * for this is we manually create a stack frame for new tasks that
 978          * directly returns through ret_from_fork() or
 979          * ret_from_kernel_thread(). See copy_thread() for details.
 980          */
 981         restore_sprs(old_thread, new_thread);
 982
 983         last = _switch(old_thread, new_thread);
 984
 985 #ifdef CONFIG_PPC_BOOK3S_64
 986         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
 987                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
 988                 batch = this_cpu_ptr(&ppc64_tlb_batch);
 989                 batch->active = 1;
 990         }
 991 #endif /* CONFIG_PPC_BOOK3S_64 */
 992
 993         return last;
 994 }
 995
 996 static int instructions_to_print = 16;
 997
 998 static void show_instructions(struct pt_regs *regs)
 999 {
1000         int i;
1001         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1002                         sizeof(int));
1003
1004         printk("Instruction dump:");
1005
1006         for (i = 0; i < instructions_to_print; i++) {
1007                 int instr;
1008
1009                 if (!(i % 8))
1010                         printk("\n");
1011
1012 #if !defined(CONFIG_BOOKE)
1013                 /* If executing with the IMMU off, adjust pc rather
1014                  * than print XXXXXXXX.
1015                  */
1016                 if (!(regs->msr & MSR_IR))
1017                         pc = (unsigned long)phys_to_virt(pc);
1018 #endif
1019
1020                 if (!__kernel_text_address(pc) ||
1021                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1022                         printk(KERN_CONT "XXXXXXXX ");
1023                 } else {
1024                         if (regs->nip == pc)
1025                                 printk(KERN_CONT "<%08x> ", instr);
1026                         else
1027                                 printk(KERN_CONT "%08x ", instr);
1028                 }
1029
1030                 pc += sizeof(int);
1031         }
1032
1033         printk("\n");
1034 }
1035
1036 struct regbit {
1037         unsigned long bit;
1038         const char *name;
1039 };
1040
1041 static struct regbit msr_bits[] = {
1042 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1043         {MSR_SF,        "SF"},
1044         {MSR_HV,        "HV"},
1045 #endif
1046         {MSR_VEC,       "VEC"},
1047         {MSR_VSX,       "VSX"},
1048 #ifdef CONFIG_BOOKE
1049         {MSR_CE,        "CE"},
1050 #endif
1051         {MSR_EE,        "EE"},
1052         {MSR_PR,        "PR"},
1053         {MSR_FP,        "FP"},
1054         {MSR_ME,        "ME"},
1055 #ifdef CONFIG_BOOKE
1056         {MSR_DE,        "DE"},
1057 #else
1058         {MSR_SE,        "SE"},
1059         {MSR_BE,        "BE"},
1060 #endif
1061         {MSR_IR,        "IR"},
1062         {MSR_DR,        "DR"},
1063         {MSR_PMM,       "PMM"},
1064 #ifndef CONFIG_BOOKE
1065         {MSR_RI,        "RI"},
1066         {MSR_LE,        "LE"},
1067 #endif
1068         {0,             NULL}
1069 };
1070
1071 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1072 {
1073         const char *s = "";
1074
1075         for (; bits->bit; ++bits)
1076                 if (val & bits->bit) {
1077                         printk("%s%s", s, bits->name);
1078                         s = sep;
1079                 }
1080 }
1081
1082 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1083 static struct regbit msr_tm_bits[] = {
1084         {MSR_TS_T,      "T"},
1085         {MSR_TS_S,      "S"},
1086         {MSR_TM,        "E"},
1087         {0,             NULL}
1088 };
1089
1090 static void print_tm_bits(unsigned long val)
1091 {
1092 /*
1093  * This only prints something if at least one of the TM bit is set.
1094  * Inside the TM[], the output means:
1095  *   E: Enabled         (bit 32)
1096  *   S: Suspended       (bit 33)
1097  *   T: Transactional   (bit 34)
1098  */
1099         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1100                 printk(",TM[");
1101                 print_bits(val, msr_tm_bits, "");
1102                 printk("]");
1103         }
1104 }
1105 #else
1106 static void print_tm_bits(unsigned long val) {}
1107 #endif
1108
1109 static void print_msr_bits(unsigned long val)
1110 {
1111         printk("<");
1112         print_bits(val, msr_bits, ",");
1113         print_tm_bits(val);
1114         printk(">");
1115 }
1116
1117 #ifdef CONFIG_PPC64
1118 #define REG             "%016lx"
1119 #define REGS_PER_LINE   4
1120 #define LAST_VOLATILE   13
1121 #else
1122 #define REG             "%08lx"
1123 #define REGS_PER_LINE   8
1124 #define LAST_VOLATILE   12
1125 #endif
1126
1127 void show_regs(struct pt_regs * regs)
1128 {
1129         int i, trap;
1130
1131         show_regs_print_info(KERN_DEFAULT);
1132
1133         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1134                regs->nip, regs->link, regs->ctr);
1135         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1136                regs, regs->trap, print_tainted(), init_utsname()->release);
1137         printk("MSR: "REG" ", regs->msr);
1138         print_msr_bits(regs->msr);
1139         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1140         trap = TRAP(regs);
1141         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1142                 printk("CFAR: "REG" ", regs->orig_gpr3);
1143         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1144 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1145                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1146 #else
1147                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1148 #endif
1149 #ifdef CONFIG_PPC64
1150         printk("SOFTE: %ld ", regs->softe);
1151 #endif
1152 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1153         if (MSR_TM_ACTIVE(regs->msr))
1154                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1155 #endif
1156
1157         for (i = 0;  i < 32;  i++) {
1158                 if ((i % REGS_PER_LINE) == 0)
1159                         printk("\nGPR%02d: ", i);
1160                 printk(REG " ", regs->gpr[i]);
1161                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1162                         break;
1163         }
1164         printk("\n");
1165 #ifdef CONFIG_KALLSYMS
1166         /*
1167          * Lookup NIP late so we have the best change of getting the
1168          * above info out without failing
1169          */
1170         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1171         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1172 #endif
1173         show_stack(current, (unsigned long *) regs->gpr[1]);
1174         if (!user_mode(regs))
1175                 show_instructions(regs);
1176 }
1177
1178 void exit_thread(void)
1179 {
1180 }
1181
1182 void flush_thread(void)
1183 {
1184 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1185         flush_ptrace_hw_breakpoint(current);
1186 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1187         set_debug_reg_defaults(&current->thread);
1188 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1189 }
1190
1191 void
1192 release_thread(struct task_struct *t)
1193 {
1194 }
1195
1196 /*
1197  * this gets called so that we can store coprocessor state into memory and
1198  * copy the current task into the new thread.
1199  */
1200 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1201 {
1202         flush_all_to_thread(src);
1203         /*
1204          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1205          * flush but it removes the checkpointed state from the current CPU and
1206          * transitions the CPU out of TM mode.  Hence we need to call
1207          * tm_recheckpoint_new_task() (on the same task) to restore the
1208          * checkpointed state back and the TM mode.
1209          */
1210         __switch_to_tm(src);
1211         tm_recheckpoint_new_task(src);
1212
1213         *dst = *src;
1214
1215         clear_task_ebb(dst);
1216
1217         return 0;
1218 }
1219
1220 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1221 {
1222 #ifdef CONFIG_PPC_STD_MMU_64
1223         unsigned long sp_vsid;
1224         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1225
1226         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1227                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1228                         << SLB_VSID_SHIFT_1T;
1229         else
1230                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1231                         << SLB_VSID_SHIFT;
1232         sp_vsid |= SLB_VSID_KERNEL | llp;
1233         p->thread.ksp_vsid = sp_vsid;
1234 #endif
1235 }
1236
1237 /*
1238  * Copy a thread..
1239  */
1240
1241 /*
1242  * Copy architecture-specific thread state
1243  */
1244 int copy_thread(unsigned long clone_flags, unsigned long usp,
1245                 unsigned long kthread_arg, struct task_struct *p)
1246 {
1247         struct pt_regs *childregs, *kregs;
1248         extern void ret_from_fork(void);
1249         extern void ret_from_kernel_thread(void);
1250         void (*f)(void);
1251         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1252
1253         /* Copy registers */
1254         sp -= sizeof(struct pt_regs);
1255         childregs = (struct pt_regs *) sp;
1256         if (unlikely(p->flags & PF_KTHREAD)) {
1257                 /* kernel thread */
1258                 struct thread_info *ti = (void *)task_stack_page(p);
1259                 memset(childregs, 0, sizeof(struct pt_regs));
1260                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1261                 /* function */
1262                 if (usp)
1263                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1264 #ifdef CONFIG_PPC64
1265                 clear_tsk_thread_flag(p, TIF_32BIT);
1266                 childregs->softe = 1;
1267 #endif
1268                 childregs->gpr[15] = kthread_arg;
1269                 p->thread.regs = NULL;  /* no user register state */
1270                 ti->flags |= _TIF_RESTOREALL;
1271                 f = ret_from_kernel_thread;
1272         } else {
1273                 /* user thread */
1274                 struct pt_regs *regs = current_pt_regs();
1275                 CHECK_FULL_REGS(regs);
1276                 *childregs = *regs;
1277                 if (usp)
1278                         childregs->gpr[1] = usp;
1279                 p->thread.regs = childregs;
1280                 childregs->gpr[3] = 0;  /* Result from fork() */
1281                 if (clone_flags & CLONE_SETTLS) {
1282 #ifdef CONFIG_PPC64
1283                         if (!is_32bit_task())
1284                                 childregs->gpr[13] = childregs->gpr[6];
1285                         else
1286 #endif
1287                                 childregs->gpr[2] = childregs->gpr[6];
1288                 }
1289
1290                 f = ret_from_fork;
1291         }
1292         sp -= STACK_FRAME_OVERHEAD;
1293
1294         /*
1295          * The way this works is that at some point in the future
1296          * some task will call _switch to switch to the new task.
1297          * That will pop off the stack frame created below and start
1298          * the new task running at ret_from_fork.  The new task will
1299          * do some house keeping and then return from the fork or clone
1300          * system call, using the stack frame created above.
1301          */
1302         ((unsigned long *)sp)[0] = 0;
1303         sp -= sizeof(struct pt_regs);
1304         kregs = (struct pt_regs *) sp;
1305         sp -= STACK_FRAME_OVERHEAD;
1306         p->thread.ksp = sp;
1307 #ifdef CONFIG_PPC32
1308         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1309                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1310 #endif
1311 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1312         p->thread.ptrace_bps[0] = NULL;
1313 #endif
1314
1315         p->thread.fp_save_area = NULL;
1316 #ifdef CONFIG_ALTIVEC
1317         p->thread.vr_save_area = NULL;
1318 #endif
1319
1320         setup_ksp_vsid(p, sp);
1321
1322 #ifdef CONFIG_PPC64
1323         if (cpu_has_feature(CPU_FTR_DSCR)) {
1324                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1325                 p->thread.dscr = mfspr(SPRN_DSCR);
1326         }
1327         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1328                 p->thread.ppr = INIT_PPR;
1329 #endif
1330         kregs->nip = ppc_function_entry(f);
1331         return 0;
1332 }
1333
1334 /*
1335  * Set up a thread for executing a new program
1336  */
1337 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1338 {
1339 #ifdef CONFIG_PPC64
1340         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1341 #endif
1342
1343         /*
1344          * If we exec out of a kernel thread then thread.regs will not be
1345          * set.  Do it now.
1346          */
1347         if (!current->thread.regs) {
1348                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1349                 current->thread.regs = regs - 1;
1350         }
1351
1352         memset(regs->gpr, 0, sizeof(regs->gpr));
1353         regs->ctr = 0;
1354         regs->link = 0;
1355         regs->xer = 0;
1356         regs->ccr = 0;
1357         regs->gpr[1] = sp;
1358
1359         /*
1360          * We have just cleared all the nonvolatile GPRs, so make
1361          * FULL_REGS(regs) return true.  This is necessary to allow
1362          * ptrace to examine the thread immediately after exec.
1363          */
1364         regs->trap &= ~1UL;
1365
1366 #ifdef CONFIG_PPC32
1367         regs->mq = 0;
1368         regs->nip = start;
1369         regs->msr = MSR_USER;
1370 #else
1371         if (!is_32bit_task()) {
1372                 unsigned long entry;
1373
1374                 if (is_elf2_task()) {
1375                         /* Look ma, no function descriptors! */
1376                         entry = start;
1377
1378                         /*
1379                          * Ulrich says:
1380                          *   The latest iteration of the ABI requires that when
1381                          *   calling a function (at its global entry point),
1382                          *   the caller must ensure r12 holds the entry point
1383                          *   address (so that the function can quickly
1384                          *   establish addressability).
1385                          */
1386                         regs->gpr[12] = start;
1387                         /* Make sure that's restored on entry to userspace. */
1388                         set_thread_flag(TIF_RESTOREALL);
1389                 } else {
1390                         unsigned long toc;
1391
1392                         /* start is a relocated pointer to the function
1393                          * descriptor for the elf _start routine.  The first
1394                          * entry in the function descriptor is the entry
1395                          * address of _start and the second entry is the TOC
1396                          * value we need to use.
1397                          */
1398                         __get_user(entry, (unsigned long __user *)start);
1399                         __get_user(toc, (unsigned long __user *)start+1);
1400
1401                         /* Check whether the e_entry function descriptor entries
1402                          * need to be relocated before we can use them.
1403                          */
1404                         if (load_addr != 0) {
1405                                 entry += load_addr;
1406                                 toc   += load_addr;
1407                         }
1408                         regs->gpr[2] = toc;
1409                 }
1410                 regs->nip = entry;
1411                 regs->msr = MSR_USER64;
1412         } else {
1413                 regs->nip = start;
1414                 regs->gpr[2] = 0;
1415                 regs->msr = MSR_USER32;
1416         }
1417 #endif
1418 #ifdef CONFIG_VSX
1419         current->thread.used_vsr = 0;
1420 #endif
1421         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1422         current->thread.fp_save_area = NULL;
1423 #ifdef CONFIG_ALTIVEC
1424         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1425         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1426         current->thread.vr_save_area = NULL;
1427         current->thread.vrsave = 0;
1428         current->thread.used_vr = 0;
1429 #endif /* CONFIG_ALTIVEC */
1430 #ifdef CONFIG_SPE
1431         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1432         current->thread.acc = 0;
1433         current->thread.spefscr = 0;
1434         current->thread.used_spe = 0;
1435 #endif /* CONFIG_SPE */
1436 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1437         if (cpu_has_feature(CPU_FTR_TM))
1438                 regs->msr |= MSR_TM;
1439         current->thread.tm_tfhar = 0;
1440         current->thread.tm_texasr = 0;
1441         current->thread.tm_tfiar = 0;
1442 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1443 }
1444 EXPORT_SYMBOL(start_thread);
1445
1446 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1447                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1448
1449 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1450 {
1451         struct pt_regs *regs = tsk->thread.regs;
1452
1453         /* This is a bit hairy.  If we are an SPE enabled  processor
1454          * (have embedded fp) we store the IEEE exception enable flags in
1455          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1456          * mode (asyn, precise, disabled) for 'Classic' FP. */
1457         if (val & PR_FP_EXC_SW_ENABLE) {
1458 #ifdef CONFIG_SPE
1459                 if (cpu_has_feature(CPU_FTR_SPE)) {
1460                         /*
1461                          * When the sticky exception bits are set
1462                          * directly by userspace, it must call prctl
1463                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1464                          * in the existing prctl settings) or
1465                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1466                          * the bits being set).  <fenv.h> functions
1467                          * saving and restoring the whole
1468                          * floating-point environment need to do so
1469                          * anyway to restore the prctl settings from
1470                          * the saved environment.
1471                          */
1472                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1473                         tsk->thread.fpexc_mode = val &
1474                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1475                         return 0;
1476                 } else {
1477                         return -EINVAL;
1478                 }
1479 #else
1480                 return -EINVAL;
1481 #endif
1482         }
1483
1484         /* on a CONFIG_SPE this does not hurt us.  The bits that
1485          * __pack_fe01 use do not overlap with bits used for
1486          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1487          * on CONFIG_SPE implementations are reserved so writing to
1488          * them does not change anything */
1489         if (val > PR_FP_EXC_PRECISE)
1490                 return -EINVAL;
1491         tsk->thread.fpexc_mode = __pack_fe01(val);
1492         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1493                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1494                         | tsk->thread.fpexc_mode;
1495         return 0;
1496 }
1497
1498 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1499 {
1500         unsigned int val;
1501
1502         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1503 #ifdef CONFIG_SPE
1504                 if (cpu_has_feature(CPU_FTR_SPE)) {
1505                         /*
1506                          * When the sticky exception bits are set
1507                          * directly by userspace, it must call prctl
1508                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1509                          * in the existing prctl settings) or
1510                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1511                          * the bits being set).  <fenv.h> functions
1512                          * saving and restoring the whole
1513                          * floating-point environment need to do so
1514                          * anyway to restore the prctl settings from
1515                          * the saved environment.
1516                          */
1517                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1518                         val = tsk->thread.fpexc_mode;
1519                 } else
1520                         return -EINVAL;
1521 #else
1522                 return -EINVAL;
1523 #endif
1524         else
1525                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1526         return put_user(val, (unsigned int __user *) adr);
1527 }
1528
1529 int set_endian(struct task_struct *tsk, unsigned int val)
1530 {
1531         struct pt_regs *regs = tsk->thread.regs;
1532
1533         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1534             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1535                 return -EINVAL;
1536
1537         if (regs == NULL)
1538                 return -EINVAL;
1539
1540         if (val == PR_ENDIAN_BIG)
1541                 regs->msr &= ~MSR_LE;
1542         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1543                 regs->msr |= MSR_LE;
1544         else
1545                 return -EINVAL;
1546
1547         return 0;
1548 }
1549
1550 int get_endian(struct task_struct *tsk, unsigned long adr)
1551 {
1552         struct pt_regs *regs = tsk->thread.regs;
1553         unsigned int val;
1554
1555         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1556             !cpu_has_feature(CPU_FTR_REAL_LE))
1557                 return -EINVAL;
1558
1559         if (regs == NULL)
1560                 return -EINVAL;
1561
1562         if (regs->msr & MSR_LE) {
1563                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1564                         val = PR_ENDIAN_LITTLE;
1565                 else
1566                         val = PR_ENDIAN_PPC_LITTLE;
1567         } else
1568                 val = PR_ENDIAN_BIG;
1569
1570         return put_user(val, (unsigned int __user *)adr);
1571 }
1572
1573 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1574 {
1575         tsk->thread.align_ctl = val;
1576         return 0;
1577 }
1578
1579 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1580 {
1581         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1582 }
1583
1584 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1585                                   unsigned long nbytes)
1586 {
1587         unsigned long stack_page;
1588         unsigned long cpu = task_cpu(p);
1589
1590         /*
1591          * Avoid crashing if the stack has overflowed and corrupted
1592          * task_cpu(p), which is in the thread_info struct.
1593          */
1594         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1595                 stack_page = (unsigned long) hardirq_ctx[cpu];
1596                 if (sp >= stack_page + sizeof(struct thread_struct)
1597                     && sp <= stack_page + THREAD_SIZE - nbytes)
1598                         return 1;
1599
1600                 stack_page = (unsigned long) softirq_ctx[cpu];
1601                 if (sp >= stack_page + sizeof(struct thread_struct)
1602                     && sp <= stack_page + THREAD_SIZE - nbytes)
1603                         return 1;
1604         }
1605         return 0;
1606 }
1607
1608 int validate_sp(unsigned long sp, struct task_struct *p,
1609                        unsigned long nbytes)
1610 {
1611         unsigned long stack_page = (unsigned long)task_stack_page(p);
1612
1613         if (sp >= stack_page + sizeof(struct thread_struct)
1614             && sp <= stack_page + THREAD_SIZE - nbytes)
1615                 return 1;
1616
1617         return valid_irq_stack(sp, p, nbytes);
1618 }
1619
1620 EXPORT_SYMBOL(validate_sp);
1621
1622 unsigned long get_wchan(struct task_struct *p)
1623 {
1624         unsigned long ip, sp;
1625         int count = 0;
1626
1627         if (!p || p == current || p->state == TASK_RUNNING)
1628                 return 0;
1629
1630         sp = p->thread.ksp;
1631         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1632                 return 0;
1633
1634         do {
1635                 sp = *(unsigned long *)sp;
1636                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1637                         return 0;
1638                 if (count > 0) {
1639                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1640                         if (!in_sched_functions(ip))
1641                                 return ip;
1642                 }
1643         } while (count++ < 16);
1644         return 0;
1645 }
1646
1647 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1648
1649 void show_stack(struct task_struct *tsk, unsigned long *stack)
1650 {
1651         unsigned long sp, ip, lr, newsp;
1652         int count = 0;
1653         int firstframe = 1;
1654 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1655         int curr_frame = current->curr_ret_stack;
1656         extern void return_to_handler(void);
1657         unsigned long rth = (unsigned long)return_to_handler;
1658 #endif
1659
1660         sp = (unsigned long) stack;
1661         if (tsk == NULL)
1662                 tsk = current;
1663         if (sp == 0) {
1664                 if (tsk == current)
1665                         sp = current_stack_pointer();
1666                 else
1667                         sp = tsk->thread.ksp;
1668         }
1669
1670         lr = 0;
1671         printk("Call Trace:\n");
1672         do {
1673                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1674                         return;
1675
1676                 stack = (unsigned long *) sp;
1677                 newsp = stack[0];
1678                 ip = stack[STACK_FRAME_LR_SAVE];
1679                 if (!firstframe || ip != lr) {
1680                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1681 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1682                         if ((ip == rth) && curr_frame >= 0) {
1683                                 printk(" (%pS)",
1684                                        (void *)current->ret_stack[curr_frame].ret);
1685                                 curr_frame--;
1686                         }
1687 #endif
1688                         if (firstframe)
1689                                 printk(" (unreliable)");
1690                         printk("\n");
1691                 }
1692                 firstframe = 0;
1693
1694                 /*
1695                  * See if this is an exception frame.
1696                  * We look for the "regshere" marker in the current frame.
1697                  */
1698                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1699                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1700                         struct pt_regs *regs = (struct pt_regs *)
1701                                 (sp + STACK_FRAME_OVERHEAD);
1702                         lr = regs->link;
1703                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1704                                regs->trap, (void *)regs->nip, (void *)lr);
1705                         firstframe = 1;
1706                 }
1707
1708                 sp = newsp;
1709         } while (count++ < kstack_depth_to_print);
1710 }
1711
1712 #ifdef CONFIG_PPC64
1713 /* Called with hard IRQs off */
1714 void notrace __ppc64_runlatch_on(void)
1715 {
1716         struct thread_info *ti = current_thread_info();
1717         unsigned long ctrl;
1718
1719         ctrl = mfspr(SPRN_CTRLF);
1720         ctrl |= CTRL_RUNLATCH;
1721         mtspr(SPRN_CTRLT, ctrl);
1722
1723         ti->local_flags |= _TLF_RUNLATCH;
1724 }
1725
1726 /* Called with hard IRQs off */
1727 void notrace __ppc64_runlatch_off(void)
1728 {
1729         struct thread_info *ti = current_thread_info();
1730         unsigned long ctrl;
1731
1732         ti->local_flags &= ~_TLF_RUNLATCH;
1733
1734         ctrl = mfspr(SPRN_CTRLF);
1735         ctrl &= ~CTRL_RUNLATCH;
1736         mtspr(SPRN_CTRLT, ctrl);
1737 }
1738 #endif /* CONFIG_PPC64 */
1739
1740 unsigned long arch_align_stack(unsigned long sp)
1741 {
1742         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1743                 sp -= get_random_int() & ~PAGE_MASK;
1744         return sp & ~0xf;
1745 }
1746
1747 static inline unsigned long brk_rnd(void)
1748 {
1749         unsigned long rnd = 0;
1750
1751         /* 8MB for 32bit, 1GB for 64bit */
1752         if (is_32bit_task())
1753                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1754         else
1755                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1756
1757         return rnd << PAGE_SHIFT;
1758 }
1759
1760 unsigned long arch_randomize_brk(struct mm_struct *mm)
1761 {
1762         unsigned long base = mm->brk;
1763         unsigned long ret;
1764
1765 #ifdef CONFIG_PPC_STD_MMU_64
1766         /*
1767          * If we are using 1TB segments and we are allowed to randomise
1768          * the heap, we can put it above 1TB so it is backed by a 1TB
1769          * segment. Otherwise the heap will be in the bottom 1TB
1770          * which always uses 256MB segments and this may result in a
1771          * performance penalty.
1772          */
1773         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1774                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1775 #endif
1776
1777         ret = PAGE_ALIGN(base + brk_rnd());
1778
1779         if (ret < mm->brk)
1780                 return mm->brk;
1781
1782         return ret;
1783 }
1784