arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61 #include <asm/cpu_has_feature.h>
  62 #include <asm/asm-prototypes.h>
  63
  64 #include <linux/kprobes.h>
  65 #include <linux/kdebug.h>
  66
  67 /* Transactional Memory debug */
  68 #ifdef TM_DEBUG_SW
  69 #define TM_DEBUG(x...) printk(KERN_INFO x)
  70 #else
  71 #define TM_DEBUG(x...) do { } while(0)
  72 #endif
  73
  74 extern unsigned long _get_SP(void);
  75
  76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  77 static void check_if_tm_restore_required(struct task_struct *tsk)
  78 {
  79         /*
  80          * If we are saving the current thread's registers, and the
  81          * thread is in a transactional state, set the TIF_RESTORE_TM
  82          * bit so that we know to restore the registers before
  83          * returning to userspace.
  84          */
  85         if (tsk == current && tsk->thread.regs &&
  86             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  87             !test_thread_flag(TIF_RESTORE_TM)) {
  88                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  89                 set_thread_flag(TIF_RESTORE_TM);
  90         }
  91 }
  92
  93 static inline bool msr_tm_active(unsigned long msr)
  94 {
  95         return MSR_TM_ACTIVE(msr);
  96 }
  97 #else
  98 static inline bool msr_tm_active(unsigned long msr) { return false; }
  99 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 100 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 101
 102 bool strict_msr_control;
 103 EXPORT_SYMBOL(strict_msr_control);
 104
 105 static int __init enable_strict_msr_control(char *str)
 106 {
 107         strict_msr_control = true;
 108         pr_info("Enabling strict facility control\n");
 109
 110         return 0;
 111 }
 112 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 113
 114 unsigned long msr_check_and_set(unsigned long bits)
 115 {
 116         unsigned long oldmsr = mfmsr();
 117         unsigned long newmsr;
 118
 119         newmsr = oldmsr | bits;
 120
 121 #ifdef CONFIG_VSX
 122         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 123                 newmsr |= MSR_VSX;
 124 #endif
 125
 126         if (oldmsr != newmsr)
 127                 mtmsr_isync(newmsr);
 128
 129         return newmsr;
 130 }
 131
 132 void __msr_check_and_clear(unsigned long bits)
 133 {
 134         unsigned long oldmsr = mfmsr();
 135         unsigned long newmsr;
 136
 137         newmsr = oldmsr & ~bits;
 138
 139 #ifdef CONFIG_VSX
 140         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 141                 newmsr &= ~MSR_VSX;
 142 #endif
 143
 144         if (oldmsr != newmsr)
 145                 mtmsr_isync(newmsr);
 146 }
 147 EXPORT_SYMBOL(__msr_check_and_clear);
 148
 149 #ifdef CONFIG_PPC_FPU
 150 void __giveup_fpu(struct task_struct *tsk)
 151 {
 152         unsigned long msr;
 153
 154         save_fpu(tsk);
 155         msr = tsk->thread.regs->msr;
 156         msr &= ~MSR_FP;
 157 #ifdef CONFIG_VSX
 158         if (cpu_has_feature(CPU_FTR_VSX))
 159                 msr &= ~MSR_VSX;
 160 #endif
 161         tsk->thread.regs->msr = msr;
 162 }
 163
 164 void giveup_fpu(struct task_struct *tsk)
 165 {
 166         check_if_tm_restore_required(tsk);
 167
 168         msr_check_and_set(MSR_FP);
 169         __giveup_fpu(tsk);
 170         msr_check_and_clear(MSR_FP);
 171 }
 172 EXPORT_SYMBOL(giveup_fpu);
 173
 174 /*
 175  * Make sure the floating-point register state in the
 176  * the thread_struct is up to date for task tsk.
 177  */
 178 void flush_fp_to_thread(struct task_struct *tsk)
 179 {
 180         if (tsk->thread.regs) {
 181                 /*
 182                  * We need to disable preemption here because if we didn't,
 183                  * another process could get scheduled after the regs->msr
 184                  * test but before we have finished saving the FP registers
 185                  * to the thread_struct.  That process could take over the
 186                  * FPU, and then when we get scheduled again we would store
 187                  * bogus values for the remaining FP registers.
 188                  */
 189                 preempt_disable();
 190                 if (tsk->thread.regs->msr & MSR_FP) {
 191                         /*
 192                          * This should only ever be called for current or
 193                          * for a stopped child process.  Since we save away
 194                          * the FP register state on context switch,
 195                          * there is something wrong if a stopped child appears
 196                          * to still have its FP state in the CPU registers.
 197                          */
 198                         BUG_ON(tsk != current);
 199                         giveup_fpu(tsk);
 200                 }
 201                 preempt_enable();
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 205
 206 void enable_kernel_fp(void)
 207 {
 208         unsigned long cpumsr;
 209
 210         WARN_ON(preemptible());
 211
 212         cpumsr = msr_check_and_set(MSR_FP);
 213
 214         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 215                 check_if_tm_restore_required(current);
 216                 /*
 217                  * If a thread has already been reclaimed then the
 218                  * checkpointed registers are on the CPU but have definitely
 219                  * been saved by the reclaim code. Don't need to and *cannot*
 220                  * giveup as this would save  to the 'live' structure not the
 221                  * checkpointed structure.
 222                  */
 223                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 224                         return;
 225                 __giveup_fpu(current);
 226         }
 227 }
 228 EXPORT_SYMBOL(enable_kernel_fp);
 229
 230 static int restore_fp(struct task_struct *tsk) {
 231         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 232                 load_fp_state(&current->thread.fp_state);
 233                 current->thread.load_fp++;
 234                 return 1;
 235         }
 236         return 0;
 237 }
 238 #else
 239 static int restore_fp(struct task_struct *tsk) { return 0; }
 240 #endif /* CONFIG_PPC_FPU */
 241
 242 #ifdef CONFIG_ALTIVEC
 243 #define loadvec(thr) ((thr).load_vec)
 244
 245 static void __giveup_altivec(struct task_struct *tsk)
 246 {
 247         unsigned long msr;
 248
 249         save_altivec(tsk);
 250         msr = tsk->thread.regs->msr;
 251         msr &= ~MSR_VEC;
 252 #ifdef CONFIG_VSX
 253         if (cpu_has_feature(CPU_FTR_VSX))
 254                 msr &= ~MSR_VSX;
 255 #endif
 256         tsk->thread.regs->msr = msr;
 257 }
 258
 259 void giveup_altivec(struct task_struct *tsk)
 260 {
 261         check_if_tm_restore_required(tsk);
 262
 263         msr_check_and_set(MSR_VEC);
 264         __giveup_altivec(tsk);
 265         msr_check_and_clear(MSR_VEC);
 266 }
 267 EXPORT_SYMBOL(giveup_altivec);
 268
 269 void enable_kernel_altivec(void)
 270 {
 271         unsigned long cpumsr;
 272
 273         WARN_ON(preemptible());
 274
 275         cpumsr = msr_check_and_set(MSR_VEC);
 276
 277         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 278                 check_if_tm_restore_required(current);
 279                 /*
 280                  * If a thread has already been reclaimed then the
 281                  * checkpointed registers are on the CPU but have definitely
 282                  * been saved by the reclaim code. Don't need to and *cannot*
 283                  * giveup as this would save  to the 'live' structure not the
 284                  * checkpointed structure.
 285                  */
 286                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 287                         return;
 288                 __giveup_altivec(current);
 289         }
 290 }
 291 EXPORT_SYMBOL(enable_kernel_altivec);
 292
 293 /*
 294  * Make sure the VMX/Altivec register state in the
 295  * the thread_struct is up to date for task tsk.
 296  */
 297 void flush_altivec_to_thread(struct task_struct *tsk)
 298 {
 299         if (tsk->thread.regs) {
 300                 preempt_disable();
 301                 if (tsk->thread.regs->msr & MSR_VEC) {
 302                         BUG_ON(tsk != current);
 303                         giveup_altivec(tsk);
 304                 }
 305                 preempt_enable();
 306         }
 307 }
 308 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 309
 310 static int restore_altivec(struct task_struct *tsk)
 311 {
 312         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 313                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 314                 load_vr_state(&tsk->thread.vr_state);
 315                 tsk->thread.used_vr = 1;
 316                 tsk->thread.load_vec++;
 317
 318                 return 1;
 319         }
 320         return 0;
 321 }
 322 #else
 323 #define loadvec(thr) 0
 324 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 325 #endif /* CONFIG_ALTIVEC */
 326
 327 #ifdef CONFIG_VSX
 328 static void __giveup_vsx(struct task_struct *tsk)
 329 {
 330         if (tsk->thread.regs->msr & MSR_FP)
 331                 __giveup_fpu(tsk);
 332         if (tsk->thread.regs->msr & MSR_VEC)
 333                 __giveup_altivec(tsk);
 334         tsk->thread.regs->msr &= ~MSR_VSX;
 335 }
 336
 337 static void giveup_vsx(struct task_struct *tsk)
 338 {
 339         check_if_tm_restore_required(tsk);
 340
 341         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 342         __giveup_vsx(tsk);
 343         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 344 }
 345
 346 static void save_vsx(struct task_struct *tsk)
 347 {
 348         if (tsk->thread.regs->msr & MSR_FP)
 349                 save_fpu(tsk);
 350         if (tsk->thread.regs->msr & MSR_VEC)
 351                 save_altivec(tsk);
 352 }
 353
 354 void enable_kernel_vsx(void)
 355 {
 356         unsigned long cpumsr;
 357
 358         WARN_ON(preemptible());
 359
 360         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 361
 362         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 363                 check_if_tm_restore_required(current);
 364                 /*
 365                  * If a thread has already been reclaimed then the
 366                  * checkpointed registers are on the CPU but have definitely
 367                  * been saved by the reclaim code. Don't need to and *cannot*
 368                  * giveup as this would save  to the 'live' structure not the
 369                  * checkpointed structure.
 370                  */
 371                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 372                         return;
 373                 if (current->thread.regs->msr & MSR_FP)
 374                         __giveup_fpu(current);
 375                 if (current->thread.regs->msr & MSR_VEC)
 376                         __giveup_altivec(current);
 377                 __giveup_vsx(current);
 378         }
 379 }
 380 EXPORT_SYMBOL(enable_kernel_vsx);
 381
 382 void flush_vsx_to_thread(struct task_struct *tsk)
 383 {
 384         if (tsk->thread.regs) {
 385                 preempt_disable();
 386                 if (tsk->thread.regs->msr & MSR_VSX) {
 387                         BUG_ON(tsk != current);
 388                         giveup_vsx(tsk);
 389                 }
 390                 preempt_enable();
 391         }
 392 }
 393 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 394
 395 static int restore_vsx(struct task_struct *tsk)
 396 {
 397         if (cpu_has_feature(CPU_FTR_VSX)) {
 398                 tsk->thread.used_vsr = 1;
 399                 return 1;
 400         }
 401
 402         return 0;
 403 }
 404 #else
 405 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 406 static inline void save_vsx(struct task_struct *tsk) { }
 407 #endif /* CONFIG_VSX */
 408
 409 #ifdef CONFIG_SPE
 410 void giveup_spe(struct task_struct *tsk)
 411 {
 412         check_if_tm_restore_required(tsk);
 413
 414         msr_check_and_set(MSR_SPE);
 415         __giveup_spe(tsk);
 416         msr_check_and_clear(MSR_SPE);
 417 }
 418 EXPORT_SYMBOL(giveup_spe);
 419
 420 void enable_kernel_spe(void)
 421 {
 422         WARN_ON(preemptible());
 423
 424         msr_check_and_set(MSR_SPE);
 425
 426         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 427                 check_if_tm_restore_required(current);
 428                 __giveup_spe(current);
 429         }
 430 }
 431 EXPORT_SYMBOL(enable_kernel_spe);
 432
 433 void flush_spe_to_thread(struct task_struct *tsk)
 434 {
 435         if (tsk->thread.regs) {
 436                 preempt_disable();
 437                 if (tsk->thread.regs->msr & MSR_SPE) {
 438                         BUG_ON(tsk != current);
 439                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 440                         giveup_spe(tsk);
 441                 }
 442                 preempt_enable();
 443         }
 444 }
 445 #endif /* CONFIG_SPE */
 446
 447 static unsigned long msr_all_available;
 448
 449 static int __init init_msr_all_available(void)
 450 {
 451 #ifdef CONFIG_PPC_FPU
 452         msr_all_available |= MSR_FP;
 453 #endif
 454 #ifdef CONFIG_ALTIVEC
 455         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 456                 msr_all_available |= MSR_VEC;
 457 #endif
 458 #ifdef CONFIG_VSX
 459         if (cpu_has_feature(CPU_FTR_VSX))
 460                 msr_all_available |= MSR_VSX;
 461 #endif
 462 #ifdef CONFIG_SPE
 463         if (cpu_has_feature(CPU_FTR_SPE))
 464                 msr_all_available |= MSR_SPE;
 465 #endif
 466
 467         return 0;
 468 }
 469 early_initcall(init_msr_all_available);
 470
 471 void giveup_all(struct task_struct *tsk)
 472 {
 473         unsigned long usermsr;
 474
 475         if (!tsk->thread.regs)
 476                 return;
 477
 478         usermsr = tsk->thread.regs->msr;
 479
 480         if ((usermsr & msr_all_available) == 0)
 481                 return;
 482
 483         msr_check_and_set(msr_all_available);
 484         check_if_tm_restore_required(tsk);
 485
 486 #ifdef CONFIG_PPC_FPU
 487         if (usermsr & MSR_FP)
 488                 __giveup_fpu(tsk);
 489 #endif
 490 #ifdef CONFIG_ALTIVEC
 491         if (usermsr & MSR_VEC)
 492                 __giveup_altivec(tsk);
 493 #endif
 494 #ifdef CONFIG_VSX
 495         if (usermsr & MSR_VSX)
 496                 __giveup_vsx(tsk);
 497 #endif
 498 #ifdef CONFIG_SPE
 499         if (usermsr & MSR_SPE)
 500                 __giveup_spe(tsk);
 501 #endif
 502
 503         msr_check_and_clear(msr_all_available);
 504 }
 505 EXPORT_SYMBOL(giveup_all);
 506
 507 void restore_math(struct pt_regs *regs)
 508 {
 509         unsigned long msr;
 510
 511         if (!msr_tm_active(regs->msr) &&
 512                 !current->thread.load_fp && !loadvec(current->thread))
 513                 return;
 514
 515         msr = regs->msr;
 516         msr_check_and_set(msr_all_available);
 517
 518         /*
 519          * Only reload if the bit is not set in the user MSR, the bit BEING set
 520          * indicates that the registers are hot
 521          */
 522         if ((!(msr & MSR_FP)) && restore_fp(current))
 523                 msr |= MSR_FP | current->thread.fpexc_mode;
 524
 525         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 526                 msr |= MSR_VEC;
 527
 528         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 529                         restore_vsx(current)) {
 530                 msr |= MSR_VSX;
 531         }
 532
 533         msr_check_and_clear(msr_all_available);
 534
 535         regs->msr = msr;
 536 }
 537
 538 void save_all(struct task_struct *tsk)
 539 {
 540         unsigned long usermsr;
 541
 542         if (!tsk->thread.regs)
 543                 return;
 544
 545         usermsr = tsk->thread.regs->msr;
 546
 547         if ((usermsr & msr_all_available) == 0)
 548                 return;
 549
 550         msr_check_and_set(msr_all_available);
 551
 552         /*
 553          * Saving the way the register space is in hardware, save_vsx boils
 554          * down to a save_fpu() and save_altivec()
 555          */
 556         if (usermsr & MSR_VSX) {
 557                 save_vsx(tsk);
 558         } else {
 559                 if (usermsr & MSR_FP)
 560                         save_fpu(tsk);
 561
 562                 if (usermsr & MSR_VEC)
 563                         save_altivec(tsk);
 564         }
 565
 566         if (usermsr & MSR_SPE)
 567                 __giveup_spe(tsk);
 568
 569         msr_check_and_clear(msr_all_available);
 570 }
 571
 572 void flush_all_to_thread(struct task_struct *tsk)
 573 {
 574         if (tsk->thread.regs) {
 575                 preempt_disable();
 576                 BUG_ON(tsk != current);
 577                 save_all(tsk);
 578
 579 #ifdef CONFIG_SPE
 580                 if (tsk->thread.regs->msr & MSR_SPE)
 581                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 582 #endif
 583
 584                 preempt_enable();
 585         }
 586 }
 587 EXPORT_SYMBOL(flush_all_to_thread);
 588
 589 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 590 void do_send_trap(struct pt_regs *regs, unsigned long address,
 591                   unsigned long error_code, int signal_code, int breakpt)
 592 {
 593         siginfo_t info;
 594
 595         current->thread.trap_nr = signal_code;
 596         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 597                         11, SIGSEGV) == NOTIFY_STOP)
 598                 return;
 599
 600         /* Deliver the signal to userspace */
 601         info.si_signo = SIGTRAP;
 602         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 603         info.si_code = signal_code;
 604         info.si_addr = (void __user *)address;
 605         force_sig_info(SIGTRAP, &info, current);
 606 }
 607 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 608 void do_break (struct pt_regs *regs, unsigned long address,
 609                     unsigned long error_code)
 610 {
 611         siginfo_t info;
 612
 613         current->thread.trap_nr = TRAP_HWBKPT;
 614         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 615                         11, SIGSEGV) == NOTIFY_STOP)
 616                 return;
 617
 618         if (debugger_break_match(regs))
 619                 return;
 620
 621         /* Clear the breakpoint */
 622         hw_breakpoint_disable();
 623
 624         /* Deliver the signal to userspace */
 625         info.si_signo = SIGTRAP;
 626         info.si_errno = 0;
 627         info.si_code = TRAP_HWBKPT;
 628         info.si_addr = (void __user *)address;
 629         force_sig_info(SIGTRAP, &info, current);
 630 }
 631 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 632
 633 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 634
 635 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 636 /*
 637  * Set the debug registers back to their default "safe" values.
 638  */
 639 static void set_debug_reg_defaults(struct thread_struct *thread)
 640 {
 641         thread->debug.iac1 = thread->debug.iac2 = 0;
 642 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 643         thread->debug.iac3 = thread->debug.iac4 = 0;
 644 #endif
 645         thread->debug.dac1 = thread->debug.dac2 = 0;
 646 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 647         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 648 #endif
 649         thread->debug.dbcr0 = 0;
 650 #ifdef CONFIG_BOOKE
 651         /*
 652          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 653          */
 654         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 655                         DBCR1_IAC3US | DBCR1_IAC4US;
 656         /*
 657          * Force Data Address Compare User/Supervisor bits to be User-only
 658          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 659          */
 660         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 661 #else
 662         thread->debug.dbcr1 = 0;
 663 #endif
 664 }
 665
 666 static void prime_debug_regs(struct debug_reg *debug)
 667 {
 668         /*
 669          * We could have inherited MSR_DE from userspace, since
 670          * it doesn't get cleared on exception entry.  Make sure
 671          * MSR_DE is clear before we enable any debug events.
 672          */
 673         mtmsr(mfmsr() & ~MSR_DE);
 674
 675         mtspr(SPRN_IAC1, debug->iac1);
 676         mtspr(SPRN_IAC2, debug->iac2);
 677 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 678         mtspr(SPRN_IAC3, debug->iac3);
 679         mtspr(SPRN_IAC4, debug->iac4);
 680 #endif
 681         mtspr(SPRN_DAC1, debug->dac1);
 682         mtspr(SPRN_DAC2, debug->dac2);
 683 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 684         mtspr(SPRN_DVC1, debug->dvc1);
 685         mtspr(SPRN_DVC2, debug->dvc2);
 686 #endif
 687         mtspr(SPRN_DBCR0, debug->dbcr0);
 688         mtspr(SPRN_DBCR1, debug->dbcr1);
 689 #ifdef CONFIG_BOOKE
 690         mtspr(SPRN_DBCR2, debug->dbcr2);
 691 #endif
 692 }
 693 /*
 694  * Unless neither the old or new thread are making use of the
 695  * debug registers, set the debug registers from the values
 696  * stored in the new thread.
 697  */
 698 void switch_booke_debug_regs(struct debug_reg *new_debug)
 699 {
 700         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 701                 || (new_debug->dbcr0 & DBCR0_IDM))
 702                         prime_debug_regs(new_debug);
 703 }
 704 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 705 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 706 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 707 static void set_debug_reg_defaults(struct thread_struct *thread)
 708 {
 709         thread->hw_brk.address = 0;
 710         thread->hw_brk.type = 0;
 711         set_breakpoint(&thread->hw_brk);
 712 }
 713 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 714 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 715
 716 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 717 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 718 {
 719         mtspr(SPRN_DAC1, dabr);
 720 #ifdef CONFIG_PPC_47x
 721         isync();
 722 #endif
 723         return 0;
 724 }
 725 #elif defined(CONFIG_PPC_BOOK3S)
 726 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 727 {
 728         mtspr(SPRN_DABR, dabr);
 729         if (cpu_has_feature(CPU_FTR_DABRX))
 730                 mtspr(SPRN_DABRX, dabrx);
 731         return 0;
 732 }
 733 #elif defined(CONFIG_PPC_8xx)
 734 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 735 {
 736         unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
 737         unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
 738         unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
 739
 740         if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
 741                 lctrl1 |= 0xa0000;
 742         else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
 743                 lctrl1 |= 0xf0000;
 744         else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
 745                 lctrl2 = 0;
 746
 747         mtspr(SPRN_LCTRL2, 0);
 748         mtspr(SPRN_CMPE, addr);
 749         mtspr(SPRN_CMPF, addr + 4);
 750         mtspr(SPRN_LCTRL1, lctrl1);
 751         mtspr(SPRN_LCTRL2, lctrl2);
 752
 753         return 0;
 754 }
 755 #else
 756 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 757 {
 758         return -EINVAL;
 759 }
 760 #endif
 761
 762 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 763 {
 764         unsigned long dabr, dabrx;
 765
 766         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 767         dabrx = ((brk->type >> 3) & 0x7);
 768
 769         if (ppc_md.set_dabr)
 770                 return ppc_md.set_dabr(dabr, dabrx);
 771
 772         return __set_dabr(dabr, dabrx);
 773 }
 774
 775 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 776 {
 777         unsigned long dawr, dawrx, mrd;
 778
 779         dawr = brk->address;
 780
 781         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 782                                    << (63 - 58); //* read/write bits */
 783         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 784                                    << (63 - 59); //* translate */
 785         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 786                                    >> 3; //* PRIM bits */
 787         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 788            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 789            0b111111=64DW.
 790            brk->len is in bytes.
 791            This aligns up to double word size, shifts and does the bias.
 792         */
 793         mrd = ((brk->len + 7) >> 3) - 1;
 794         dawrx |= (mrd & 0x3f) << (63 - 53);
 795
 796         if (ppc_md.set_dawr)
 797                 return ppc_md.set_dawr(dawr, dawrx);
 798         mtspr(SPRN_DAWR, dawr);
 799         mtspr(SPRN_DAWRX, dawrx);
 800         return 0;
 801 }
 802
 803 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 804 {
 805         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 806
 807         if (cpu_has_feature(CPU_FTR_DAWR))
 808                 set_dawr(brk);
 809         else
 810                 set_dabr(brk);
 811 }
 812
 813 void set_breakpoint(struct arch_hw_breakpoint *brk)
 814 {
 815         preempt_disable();
 816         __set_breakpoint(brk);
 817         preempt_enable();
 818 }
 819
 820 #ifdef CONFIG_PPC64
 821 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 822 #endif
 823
 824 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 825                               struct arch_hw_breakpoint *b)
 826 {
 827         if (a->address != b->address)
 828                 return false;
 829         if (a->type != b->type)
 830                 return false;
 831         if (a->len != b->len)
 832                 return false;
 833         return true;
 834 }
 835
 836 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 837
 838 static inline bool tm_enabled(struct task_struct *tsk)
 839 {
 840         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 841 }
 842
 843 static void tm_reclaim_thread(struct thread_struct *thr,
 844                               struct thread_info *ti, uint8_t cause)
 845 {
 846         /*
 847          * Use the current MSR TM suspended bit to track if we have
 848          * checkpointed state outstanding.
 849          * On signal delivery, we'd normally reclaim the checkpointed
 850          * state to obtain stack pointer (see:get_tm_stackpointer()).
 851          * This will then directly return to userspace without going
 852          * through __switch_to(). However, if the stack frame is bad,
 853          * we need to exit this thread which calls __switch_to() which
 854          * will again attempt to reclaim the already saved tm state.
 855          * Hence we need to check that we've not already reclaimed
 856          * this state.
 857          * We do this using the current MSR, rather tracking it in
 858          * some specific thread_struct bit, as it has the additional
 859          * benefit of checking for a potential TM bad thing exception.
 860          */
 861         if (!MSR_TM_SUSPENDED(mfmsr()))
 862                 return;
 863
 864         giveup_all(container_of(thr, struct task_struct, thread));
 865
 866         tm_reclaim(thr, thr->ckpt_regs.msr, cause);
 867 }
 868
 869 void tm_reclaim_current(uint8_t cause)
 870 {
 871         tm_enable();
 872         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 873 }
 874
 875 static inline void tm_reclaim_task(struct task_struct *tsk)
 876 {
 877         /* We have to work out if we're switching from/to a task that's in the
 878          * middle of a transaction.
 879          *
 880          * In switching we need to maintain a 2nd register state as
 881          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 882          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 883          * ckvr_state
 884          *
 885          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 886          */
 887         struct thread_struct *thr = &tsk->thread;
 888
 889         if (!thr->regs)
 890                 return;
 891
 892         if (!MSR_TM_ACTIVE(thr->regs->msr))
 893                 goto out_and_saveregs;
 894
 895         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 896                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 897                  tsk->pid, thr->regs->nip,
 898                  thr->regs->ccr, thr->regs->msr,
 899                  thr->regs->trap);
 900
 901         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 902
 903         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 904                  tsk->pid);
 905
 906 out_and_saveregs:
 907         /* Always save the regs here, even if a transaction's not active.
 908          * This context-switches a thread's TM info SPRs.  We do it here to
 909          * be consistent with the restore path (in recheckpoint) which
 910          * cannot happen later in _switch().
 911          */
 912         tm_save_sprs(thr);
 913 }
 914
 915 extern void __tm_recheckpoint(struct thread_struct *thread,
 916                               unsigned long orig_msr);
 917
 918 void tm_recheckpoint(struct thread_struct *thread,
 919                      unsigned long orig_msr)
 920 {
 921         unsigned long flags;
 922
 923         if (!(thread->regs->msr & MSR_TM))
 924                 return;
 925
 926         /* We really can't be interrupted here as the TEXASR registers can't
 927          * change and later in the trecheckpoint code, we have a userspace R1.
 928          * So let's hard disable over this region.
 929          */
 930         local_irq_save(flags);
 931         hard_irq_disable();
 932
 933         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 934          * before the trecheckpoint and no explosion occurs.
 935          */
 936         tm_restore_sprs(thread);
 937
 938         __tm_recheckpoint(thread, orig_msr);
 939
 940         local_irq_restore(flags);
 941 }
 942
 943 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 944 {
 945         unsigned long msr;
 946
 947         if (!cpu_has_feature(CPU_FTR_TM))
 948                 return;
 949
 950         /* Recheckpoint the registers of the thread we're about to switch to.
 951          *
 952          * If the task was using FP, we non-lazily reload both the original and
 953          * the speculative FP register states.  This is because the kernel
 954          * doesn't see if/when a TM rollback occurs, so if we take an FP
 955          * unavailable later, we are unable to determine which set of FP regs
 956          * need to be restored.
 957          */
 958         if (!tm_enabled(new))
 959                 return;
 960
 961         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 962                 tm_restore_sprs(&new->thread);
 963                 return;
 964         }
 965         msr = new->thread.ckpt_regs.msr;
 966         /* Recheckpoint to restore original checkpointed register state. */
 967         TM_DEBUG("*** tm_recheckpoint of pid %d "
 968                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 969                  new->pid, new->thread.regs->msr, msr);
 970
 971         tm_recheckpoint(&new->thread, msr);
 972
 973         /*
 974          * The checkpointed state has been restored but the live state has
 975          * not, ensure all the math functionality is turned off to trigger
 976          * restore_math() to reload.
 977          */
 978         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
 979
 980         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 981                  "(kernel msr 0x%lx)\n",
 982                  new->pid, mfmsr());
 983 }
 984
 985 static inline void __switch_to_tm(struct task_struct *prev,
 986                 struct task_struct *new)
 987 {
 988         if (cpu_has_feature(CPU_FTR_TM)) {
 989                 if (tm_enabled(prev) || tm_enabled(new))
 990                         tm_enable();
 991
 992                 if (tm_enabled(prev)) {
 993                         prev->thread.load_tm++;
 994                         tm_reclaim_task(prev);
 995                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
 996                                 prev->thread.regs->msr &= ~MSR_TM;
 997                 }
 998
 999                 tm_recheckpoint_new_task(new);
1000         }
1001 }
1002
1003 /*
1004  * This is called if we are on the way out to userspace and the
1005  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1006  * FP and/or vector state and does so if necessary.
1007  * If userspace is inside a transaction (whether active or
1008  * suspended) and FP/VMX/VSX instructions have ever been enabled
1009  * inside that transaction, then we have to keep them enabled
1010  * and keep the FP/VMX/VSX state loaded while ever the transaction
1011  * continues.  The reason is that if we didn't, and subsequently
1012  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1013  * we don't know whether it's the same transaction, and thus we
1014  * don't know which of the checkpointed state and the transactional
1015  * state to use.
1016  */
1017 void restore_tm_state(struct pt_regs *regs)
1018 {
1019         unsigned long msr_diff;
1020
1021         /*
1022          * This is the only moment we should clear TIF_RESTORE_TM as
1023          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1024          * again, anything else could lead to an incorrect ckpt_msr being
1025          * saved and therefore incorrect signal contexts.
1026          */
1027         clear_thread_flag(TIF_RESTORE_TM);
1028         if (!MSR_TM_ACTIVE(regs->msr))
1029                 return;
1030
1031         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1032         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1033
1034         /* Ensure that restore_math() will restore */
1035         if (msr_diff & MSR_FP)
1036                 current->thread.load_fp = 1;
1037 #ifdef CONFIG_ALTIVEC
1038         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1039                 current->thread.load_vec = 1;
1040 #endif
1041         restore_math(regs);
1042
1043         regs->msr |= msr_diff;
1044 }
1045
1046 #else
1047 #define tm_recheckpoint_new_task(new)
1048 #define __switch_to_tm(prev, new)
1049 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1050
1051 static inline void save_sprs(struct thread_struct *t)
1052 {
1053 #ifdef CONFIG_ALTIVEC
1054         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1055                 t->vrsave = mfspr(SPRN_VRSAVE);
1056 #endif
1057 #ifdef CONFIG_PPC_BOOK3S_64
1058         if (cpu_has_feature(CPU_FTR_DSCR))
1059                 t->dscr = mfspr(SPRN_DSCR);
1060
1061         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1062                 t->bescr = mfspr(SPRN_BESCR);
1063                 t->ebbhr = mfspr(SPRN_EBBHR);
1064                 t->ebbrr = mfspr(SPRN_EBBRR);
1065
1066                 t->fscr = mfspr(SPRN_FSCR);
1067
1068                 /*
1069                  * Note that the TAR is not available for use in the kernel.
1070                  * (To provide this, the TAR should be backed up/restored on
1071                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1072                  * this should be in pt_regs anyway (for debug).)
1073                  */
1074                 t->tar = mfspr(SPRN_TAR);
1075         }
1076 #endif
1077 }
1078
1079 static inline void restore_sprs(struct thread_struct *old_thread,
1080                                 struct thread_struct *new_thread)
1081 {
1082 #ifdef CONFIG_ALTIVEC
1083         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1084             old_thread->vrsave != new_thread->vrsave)
1085                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1086 #endif
1087 #ifdef CONFIG_PPC_BOOK3S_64
1088         if (cpu_has_feature(CPU_FTR_DSCR)) {
1089                 u64 dscr = get_paca()->dscr_default;
1090                 if (new_thread->dscr_inherit)
1091                         dscr = new_thread->dscr;
1092
1093                 if (old_thread->dscr != dscr)
1094                         mtspr(SPRN_DSCR, dscr);
1095         }
1096
1097         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1098                 if (old_thread->bescr != new_thread->bescr)
1099                         mtspr(SPRN_BESCR, new_thread->bescr);
1100                 if (old_thread->ebbhr != new_thread->ebbhr)
1101                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1102                 if (old_thread->ebbrr != new_thread->ebbrr)
1103                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1104
1105                 if (old_thread->fscr != new_thread->fscr)
1106                         mtspr(SPRN_FSCR, new_thread->fscr);
1107
1108                 if (old_thread->tar != new_thread->tar)
1109                         mtspr(SPRN_TAR, new_thread->tar);
1110         }
1111 #endif
1112 }
1113
1114 struct task_struct *__switch_to(struct task_struct *prev,
1115         struct task_struct *new)
1116 {
1117         struct thread_struct *new_thread, *old_thread;
1118         struct task_struct *last;
1119 #ifdef CONFIG_PPC_BOOK3S_64
1120         struct ppc64_tlb_batch *batch;
1121 #endif
1122
1123         new_thread = &new->thread;
1124         old_thread = &current->thread;
1125
1126         WARN_ON(!irqs_disabled());
1127
1128 #ifdef CONFIG_PPC64
1129         /*
1130          * Collect processor utilization data per process
1131          */
1132         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1133                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1134                 long unsigned start_tb, current_tb;
1135                 start_tb = old_thread->start_tb;
1136                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1137                 old_thread->accum_tb += (current_tb - start_tb);
1138                 new_thread->start_tb = current_tb;
1139         }
1140 #endif /* CONFIG_PPC64 */
1141
1142 #ifdef CONFIG_PPC_STD_MMU_64
1143         batch = this_cpu_ptr(&ppc64_tlb_batch);
1144         if (batch->active) {
1145                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1146                 if (batch->index)
1147                         __flush_tlb_pending(batch);
1148                 batch->active = 0;
1149         }
1150 #endif /* CONFIG_PPC_STD_MMU_64 */
1151
1152 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1153         switch_booke_debug_regs(&new->thread.debug);
1154 #else
1155 /*
1156  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1157  * schedule DABR
1158  */
1159 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1160         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1161                 __set_breakpoint(&new->thread.hw_brk);
1162 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1163 #endif
1164
1165         /*
1166          * We need to save SPRs before treclaim/trecheckpoint as these will
1167          * change a number of them.
1168          */
1169         save_sprs(&prev->thread);
1170
1171         /* Save FPU, Altivec, VSX and SPE state */
1172         giveup_all(prev);
1173
1174         __switch_to_tm(prev, new);
1175
1176         /*
1177          * We can't take a PMU exception inside _switch() since there is a
1178          * window where the kernel stack SLB and the kernel stack are out
1179          * of sync. Hard disable here.
1180          */
1181         hard_irq_disable();
1182
1183         /*
1184          * Call restore_sprs() before calling _switch(). If we move it after
1185          * _switch() then we miss out on calling it for new tasks. The reason
1186          * for this is we manually create a stack frame for new tasks that
1187          * directly returns through ret_from_fork() or
1188          * ret_from_kernel_thread(). See copy_thread() for details.
1189          */
1190         restore_sprs(old_thread, new_thread);
1191
1192         last = _switch(old_thread, new_thread);
1193
1194 #ifdef CONFIG_PPC_STD_MMU_64
1195         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1196                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1197                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1198                 batch->active = 1;
1199         }
1200
1201         if (current_thread_info()->task->thread.regs)
1202                 restore_math(current_thread_info()->task->thread.regs);
1203 #endif /* CONFIG_PPC_STD_MMU_64 */
1204
1205         return last;
1206 }
1207
1208 static int instructions_to_print = 16;
1209
1210 static void show_instructions(struct pt_regs *regs)
1211 {
1212         int i;
1213         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1214                         sizeof(int));
1215
1216         printk("Instruction dump:");
1217
1218         for (i = 0; i < instructions_to_print; i++) {
1219                 int instr;
1220
1221                 if (!(i % 8))
1222                         pr_cont("\n");
1223
1224 #if !defined(CONFIG_BOOKE)
1225                 /* If executing with the IMMU off, adjust pc rather
1226                  * than print XXXXXXXX.
1227                  */
1228                 if (!(regs->msr & MSR_IR))
1229                         pc = (unsigned long)phys_to_virt(pc);
1230 #endif
1231
1232                 if (!__kernel_text_address(pc) ||
1233                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1234                         pr_cont("XXXXXXXX ");
1235                 } else {
1236                         if (regs->nip == pc)
1237                                 pr_cont("<%08x> ", instr);
1238                         else
1239                                 pr_cont("%08x ", instr);
1240                 }
1241
1242                 pc += sizeof(int);
1243         }
1244
1245         pr_cont("\n");
1246 }
1247
1248 struct regbit {
1249         unsigned long bit;
1250         const char *name;
1251 };
1252
1253 static struct regbit msr_bits[] = {
1254 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1255         {MSR_SF,        "SF"},
1256         {MSR_HV,        "HV"},
1257 #endif
1258         {MSR_VEC,       "VEC"},
1259         {MSR_VSX,       "VSX"},
1260 #ifdef CONFIG_BOOKE
1261         {MSR_CE,        "CE"},
1262 #endif
1263         {MSR_EE,        "EE"},
1264         {MSR_PR,        "PR"},
1265         {MSR_FP,        "FP"},
1266         {MSR_ME,        "ME"},
1267 #ifdef CONFIG_BOOKE
1268         {MSR_DE,        "DE"},
1269 #else
1270         {MSR_SE,        "SE"},
1271         {MSR_BE,        "BE"},
1272 #endif
1273         {MSR_IR,        "IR"},
1274         {MSR_DR,        "DR"},
1275         {MSR_PMM,       "PMM"},
1276 #ifndef CONFIG_BOOKE
1277         {MSR_RI,        "RI"},
1278         {MSR_LE,        "LE"},
1279 #endif
1280         {0,             NULL}
1281 };
1282
1283 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1284 {
1285         const char *s = "";
1286
1287         for (; bits->bit; ++bits)
1288                 if (val & bits->bit) {
1289                         pr_cont("%s%s", s, bits->name);
1290                         s = sep;
1291                 }
1292 }
1293
1294 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1295 static struct regbit msr_tm_bits[] = {
1296         {MSR_TS_T,      "T"},
1297         {MSR_TS_S,      "S"},
1298         {MSR_TM,        "E"},
1299         {0,             NULL}
1300 };
1301
1302 static void print_tm_bits(unsigned long val)
1303 {
1304 /*
1305  * This only prints something if at least one of the TM bit is set.
1306  * Inside the TM[], the output means:
1307  *   E: Enabled         (bit 32)
1308  *   S: Suspended       (bit 33)
1309  *   T: Transactional   (bit 34)
1310  */
1311         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1312                 pr_cont(",TM[");
1313                 print_bits(val, msr_tm_bits, "");
1314                 pr_cont("]");
1315         }
1316 }
1317 #else
1318 static void print_tm_bits(unsigned long val) {}
1319 #endif
1320
1321 static void print_msr_bits(unsigned long val)
1322 {
1323         pr_cont("<");
1324         print_bits(val, msr_bits, ",");
1325         print_tm_bits(val);
1326         pr_cont(">");
1327 }
1328
1329 #ifdef CONFIG_PPC64
1330 #define REG             "%016lx"
1331 #define REGS_PER_LINE   4
1332 #define LAST_VOLATILE   13
1333 #else
1334 #define REG             "%08lx"
1335 #define REGS_PER_LINE   8
1336 #define LAST_VOLATILE   12
1337 #endif
1338
1339 void show_regs(struct pt_regs * regs)
1340 {
1341         int i, trap;
1342
1343         show_regs_print_info(KERN_DEFAULT);
1344
1345         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1346                regs->nip, regs->link, regs->ctr);
1347         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1348                regs, regs->trap, print_tainted(), init_utsname()->release);
1349         printk("MSR: "REG" ", regs->msr);
1350         print_msr_bits(regs->msr);
1351         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1352         trap = TRAP(regs);
1353         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1354                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1355         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1356 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1357                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1358 #else
1359                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1360 #endif
1361 #ifdef CONFIG_PPC64
1362         pr_cont("SOFTE: %ld ", regs->softe);
1363 #endif
1364 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1365         if (MSR_TM_ACTIVE(regs->msr))
1366                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1367 #endif
1368
1369         for (i = 0;  i < 32;  i++) {
1370                 if ((i % REGS_PER_LINE) == 0)
1371                         pr_cont("\nGPR%02d: ", i);
1372                 pr_cont(REG " ", regs->gpr[i]);
1373                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1374                         break;
1375         }
1376         pr_cont("\n");
1377 #ifdef CONFIG_KALLSYMS
1378         /*
1379          * Lookup NIP late so we have the best change of getting the
1380          * above info out without failing
1381          */
1382         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1383         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1384 #endif
1385         show_stack(current, (unsigned long *) regs->gpr[1]);
1386         if (!user_mode(regs))
1387                 show_instructions(regs);
1388 }
1389
1390 void flush_thread(void)
1391 {
1392 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1393         flush_ptrace_hw_breakpoint(current);
1394 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1395         set_debug_reg_defaults(&current->thread);
1396 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1397 }
1398
1399 void
1400 release_thread(struct task_struct *t)
1401 {
1402 }
1403
1404 /*
1405  * this gets called so that we can store coprocessor state into memory and
1406  * copy the current task into the new thread.
1407  */
1408 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1409 {
1410         flush_all_to_thread(src);
1411         /*
1412          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1413          * flush but it removes the checkpointed state from the current CPU and
1414          * transitions the CPU out of TM mode.  Hence we need to call
1415          * tm_recheckpoint_new_task() (on the same task) to restore the
1416          * checkpointed state back and the TM mode.
1417          *
1418          * Can't pass dst because it isn't ready. Doesn't matter, passing
1419          * dst is only important for __switch_to()
1420          */
1421         __switch_to_tm(src, src);
1422
1423         *dst = *src;
1424
1425         clear_task_ebb(dst);
1426
1427         return 0;
1428 }
1429
1430 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1431 {
1432 #ifdef CONFIG_PPC_STD_MMU_64
1433         unsigned long sp_vsid;
1434         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1435
1436         if (radix_enabled())
1437                 return;
1438
1439         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1440                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1441                         << SLB_VSID_SHIFT_1T;
1442         else
1443                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1444                         << SLB_VSID_SHIFT;
1445         sp_vsid |= SLB_VSID_KERNEL | llp;
1446         p->thread.ksp_vsid = sp_vsid;
1447 #endif
1448 }
1449
1450 /*
1451  * Copy a thread..
1452  */
1453
1454 /*
1455  * Copy architecture-specific thread state
1456  */
1457 int copy_thread(unsigned long clone_flags, unsigned long usp,
1458                 unsigned long kthread_arg, struct task_struct *p)
1459 {
1460         struct pt_regs *childregs, *kregs;
1461         extern void ret_from_fork(void);
1462         extern void ret_from_kernel_thread(void);
1463         void (*f)(void);
1464         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1465         struct thread_info *ti = task_thread_info(p);
1466
1467         klp_init_thread_info(ti);
1468
1469         /* Copy registers */
1470         sp -= sizeof(struct pt_regs);
1471         childregs = (struct pt_regs *) sp;
1472         if (unlikely(p->flags & PF_KTHREAD)) {
1473                 /* kernel thread */
1474                 memset(childregs, 0, sizeof(struct pt_regs));
1475                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1476                 /* function */
1477                 if (usp)
1478                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1479 #ifdef CONFIG_PPC64
1480                 clear_tsk_thread_flag(p, TIF_32BIT);
1481                 childregs->softe = 1;
1482 #endif
1483                 childregs->gpr[15] = kthread_arg;
1484                 p->thread.regs = NULL;  /* no user register state */
1485                 ti->flags |= _TIF_RESTOREALL;
1486                 f = ret_from_kernel_thread;
1487         } else {
1488                 /* user thread */
1489                 struct pt_regs *regs = current_pt_regs();
1490                 CHECK_FULL_REGS(regs);
1491                 *childregs = *regs;
1492                 if (usp)
1493                         childregs->gpr[1] = usp;
1494                 p->thread.regs = childregs;
1495                 childregs->gpr[3] = 0;  /* Result from fork() */
1496                 if (clone_flags & CLONE_SETTLS) {
1497 #ifdef CONFIG_PPC64
1498                         if (!is_32bit_task())
1499                                 childregs->gpr[13] = childregs->gpr[6];
1500                         else
1501 #endif
1502                                 childregs->gpr[2] = childregs->gpr[6];
1503                 }
1504
1505                 f = ret_from_fork;
1506         }
1507         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1508         sp -= STACK_FRAME_OVERHEAD;
1509
1510         /*
1511          * The way this works is that at some point in the future
1512          * some task will call _switch to switch to the new task.
1513          * That will pop off the stack frame created below and start
1514          * the new task running at ret_from_fork.  The new task will
1515          * do some house keeping and then return from the fork or clone
1516          * system call, using the stack frame created above.
1517          */
1518         ((unsigned long *)sp)[0] = 0;
1519         sp -= sizeof(struct pt_regs);
1520         kregs = (struct pt_regs *) sp;
1521         sp -= STACK_FRAME_OVERHEAD;
1522         p->thread.ksp = sp;
1523 #ifdef CONFIG_PPC32
1524         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1525                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1526 #endif
1527 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1528         p->thread.ptrace_bps[0] = NULL;
1529 #endif
1530
1531         p->thread.fp_save_area = NULL;
1532 #ifdef CONFIG_ALTIVEC
1533         p->thread.vr_save_area = NULL;
1534 #endif
1535
1536         setup_ksp_vsid(p, sp);
1537
1538 #ifdef CONFIG_PPC64
1539         if (cpu_has_feature(CPU_FTR_DSCR)) {
1540                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1541                 p->thread.dscr = mfspr(SPRN_DSCR);
1542         }
1543         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1544                 p->thread.ppr = INIT_PPR;
1545 #endif
1546         kregs->nip = ppc_function_entry(f);
1547         return 0;
1548 }
1549
1550 /*
1551  * Set up a thread for executing a new program
1552  */
1553 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1554 {
1555 #ifdef CONFIG_PPC64
1556         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1557 #endif
1558
1559         /*
1560          * If we exec out of a kernel thread then thread.regs will not be
1561          * set.  Do it now.
1562          */
1563         if (!current->thread.regs) {
1564                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1565                 current->thread.regs = regs - 1;
1566         }
1567
1568 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1569         /*
1570          * Clear any transactional state, we're exec()ing. The cause is
1571          * not important as there will never be a recheckpoint so it's not
1572          * user visible.
1573          */
1574         if (MSR_TM_SUSPENDED(mfmsr()))
1575                 tm_reclaim_current(0);
1576 #endif
1577
1578         memset(regs->gpr, 0, sizeof(regs->gpr));
1579         regs->ctr = 0;
1580         regs->link = 0;
1581         regs->xer = 0;
1582         regs->ccr = 0;
1583         regs->gpr[1] = sp;
1584
1585         /*
1586          * We have just cleared all the nonvolatile GPRs, so make
1587          * FULL_REGS(regs) return true.  This is necessary to allow
1588          * ptrace to examine the thread immediately after exec.
1589          */
1590         regs->trap &= ~1UL;
1591
1592 #ifdef CONFIG_PPC32
1593         regs->mq = 0;
1594         regs->nip = start;
1595         regs->msr = MSR_USER;
1596 #else
1597         if (!is_32bit_task()) {
1598                 unsigned long entry;
1599
1600                 if (is_elf2_task()) {
1601                         /* Look ma, no function descriptors! */
1602                         entry = start;
1603
1604                         /*
1605                          * Ulrich says:
1606                          *   The latest iteration of the ABI requires that when
1607                          *   calling a function (at its global entry point),
1608                          *   the caller must ensure r12 holds the entry point
1609                          *   address (so that the function can quickly
1610                          *   establish addressability).
1611                          */
1612                         regs->gpr[12] = start;
1613                         /* Make sure that's restored on entry to userspace. */
1614                         set_thread_flag(TIF_RESTOREALL);
1615                 } else {
1616                         unsigned long toc;
1617
1618                         /* start is a relocated pointer to the function
1619                          * descriptor for the elf _start routine.  The first
1620                          * entry in the function descriptor is the entry
1621                          * address of _start and the second entry is the TOC
1622                          * value we need to use.
1623                          */
1624                         __get_user(entry, (unsigned long __user *)start);
1625                         __get_user(toc, (unsigned long __user *)start+1);
1626
1627                         /* Check whether the e_entry function descriptor entries
1628                          * need to be relocated before we can use them.
1629                          */
1630                         if (load_addr != 0) {
1631                                 entry += load_addr;
1632                                 toc   += load_addr;
1633                         }
1634                         regs->gpr[2] = toc;
1635                 }
1636                 regs->nip = entry;
1637                 regs->msr = MSR_USER64;
1638         } else {
1639                 regs->nip = start;
1640                 regs->gpr[2] = 0;
1641                 regs->msr = MSR_USER32;
1642         }
1643 #endif
1644 #ifdef CONFIG_VSX
1645         current->thread.used_vsr = 0;
1646 #endif
1647         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1648         current->thread.fp_save_area = NULL;
1649 #ifdef CONFIG_ALTIVEC
1650         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1651         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1652         current->thread.vr_save_area = NULL;
1653         current->thread.vrsave = 0;
1654         current->thread.used_vr = 0;
1655 #endif /* CONFIG_ALTIVEC */
1656 #ifdef CONFIG_SPE
1657         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1658         current->thread.acc = 0;
1659         current->thread.spefscr = 0;
1660         current->thread.used_spe = 0;
1661 #endif /* CONFIG_SPE */
1662 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1663         current->thread.tm_tfhar = 0;
1664         current->thread.tm_texasr = 0;
1665         current->thread.tm_tfiar = 0;
1666 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1667 }
1668 EXPORT_SYMBOL(start_thread);
1669
1670 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1671                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1672
1673 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1674 {
1675         struct pt_regs *regs = tsk->thread.regs;
1676
1677         /* This is a bit hairy.  If we are an SPE enabled  processor
1678          * (have embedded fp) we store the IEEE exception enable flags in
1679          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1680          * mode (asyn, precise, disabled) for 'Classic' FP. */
1681         if (val & PR_FP_EXC_SW_ENABLE) {
1682 #ifdef CONFIG_SPE
1683                 if (cpu_has_feature(CPU_FTR_SPE)) {
1684                         /*
1685                          * When the sticky exception bits are set
1686                          * directly by userspace, it must call prctl
1687                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1688                          * in the existing prctl settings) or
1689                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1690                          * the bits being set).  <fenv.h> functions
1691                          * saving and restoring the whole
1692                          * floating-point environment need to do so
1693                          * anyway to restore the prctl settings from
1694                          * the saved environment.
1695                          */
1696                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1697                         tsk->thread.fpexc_mode = val &
1698                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1699                         return 0;
1700                 } else {
1701                         return -EINVAL;
1702                 }
1703 #else
1704                 return -EINVAL;
1705 #endif
1706         }
1707
1708         /* on a CONFIG_SPE this does not hurt us.  The bits that
1709          * __pack_fe01 use do not overlap with bits used for
1710          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1711          * on CONFIG_SPE implementations are reserved so writing to
1712          * them does not change anything */
1713         if (val > PR_FP_EXC_PRECISE)
1714                 return -EINVAL;
1715         tsk->thread.fpexc_mode = __pack_fe01(val);
1716         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1717                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1718                         | tsk->thread.fpexc_mode;
1719         return 0;
1720 }
1721
1722 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1723 {
1724         unsigned int val;
1725
1726         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1727 #ifdef CONFIG_SPE
1728                 if (cpu_has_feature(CPU_FTR_SPE)) {
1729                         /*
1730                          * When the sticky exception bits are set
1731                          * directly by userspace, it must call prctl
1732                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1733                          * in the existing prctl settings) or
1734                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1735                          * the bits being set).  <fenv.h> functions
1736                          * saving and restoring the whole
1737                          * floating-point environment need to do so
1738                          * anyway to restore the prctl settings from
1739                          * the saved environment.
1740                          */
1741                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1742                         val = tsk->thread.fpexc_mode;
1743                 } else
1744                         return -EINVAL;
1745 #else
1746                 return -EINVAL;
1747 #endif
1748         else
1749                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1750         return put_user(val, (unsigned int __user *) adr);
1751 }
1752
1753 int set_endian(struct task_struct *tsk, unsigned int val)
1754 {
1755         struct pt_regs *regs = tsk->thread.regs;
1756
1757         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1758             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1759                 return -EINVAL;
1760
1761         if (regs == NULL)
1762                 return -EINVAL;
1763
1764         if (val == PR_ENDIAN_BIG)
1765                 regs->msr &= ~MSR_LE;
1766         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1767                 regs->msr |= MSR_LE;
1768         else
1769                 return -EINVAL;
1770
1771         return 0;
1772 }
1773
1774 int get_endian(struct task_struct *tsk, unsigned long adr)
1775 {
1776         struct pt_regs *regs = tsk->thread.regs;
1777         unsigned int val;
1778
1779         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1780             !cpu_has_feature(CPU_FTR_REAL_LE))
1781                 return -EINVAL;
1782
1783         if (regs == NULL)
1784                 return -EINVAL;
1785
1786         if (regs->msr & MSR_LE) {
1787                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1788                         val = PR_ENDIAN_LITTLE;
1789                 else
1790                         val = PR_ENDIAN_PPC_LITTLE;
1791         } else
1792                 val = PR_ENDIAN_BIG;
1793
1794         return put_user(val, (unsigned int __user *)adr);
1795 }
1796
1797 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1798 {
1799         tsk->thread.align_ctl = val;
1800         return 0;
1801 }
1802
1803 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1804 {
1805         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1806 }
1807
1808 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1809                                   unsigned long nbytes)
1810 {
1811         unsigned long stack_page;
1812         unsigned long cpu = task_cpu(p);
1813
1814         /*
1815          * Avoid crashing if the stack has overflowed and corrupted
1816          * task_cpu(p), which is in the thread_info struct.
1817          */
1818         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1819                 stack_page = (unsigned long) hardirq_ctx[cpu];
1820                 if (sp >= stack_page + sizeof(struct thread_struct)
1821                     && sp <= stack_page + THREAD_SIZE - nbytes)
1822                         return 1;
1823
1824                 stack_page = (unsigned long) softirq_ctx[cpu];
1825                 if (sp >= stack_page + sizeof(struct thread_struct)
1826                     && sp <= stack_page + THREAD_SIZE - nbytes)
1827                         return 1;
1828         }
1829         return 0;
1830 }
1831
1832 int validate_sp(unsigned long sp, struct task_struct *p,
1833                        unsigned long nbytes)
1834 {
1835         unsigned long stack_page = (unsigned long)task_stack_page(p);
1836
1837         if (sp >= stack_page + sizeof(struct thread_struct)
1838             && sp <= stack_page + THREAD_SIZE - nbytes)
1839                 return 1;
1840
1841         return valid_irq_stack(sp, p, nbytes);
1842 }
1843
1844 EXPORT_SYMBOL(validate_sp);
1845
1846 unsigned long get_wchan(struct task_struct *p)
1847 {
1848         unsigned long ip, sp;
1849         int count = 0;
1850
1851         if (!p || p == current || p->state == TASK_RUNNING)
1852                 return 0;
1853
1854         sp = p->thread.ksp;
1855         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1856                 return 0;
1857
1858         do {
1859                 sp = *(unsigned long *)sp;
1860                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1861                         return 0;
1862                 if (count > 0) {
1863                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1864                         if (!in_sched_functions(ip))
1865                                 return ip;
1866                 }
1867         } while (count++ < 16);
1868         return 0;
1869 }
1870
1871 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1872
1873 void show_stack(struct task_struct *tsk, unsigned long *stack)
1874 {
1875         unsigned long sp, ip, lr, newsp;
1876         int count = 0;
1877         int firstframe = 1;
1878 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1879         int curr_frame = current->curr_ret_stack;
1880         extern void return_to_handler(void);
1881         unsigned long rth = (unsigned long)return_to_handler;
1882 #endif
1883
1884         sp = (unsigned long) stack;
1885         if (tsk == NULL)
1886                 tsk = current;
1887         if (sp == 0) {
1888                 if (tsk == current)
1889                         sp = current_stack_pointer();
1890                 else
1891                         sp = tsk->thread.ksp;
1892         }
1893
1894         lr = 0;
1895         printk("Call Trace:\n");
1896         do {
1897                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1898                         return;
1899
1900                 stack = (unsigned long *) sp;
1901                 newsp = stack[0];
1902                 ip = stack[STACK_FRAME_LR_SAVE];
1903                 if (!firstframe || ip != lr) {
1904                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1905 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1906                         if ((ip == rth) && curr_frame >= 0) {
1907                                 pr_cont(" (%pS)",
1908                                        (void *)current->ret_stack[curr_frame].ret);
1909                                 curr_frame--;
1910                         }
1911 #endif
1912                         if (firstframe)
1913                                 pr_cont(" (unreliable)");
1914                         pr_cont("\n");
1915                 }
1916                 firstframe = 0;
1917
1918                 /*
1919                  * See if this is an exception frame.
1920                  * We look for the "regshere" marker in the current frame.
1921                  */
1922                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1923                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1924                         struct pt_regs *regs = (struct pt_regs *)
1925                                 (sp + STACK_FRAME_OVERHEAD);
1926                         lr = regs->link;
1927                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1928                                regs->trap, (void *)regs->nip, (void *)lr);
1929                         firstframe = 1;
1930                 }
1931
1932                 sp = newsp;
1933         } while (count++ < kstack_depth_to_print);
1934 }
1935
1936 #ifdef CONFIG_PPC64
1937 /* Called with hard IRQs off */
1938 void notrace __ppc64_runlatch_on(void)
1939 {
1940         struct thread_info *ti = current_thread_info();
1941         unsigned long ctrl;
1942
1943         ctrl = mfspr(SPRN_CTRLF);
1944         ctrl |= CTRL_RUNLATCH;
1945         mtspr(SPRN_CTRLT, ctrl);
1946
1947         ti->local_flags |= _TLF_RUNLATCH;
1948 }
1949
1950 /* Called with hard IRQs off */
1951 void notrace __ppc64_runlatch_off(void)
1952 {
1953         struct thread_info *ti = current_thread_info();
1954         unsigned long ctrl;
1955
1956         ti->local_flags &= ~_TLF_RUNLATCH;
1957
1958         ctrl = mfspr(SPRN_CTRLF);
1959         ctrl &= ~CTRL_RUNLATCH;
1960         mtspr(SPRN_CTRLT, ctrl);
1961 }
1962 #endif /* CONFIG_PPC64 */
1963
1964 unsigned long arch_align_stack(unsigned long sp)
1965 {
1966         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1967                 sp -= get_random_int() & ~PAGE_MASK;
1968         return sp & ~0xf;
1969 }
1970
1971 static inline unsigned long brk_rnd(void)
1972 {
1973         unsigned long rnd = 0;
1974
1975         /* 8MB for 32bit, 1GB for 64bit */
1976         if (is_32bit_task())
1977                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1978         else
1979                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1980
1981         return rnd << PAGE_SHIFT;
1982 }
1983
1984 unsigned long arch_randomize_brk(struct mm_struct *mm)
1985 {
1986         unsigned long base = mm->brk;
1987         unsigned long ret;
1988
1989 #ifdef CONFIG_PPC_STD_MMU_64
1990         /*
1991          * If we are using 1TB segments and we are allowed to randomise
1992          * the heap, we can put it above 1TB so it is backed by a 1TB
1993          * segment. Otherwise the heap will be in the bottom 1TB
1994          * which always uses 256MB segments and this may result in a
1995          * performance penalty. We don't need to worry about radix. For
1996          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1997          */
1998         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1999                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2000 #endif
2001
2002         ret = PAGE_ALIGN(base + brk_rnd());
2003
2004         if (ret < mm->brk)
2005                 return mm->brk;
2006
2007         return ret;
2008 }
2009