1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
12 * Common pmac/prep/chrp pci routines. -- Cort
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/export.h>
21 #include <linux/of_address.h>
22 #include <linux/of_pci.h>
24 #include <linux/shmem_fs.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
30 #include <linux/vgaarb.h>
31 #include <linux/numa.h>
32 #include <linux/msi.h>
34 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
39 #include <asm/machdep.h>
40 #include <asm/ppc-pci.h>
43 #include "../../../drivers/pci/pci.h"
45 /* hose_spinlock protects accesses to the the phb_bitmap. */
46 static DEFINE_SPINLOCK(hose_spinlock);
49 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
50 #define MAX_PHBS 0x10000
53 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
54 * Accesses to this bitmap should be protected by hose_spinlock.
56 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
58 /* ISA Memory physical address */
59 resource_size_t isa_mem_base;
60 EXPORT_SYMBOL(isa_mem_base);
63 static const struct dma_map_ops *pci_dma_ops;
65 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
67 pci_dma_ops = dma_ops;
71 * This function should run under locking protection, specifically
74 static int get_phb_number(struct device_node *dn)
80 * Try fixed PHB numbering first, by checking archs and reading
81 * the respective device-tree properties. Firstly, try reading
82 * standard "linux,pci-domain", then try reading "ibm,opal-phbid"
83 * (only present in powernv OPAL environment), then try device-tree
84 * alias and as the last try to use lower bits of "reg" property.
86 ret = of_get_pci_domain_nr(dn);
92 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
95 ret = of_alias_get_id(dn, "pci");
103 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
108 phb_id = (int)(prop & (MAX_PHBS - 1));
110 /* We need to be sure to not use the same PHB number twice. */
111 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
114 /* If everything fails then fallback to dynamic PHB numbering. */
115 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
116 BUG_ON(phb_id >= MAX_PHBS);
117 set_bit(phb_id, phb_bitmap);
122 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
124 struct pci_controller *phb;
126 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
129 spin_lock(&hose_spinlock);
130 phb->global_number = get_phb_number(dev);
131 list_add_tail(&phb->list_node, &hose_list);
132 spin_unlock(&hose_spinlock);
134 phb->is_dynamic = slab_is_available();
137 int nid = of_node_to_nid(dev);
139 if (nid < 0 || !node_online(nid))
142 PHB_SET_NODE(phb, nid);
147 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
149 void pcibios_free_controller(struct pci_controller *phb)
151 spin_lock(&hose_spinlock);
153 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
154 if (phb->global_number < MAX_PHBS)
155 clear_bit(phb->global_number, phb_bitmap);
157 list_del(&phb->list_node);
158 spin_unlock(&hose_spinlock);
163 EXPORT_SYMBOL_GPL(pcibios_free_controller);
166 * This function is used to call pcibios_free_controller()
167 * in a deferred manner: a callback from the PCI subsystem.
169 * _*DO NOT*_ call pcibios_free_controller() explicitly if
170 * this is used (or it may access an invalid *phb pointer).
172 * The callback occurs when all references to the root bus
173 * are dropped (e.g., child buses/devices and their users).
175 * It's called as .release_fn() of 'struct pci_host_bridge'
176 * which is associated with the 'struct pci_controller.bus'
177 * (root bus) - it expects .release_data to hold a pointer
178 * to 'struct pci_controller'.
180 * In order to use it, register .release_fn()/release_data
183 * pci_set_host_bridge_release(bridge,
184 * pcibios_free_controller_deferred
187 * e.g. in the pcibios_root_bridge_prepare() callback from
188 * pci_create_root_bus().
190 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
192 struct pci_controller *phb = (struct pci_controller *)
193 bridge->release_data;
195 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
197 pcibios_free_controller(phb);
199 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
202 * The function is used to return the minimal alignment
203 * for memory or I/O windows of the associated P2P bridge.
204 * By default, 4KiB alignment for I/O windows and 1MiB for
207 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
210 struct pci_controller *phb = pci_bus_to_host(bus);
212 if (phb->controller_ops.window_alignment)
213 return phb->controller_ops.window_alignment(bus, type);
216 * PCI core will figure out the default
217 * alignment: 4KiB for I/O and 1MiB for
223 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
225 struct pci_controller *hose = pci_bus_to_host(bus);
227 if (hose->controller_ops.setup_bridge)
228 hose->controller_ops.setup_bridge(bus, type);
231 void pcibios_reset_secondary_bus(struct pci_dev *dev)
233 struct pci_controller *phb = pci_bus_to_host(dev->bus);
235 if (phb->controller_ops.reset_secondary_bus) {
236 phb->controller_ops.reset_secondary_bus(dev);
240 pci_reset_secondary_bus(dev);
243 resource_size_t pcibios_default_alignment(void)
245 if (ppc_md.pcibios_default_alignment)
246 return ppc_md.pcibios_default_alignment();
251 #ifdef CONFIG_PCI_IOV
252 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
254 if (ppc_md.pcibios_iov_resource_alignment)
255 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
257 return pci_iov_resource_size(pdev, resno);
260 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
262 if (ppc_md.pcibios_sriov_enable)
263 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
268 int pcibios_sriov_disable(struct pci_dev *pdev)
270 if (ppc_md.pcibios_sriov_disable)
271 return ppc_md.pcibios_sriov_disable(pdev);
276 #endif /* CONFIG_PCI_IOV */
278 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
281 return hose->pci_io_size;
283 return resource_size(&hose->io_resource);
287 int pcibios_vaddr_is_ioport(void __iomem *address)
290 struct pci_controller *hose;
291 resource_size_t size;
293 spin_lock(&hose_spinlock);
294 list_for_each_entry(hose, &hose_list, list_node) {
295 size = pcibios_io_size(hose);
296 if (address >= hose->io_base_virt &&
297 address < (hose->io_base_virt + size)) {
302 spin_unlock(&hose_spinlock);
306 unsigned long pci_address_to_pio(phys_addr_t address)
308 struct pci_controller *hose;
309 resource_size_t size;
310 unsigned long ret = ~0;
312 spin_lock(&hose_spinlock);
313 list_for_each_entry(hose, &hose_list, list_node) {
314 size = pcibios_io_size(hose);
315 if (address >= hose->io_base_phys &&
316 address < (hose->io_base_phys + size)) {
318 (unsigned long)hose->io_base_virt - _IO_BASE;
319 ret = base + (address - hose->io_base_phys);
323 spin_unlock(&hose_spinlock);
327 EXPORT_SYMBOL_GPL(pci_address_to_pio);
330 * Return the domain number for this bus.
332 int pci_domain_nr(struct pci_bus *bus)
334 struct pci_controller *hose = pci_bus_to_host(bus);
336 return hose->global_number;
338 EXPORT_SYMBOL(pci_domain_nr);
340 /* This routine is meant to be used early during boot, when the
341 * PCI bus numbers have not yet been assigned, and you need to
342 * issue PCI config cycles to an OF device.
343 * It could also be used to "fix" RTAS config cycles if you want
344 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
347 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
350 struct pci_controller *hose, *tmp;
351 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
352 if (hose->dn == node)
359 struct pci_controller *pci_find_controller_for_domain(int domain_nr)
361 struct pci_controller *hose;
363 list_for_each_entry(hose, &hose_list, list_node)
364 if (hose->global_number == domain_nr)
370 struct pci_intx_virq {
373 struct list_head list_node;
376 static LIST_HEAD(intx_list);
377 static DEFINE_MUTEX(intx_mutex);
379 static void ppc_pci_intx_release(struct kref *kref)
381 struct pci_intx_virq *vi = container_of(kref, struct pci_intx_virq, kref);
383 list_del(&vi->list_node);
384 irq_dispose_mapping(vi->virq);
388 static int ppc_pci_unmap_irq_line(struct notifier_block *nb,
389 unsigned long action, void *data)
391 struct pci_dev *pdev = to_pci_dev(data);
393 if (action == BUS_NOTIFY_DEL_DEVICE) {
394 struct pci_intx_virq *vi;
396 mutex_lock(&intx_mutex);
397 list_for_each_entry(vi, &intx_list, list_node) {
398 if (vi->virq == pdev->irq) {
399 kref_put(&vi->kref, ppc_pci_intx_release);
403 mutex_unlock(&intx_mutex);
409 static struct notifier_block ppc_pci_unmap_irq_notifier = {
410 .notifier_call = ppc_pci_unmap_irq_line,
413 static int ppc_pci_register_irq_notifier(void)
415 return bus_register_notifier(&pci_bus_type, &ppc_pci_unmap_irq_notifier);
417 arch_initcall(ppc_pci_register_irq_notifier);
420 * Reads the interrupt pin to determine if interrupt is use by card.
421 * If the interrupt is used, then gets the interrupt line from the
422 * openfirmware and sets it in the pci_dev and pci_config line.
424 static int pci_read_irq_line(struct pci_dev *pci_dev)
427 struct pci_intx_virq *vi, *vitmp;
429 /* Preallocate vi as rewind is complex if this fails after mapping */
430 vi = kzalloc(sizeof(struct pci_intx_virq), GFP_KERNEL);
434 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
436 /* Try to get a mapping from the device-tree */
437 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
441 /* If that fails, lets fallback to what is in the config
442 * space and map that through the default controller. We
443 * also set the type to level low since that's what PCI
444 * interrupts are. If your platform does differently, then
445 * either provide a proper interrupt tree or don't use this
448 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
452 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
453 line == 0xff || line == 0) {
456 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
459 virq = irq_create_mapping(NULL, line);
461 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
465 pr_debug(" Failed to map !\n");
469 pr_debug(" Mapped to linux irq %d\n", virq);
473 mutex_lock(&intx_mutex);
474 list_for_each_entry(vitmp, &intx_list, list_node) {
475 if (vitmp->virq == virq) {
476 kref_get(&vitmp->kref);
484 kref_init(&vi->kref);
485 list_add_tail(&vi->list_node, &intx_list);
487 mutex_unlock(&intx_mutex);
496 * Platform support for /proc/bus/pci/X/Y mmap()s.
499 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
501 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
502 resource_size_t ioaddr = pci_resource_start(pdev, bar);
507 /* Convert to an offset within this PCI controller */
508 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
510 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
515 * This one is used by /dev/mem and fbdev who have no clue about the
516 * PCI device, it tries to find the PCI device first and calls the
519 pgprot_t pci_phys_mem_access_prot(struct file *file,
524 struct pci_dev *pdev = NULL;
525 struct resource *found = NULL;
526 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
529 if (page_is_ram(pfn))
532 prot = pgprot_noncached(prot);
533 for_each_pci_dev(pdev) {
534 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
535 struct resource *rp = &pdev->resource[i];
536 int flags = rp->flags;
538 /* Active and same type? */
539 if ((flags & IORESOURCE_MEM) == 0)
541 /* In the range of this resource? */
542 if (offset < (rp->start & PAGE_MASK) ||
552 if (found->flags & IORESOURCE_PREFETCH)
553 prot = pgprot_noncached_wc(prot);
557 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
558 (unsigned long long)offset, pgprot_val(prot));
563 /* This provides legacy IO read access on a bus */
564 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
566 unsigned long offset;
567 struct pci_controller *hose = pci_bus_to_host(bus);
568 struct resource *rp = &hose->io_resource;
571 /* Check if port can be supported by that bus. We only check
572 * the ranges of the PHB though, not the bus itself as the rules
573 * for forwarding legacy cycles down bridges are not our problem
574 * here. So if the host bridge supports it, we do it.
576 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
579 if (!(rp->flags & IORESOURCE_IO))
581 if (offset < rp->start || (offset + size) > rp->end)
583 addr = hose->io_base_virt + port;
587 *((u8 *)val) = in_8(addr);
592 *((u16 *)val) = in_le16(addr);
597 *((u32 *)val) = in_le32(addr);
603 /* This provides legacy IO write access on a bus */
604 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
606 unsigned long offset;
607 struct pci_controller *hose = pci_bus_to_host(bus);
608 struct resource *rp = &hose->io_resource;
611 /* Check if port can be supported by that bus. We only check
612 * the ranges of the PHB though, not the bus itself as the rules
613 * for forwarding legacy cycles down bridges are not our problem
614 * here. So if the host bridge supports it, we do it.
616 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
619 if (!(rp->flags & IORESOURCE_IO))
621 if (offset < rp->start || (offset + size) > rp->end)
623 addr = hose->io_base_virt + port;
625 /* WARNING: The generic code is idiotic. It gets passed a pointer
626 * to what can be a 1, 2 or 4 byte quantity and always reads that
627 * as a u32, which means that we have to correct the location of
628 * the data read within those 32 bits for size 1 and 2
632 out_8(addr, val >> 24);
637 out_le16(addr, val >> 16);
648 /* This provides legacy IO or memory mmap access on a bus */
649 int pci_mmap_legacy_page_range(struct pci_bus *bus,
650 struct vm_area_struct *vma,
651 enum pci_mmap_state mmap_state)
653 struct pci_controller *hose = pci_bus_to_host(bus);
654 resource_size_t offset =
655 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
656 resource_size_t size = vma->vm_end - vma->vm_start;
659 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
660 pci_domain_nr(bus), bus->number,
661 mmap_state == pci_mmap_mem ? "MEM" : "IO",
662 (unsigned long long)offset,
663 (unsigned long long)(offset + size - 1));
665 if (mmap_state == pci_mmap_mem) {
668 * Because X is lame and can fail starting if it gets an error trying
669 * to mmap legacy_mem (instead of just moving on without legacy memory
670 * access) we fake it here by giving it anonymous memory, effectively
671 * behaving just like /dev/zero
673 if ((offset + size) > hose->isa_mem_size) {
675 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
676 current->comm, current->pid, pci_domain_nr(bus), bus->number);
677 if (vma->vm_flags & VM_SHARED)
678 return shmem_zero_setup(vma);
681 offset += hose->isa_mem_phys;
683 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
684 unsigned long roffset = offset + io_offset;
685 rp = &hose->io_resource;
686 if (!(rp->flags & IORESOURCE_IO))
688 if (roffset < rp->start || (roffset + size) > rp->end)
690 offset += hose->io_base_phys;
692 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
694 vma->vm_pgoff = offset >> PAGE_SHIFT;
695 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
696 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
697 vma->vm_end - vma->vm_start,
701 void pci_resource_to_user(const struct pci_dev *dev, int bar,
702 const struct resource *rsrc,
703 resource_size_t *start, resource_size_t *end)
705 struct pci_bus_region region;
707 if (rsrc->flags & IORESOURCE_IO) {
708 pcibios_resource_to_bus(dev->bus, ®ion,
709 (struct resource *) rsrc);
710 *start = region.start;
715 /* We pass a CPU physical address to userland for MMIO instead of a
716 * BAR value because X is lame and expects to be able to use that
717 * to pass to /dev/mem!
719 * That means we may have 64-bit values where some apps only expect
720 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
722 *start = rsrc->start;
727 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
728 * @hose: newly allocated pci_controller to be setup
729 * @dev: device node of the host bridge
730 * @primary: set if primary bus (32 bits only, soon to be deprecated)
732 * This function will parse the "ranges" property of a PCI host bridge device
733 * node and setup the resource mapping of a pci controller based on its
736 * Life would be boring if it wasn't for a few issues that we have to deal
739 * - We can only cope with one IO space range and up to 3 Memory space
740 * ranges. However, some machines (thanks Apple !) tend to split their
741 * space into lots of small contiguous ranges. So we have to coalesce.
743 * - Some busses have IO space not starting at 0, which causes trouble with
744 * the way we do our IO resource renumbering. The code somewhat deals with
745 * it for 64 bits but I would expect problems on 32 bits.
747 * - Some 32 bits platforms such as 4xx can have physical space larger than
748 * 32 bits so we need to use 64 bits values for the parsing
750 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
751 struct device_node *dev, int primary)
754 struct resource *res;
755 struct of_pci_range range;
756 struct of_pci_range_parser parser;
758 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
759 dev, primary ? "(primary)" : "");
761 /* Check for ranges property */
762 if (of_pci_range_parser_init(&parser, dev))
766 for_each_of_pci_range(&parser, &range) {
767 /* If we failed translation or got a zero-sized region
768 * (some FW try to feed us with non sensical zero sized regions
769 * such as power3 which look like some kind of attempt at exposing
770 * the VGA memory hole)
772 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
775 /* Act based on address space type */
777 switch (range.flags & IORESOURCE_TYPE_BITS) {
780 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
781 range.cpu_addr, range.cpu_addr + range.size - 1,
784 /* We support only one IO range */
785 if (hose->pci_io_size) {
787 " \\--> Skipped (too many) !\n");
791 /* On 32 bits, limit I/O space to 16MB */
792 if (range.size > 0x01000000)
793 range.size = 0x01000000;
795 /* 32 bits needs to map IOs here */
796 hose->io_base_virt = ioremap(range.cpu_addr,
799 /* Expect trouble if pci_addr is not 0 */
802 (unsigned long)hose->io_base_virt;
803 #endif /* CONFIG_PPC32 */
804 /* pci_io_size and io_base_phys always represent IO
805 * space starting at 0 so we factor in pci_addr
807 hose->pci_io_size = range.pci_addr + range.size;
808 hose->io_base_phys = range.cpu_addr - range.pci_addr;
811 res = &hose->io_resource;
812 range.cpu_addr = range.pci_addr;
816 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
817 range.cpu_addr, range.cpu_addr + range.size - 1,
819 (range.flags & IORESOURCE_PREFETCH) ?
822 /* We support only 3 memory ranges */
825 " \\--> Skipped (too many) !\n");
828 /* Handles ISA memory hole space here */
829 if (range.pci_addr == 0) {
830 if (primary || isa_mem_base == 0)
831 isa_mem_base = range.cpu_addr;
832 hose->isa_mem_phys = range.cpu_addr;
833 hose->isa_mem_size = range.size;
837 hose->mem_offset[memno] = range.cpu_addr -
839 res = &hose->mem_resources[memno++];
843 res->name = dev->full_name;
844 res->flags = range.flags;
845 res->start = range.cpu_addr;
846 res->end = range.cpu_addr + range.size - 1;
847 res->parent = res->child = res->sibling = NULL;
852 /* Decide whether to display the domain number in /proc */
853 int pci_proc_domain(struct pci_bus *bus)
855 struct pci_controller *hose = pci_bus_to_host(bus);
857 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
859 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
860 return hose->global_number != 0;
864 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
866 if (ppc_md.pcibios_root_bridge_prepare)
867 return ppc_md.pcibios_root_bridge_prepare(bridge);
872 /* This header fixup will do the resource fixup for all devices as they are
873 * probed, but not for bridge ranges
875 static void pcibios_fixup_resources(struct pci_dev *dev)
877 struct pci_controller *hose = pci_bus_to_host(dev->bus);
881 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
889 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
890 struct resource *res = dev->resource + i;
891 struct pci_bus_region reg;
895 /* If we're going to re-assign everything, we mark all resources
896 * as unset (and 0-base them). In addition, we mark BARs starting
897 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
898 * since in that case, we don't want to re-assign anything
900 pcibios_resource_to_bus(dev->bus, ®, res);
901 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
902 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
903 /* Only print message if not re-assigning */
904 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
905 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
906 pci_name(dev), i, res);
907 res->end -= res->start;
909 res->flags |= IORESOURCE_UNSET;
913 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
916 /* Call machine specific resource fixup */
917 if (ppc_md.pcibios_fixup_resources)
918 ppc_md.pcibios_fixup_resources(dev);
920 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
922 /* This function tries to figure out if a bridge resource has been initialized
923 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
924 * things go more smoothly when it gets it right. It should covers cases such
925 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
927 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
928 struct resource *res)
930 struct pci_controller *hose = pci_bus_to_host(bus);
931 struct pci_dev *dev = bus->self;
932 resource_size_t offset;
933 struct pci_bus_region region;
937 /* We don't do anything if PCI_PROBE_ONLY is set */
938 if (pci_has_flag(PCI_PROBE_ONLY))
941 /* Job is a bit different between memory and IO */
942 if (res->flags & IORESOURCE_MEM) {
943 pcibios_resource_to_bus(dev->bus, ®ion, res);
945 /* If the BAR is non-0 then it's probably been initialized */
946 if (region.start != 0)
949 /* The BAR is 0, let's check if memory decoding is enabled on
950 * the bridge. If not, we consider it unassigned
952 pci_read_config_word(dev, PCI_COMMAND, &command);
953 if ((command & PCI_COMMAND_MEMORY) == 0)
956 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
957 * resources covers that starting address (0 then it's good enough for
958 * us for memory space)
960 for (i = 0; i < 3; i++) {
961 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
962 hose->mem_resources[i].start == hose->mem_offset[i])
966 /* Well, it starts at 0 and we know it will collide so we may as
967 * well consider it as unassigned. That covers the Apple case.
971 /* If the BAR is non-0, then we consider it assigned */
972 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
973 if (((res->start - offset) & 0xfffffffful) != 0)
976 /* Here, we are a bit different than memory as typically IO space
977 * starting at low addresses -is- valid. What we do instead if that
978 * we consider as unassigned anything that doesn't have IO enabled
979 * in the PCI command register, and that's it.
981 pci_read_config_word(dev, PCI_COMMAND, &command);
982 if (command & PCI_COMMAND_IO)
985 /* It's starting at 0 and IO is disabled in the bridge, consider
992 /* Fixup resources of a PCI<->PCI bridge */
993 static void pcibios_fixup_bridge(struct pci_bus *bus)
995 struct resource *res;
998 struct pci_dev *dev = bus->self;
1000 pci_bus_for_each_resource(bus, res, i) {
1001 if (!res || !res->flags)
1003 if (i >= 3 && bus->self->transparent)
1006 /* If we're going to reassign everything, we can
1007 * shrink the P2P resource to have size as being
1008 * of 0 in order to save space.
1010 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1011 res->flags |= IORESOURCE_UNSET;
1017 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
1019 /* Try to detect uninitialized P2P bridge resources,
1020 * and clear them out so they get re-assigned later
1022 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1024 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1029 void pcibios_setup_bus_self(struct pci_bus *bus)
1031 struct pci_controller *phb;
1033 /* Fix up the bus resources for P2P bridges */
1034 if (bus->self != NULL)
1035 pcibios_fixup_bridge(bus);
1037 /* Platform specific bus fixups. This is currently only used
1038 * by fsl_pci and I'm hoping to get rid of it at some point
1040 if (ppc_md.pcibios_fixup_bus)
1041 ppc_md.pcibios_fixup_bus(bus);
1043 /* Setup bus DMA mappings */
1044 phb = pci_bus_to_host(bus);
1045 if (phb->controller_ops.dma_bus_setup)
1046 phb->controller_ops.dma_bus_setup(bus);
1049 void pcibios_bus_add_device(struct pci_dev *dev)
1051 struct pci_controller *phb;
1052 /* Fixup NUMA node as it may not be setup yet by the generic
1053 * code and is needed by the DMA init
1055 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1057 /* Hook up default DMA ops */
1058 set_dma_ops(&dev->dev, pci_dma_ops);
1059 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
1061 /* Additional platform DMA/iommu setup */
1062 phb = pci_bus_to_host(dev->bus);
1063 if (phb->controller_ops.dma_dev_setup)
1064 phb->controller_ops.dma_dev_setup(dev);
1066 /* Read default IRQs and fixup if necessary */
1067 pci_read_irq_line(dev);
1068 if (ppc_md.pci_irq_fixup)
1069 ppc_md.pci_irq_fixup(dev);
1071 if (ppc_md.pcibios_bus_add_device)
1072 ppc_md.pcibios_bus_add_device(dev);
1075 int pcibios_add_device(struct pci_dev *dev)
1077 struct irq_domain *d;
1079 #ifdef CONFIG_PCI_IOV
1080 if (ppc_md.pcibios_fixup_sriov)
1081 ppc_md.pcibios_fixup_sriov(dev);
1082 #endif /* CONFIG_PCI_IOV */
1084 d = dev_get_msi_domain(&dev->bus->dev);
1086 dev_set_msi_domain(&dev->dev, d);
1090 void pcibios_set_master(struct pci_dev *dev)
1092 /* No special bus mastering setup handling */
1095 void pcibios_fixup_bus(struct pci_bus *bus)
1097 /* When called from the generic PCI probe, read PCI<->PCI bridge
1098 * bases. This is -not- called when generating the PCI tree from
1099 * the OF device-tree.
1101 pci_read_bridge_bases(bus);
1103 /* Now fixup the bus bus */
1104 pcibios_setup_bus_self(bus);
1106 EXPORT_SYMBOL(pcibios_fixup_bus);
1108 static int skip_isa_ioresource_align(struct pci_dev *dev)
1110 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1111 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1117 * We need to avoid collisions with `mirrored' VGA ports
1118 * and other strange ISA hardware, so we always want the
1119 * addresses to be allocated in the 0x000-0x0ff region
1122 * Why? Because some silly external IO cards only decode
1123 * the low 10 bits of the IO address. The 0x00-0xff region
1124 * is reserved for motherboard devices that decode all 16
1125 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1126 * but we want to try to avoid allocating at 0x2900-0x2bff
1127 * which might have be mirrored at 0x0100-0x03ff..
1129 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1130 resource_size_t size, resource_size_t align)
1132 struct pci_dev *dev = data;
1133 resource_size_t start = res->start;
1135 if (res->flags & IORESOURCE_IO) {
1136 if (skip_isa_ioresource_align(dev))
1139 start = (start + 0x3ff) & ~0x3ff;
1144 EXPORT_SYMBOL(pcibios_align_resource);
1147 * Reparent resource children of pr that conflict with res
1148 * under res, and make res replace those children.
1150 static int reparent_resources(struct resource *parent,
1151 struct resource *res)
1153 struct resource *p, **pp;
1154 struct resource **firstpp = NULL;
1156 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1157 if (p->end < res->start)
1159 if (res->end < p->start)
1161 if (p->start < res->start || p->end > res->end)
1162 return -1; /* not completely contained */
1163 if (firstpp == NULL)
1166 if (firstpp == NULL)
1167 return -1; /* didn't find any conflicting entries? */
1168 res->parent = parent;
1169 res->child = *firstpp;
1173 for (p = res->child; p != NULL; p = p->sibling) {
1175 pr_debug("PCI: Reparented %s %pR under %s\n",
1176 p->name, p, res->name);
1182 * Handle resources of PCI devices. If the world were perfect, we could
1183 * just allocate all the resource regions and do nothing more. It isn't.
1184 * On the other hand, we cannot just re-allocate all devices, as it would
1185 * require us to know lots of host bridge internals. So we attempt to
1186 * keep as much of the original configuration as possible, but tweak it
1187 * when it's found to be wrong.
1189 * Known BIOS problems we have to work around:
1190 * - I/O or memory regions not configured
1191 * - regions configured, but not enabled in the command register
1192 * - bogus I/O addresses above 64K used
1193 * - expansion ROMs left enabled (this may sound harmless, but given
1194 * the fact the PCI specs explicitly allow address decoders to be
1195 * shared between expansion ROMs and other resource regions, it's
1196 * at least dangerous)
1199 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1200 * This gives us fixed barriers on where we can allocate.
1201 * (2) Allocate resources for all enabled devices. If there is
1202 * a collision, just mark the resource as unallocated. Also
1203 * disable expansion ROMs during this step.
1204 * (3) Try to allocate resources for disabled devices. If the
1205 * resources were assigned correctly, everything goes well,
1206 * if they weren't, they won't disturb allocation of other
1208 * (4) Assign new addresses to resources which were either
1209 * not configured at all or misconfigured. If explicitly
1210 * requested by the user, configure expansion ROM address
1214 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1218 struct resource *res, *pr;
1220 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1221 pci_domain_nr(bus), bus->number);
1223 pci_bus_for_each_resource(bus, res, i) {
1224 if (!res || !res->flags || res->start > res->end || res->parent)
1227 /* If the resource was left unset at this point, we clear it */
1228 if (res->flags & IORESOURCE_UNSET)
1229 goto clear_resource;
1231 if (bus->parent == NULL)
1232 pr = (res->flags & IORESOURCE_IO) ?
1233 &ioport_resource : &iomem_resource;
1235 pr = pci_find_parent_resource(bus->self, res);
1237 /* this happens when the generic PCI
1238 * code (wrongly) decides that this
1239 * bridge is transparent -- paulus
1245 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1246 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1247 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1249 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1250 struct pci_dev *dev = bus->self;
1252 if (request_resource(pr, res) == 0)
1255 * Must be a conflict with an existing entry.
1256 * Move that entry (or entries) under the
1257 * bridge resource and try again.
1259 if (reparent_resources(pr, res) == 0)
1262 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1263 pci_claim_bridge_resource(dev,
1264 i + PCI_BRIDGE_RESOURCES) == 0)
1267 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1270 /* The resource might be figured out when doing
1271 * reassignment based on the resources required
1272 * by the downstream PCI devices. Here we set
1273 * the size of the resource to be 0 in order to
1281 list_for_each_entry(b, &bus->children, node)
1282 pcibios_allocate_bus_resources(b);
1285 static inline void alloc_resource(struct pci_dev *dev, int idx)
1287 struct resource *pr, *r = &dev->resource[idx];
1289 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1290 pci_name(dev), idx, r);
1292 pr = pci_find_parent_resource(dev, r);
1293 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1294 request_resource(pr, r) < 0) {
1295 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1296 " of device %s, will remap\n", idx, pci_name(dev));
1298 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1299 /* We'll assign a new address later */
1300 r->flags |= IORESOURCE_UNSET;
1306 static void __init pcibios_allocate_resources(int pass)
1308 struct pci_dev *dev = NULL;
1313 for_each_pci_dev(dev) {
1314 pci_read_config_word(dev, PCI_COMMAND, &command);
1315 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1316 r = &dev->resource[idx];
1317 if (r->parent) /* Already allocated */
1319 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1320 continue; /* Not assigned at all */
1321 /* We only allocate ROMs on pass 1 just in case they
1322 * have been screwed up by firmware
1324 if (idx == PCI_ROM_RESOURCE )
1326 if (r->flags & IORESOURCE_IO)
1327 disabled = !(command & PCI_COMMAND_IO);
1329 disabled = !(command & PCI_COMMAND_MEMORY);
1330 if (pass == disabled)
1331 alloc_resource(dev, idx);
1335 r = &dev->resource[PCI_ROM_RESOURCE];
1337 /* Turn the ROM off, leave the resource region,
1338 * but keep it unregistered.
1341 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1342 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1343 pr_debug("PCI: Switching off ROM of %s\n",
1345 r->flags &= ~IORESOURCE_ROM_ENABLE;
1346 pci_write_config_dword(dev, dev->rom_base_reg,
1347 reg & ~PCI_ROM_ADDRESS_ENABLE);
1353 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1355 struct pci_controller *hose = pci_bus_to_host(bus);
1356 resource_size_t offset;
1357 struct resource *res, *pres;
1360 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1363 if (!(hose->io_resource.flags & IORESOURCE_IO))
1365 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1366 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1367 BUG_ON(res == NULL);
1368 res->name = "Legacy IO";
1369 res->flags = IORESOURCE_IO;
1370 res->start = offset;
1371 res->end = (offset + 0xfff) & 0xfffffffful;
1372 pr_debug("Candidate legacy IO: %pR\n", res);
1373 if (request_resource(&hose->io_resource, res)) {
1375 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1376 pci_domain_nr(bus), bus->number, res);
1381 /* Check for memory */
1382 for (i = 0; i < 3; i++) {
1383 pres = &hose->mem_resources[i];
1384 offset = hose->mem_offset[i];
1385 if (!(pres->flags & IORESOURCE_MEM))
1387 pr_debug("hose mem res: %pR\n", pres);
1388 if ((pres->start - offset) <= 0xa0000 &&
1389 (pres->end - offset) >= 0xbffff)
1394 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1395 BUG_ON(res == NULL);
1396 res->name = "Legacy VGA memory";
1397 res->flags = IORESOURCE_MEM;
1398 res->start = 0xa0000 + offset;
1399 res->end = 0xbffff + offset;
1400 pr_debug("Candidate VGA memory: %pR\n", res);
1401 if (request_resource(pres, res)) {
1403 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1404 pci_domain_nr(bus), bus->number, res);
1409 void __init pcibios_resource_survey(void)
1413 /* Allocate and assign resources */
1414 list_for_each_entry(b, &pci_root_buses, node)
1415 pcibios_allocate_bus_resources(b);
1416 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1417 pcibios_allocate_resources(0);
1418 pcibios_allocate_resources(1);
1421 /* Before we start assigning unassigned resource, we try to reserve
1422 * the low IO area and the VGA memory area if they intersect the
1423 * bus available resources to avoid allocating things on top of them
1425 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1426 list_for_each_entry(b, &pci_root_buses, node)
1427 pcibios_reserve_legacy_regions(b);
1430 /* Now, if the platform didn't decide to blindly trust the firmware,
1431 * we proceed to assigning things that were left unassigned
1433 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1434 pr_debug("PCI: Assigning unassigned resources...\n");
1435 pci_assign_unassigned_resources();
1439 /* This is used by the PCI hotplug driver to allocate resource
1440 * of newly plugged busses. We can try to consolidate with the
1441 * rest of the code later, for now, keep it as-is as our main
1442 * resource allocation function doesn't deal with sub-trees yet.
1444 void pcibios_claim_one_bus(struct pci_bus *bus)
1446 struct pci_dev *dev;
1447 struct pci_bus *child_bus;
1449 list_for_each_entry(dev, &bus->devices, bus_list) {
1452 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1453 struct resource *r = &dev->resource[i];
1455 if (r->parent || !r->start || !r->flags)
1458 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1459 pci_name(dev), i, r);
1461 if (pci_claim_resource(dev, i) == 0)
1464 pci_claim_bridge_resource(dev, i);
1468 list_for_each_entry(child_bus, &bus->children, node)
1469 pcibios_claim_one_bus(child_bus);
1471 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1474 /* pcibios_finish_adding_to_bus
1476 * This is to be called by the hotplug code after devices have been
1477 * added to a bus, this include calling it for a PHB that is just
1480 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1482 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1483 pci_domain_nr(bus), bus->number);
1485 /* Allocate bus and devices resources */
1486 pcibios_allocate_bus_resources(bus);
1487 pcibios_claim_one_bus(bus);
1488 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1490 pci_assign_unassigned_bridge_resources(bus->self);
1492 pci_assign_unassigned_bus_resources(bus);
1495 /* Add new devices to global lists. Register in proc, sysfs. */
1496 pci_bus_add_devices(bus);
1498 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1500 int pcibios_enable_device(struct pci_dev *dev, int mask)
1502 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1504 if (phb->controller_ops.enable_device_hook)
1505 if (!phb->controller_ops.enable_device_hook(dev))
1508 return pci_enable_resources(dev, mask);
1511 void pcibios_disable_device(struct pci_dev *dev)
1513 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1515 if (phb->controller_ops.disable_device)
1516 phb->controller_ops.disable_device(dev);
1519 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1521 return (unsigned long) hose->io_base_virt - _IO_BASE;
1524 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1525 struct list_head *resources)
1527 struct resource *res;
1528 resource_size_t offset;
1531 /* Hookup PHB IO resource */
1532 res = &hose->io_resource;
1535 pr_debug("PCI: I/O resource not set for host"
1536 " bridge %pOF (domain %d)\n",
1537 hose->dn, hose->global_number);
1539 offset = pcibios_io_space_offset(hose);
1541 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1542 res, (unsigned long long)offset);
1543 pci_add_resource_offset(resources, res, offset);
1546 /* Hookup PHB Memory resources */
1547 for (i = 0; i < 3; ++i) {
1548 res = &hose->mem_resources[i];
1552 offset = hose->mem_offset[i];
1553 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1554 res, (unsigned long long)offset);
1556 pci_add_resource_offset(resources, res, offset);
1561 * Null PCI config access functions, for the case when we can't
1564 #define NULL_PCI_OP(rw, size, type) \
1566 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1568 return PCIBIOS_DEVICE_NOT_FOUND; \
1572 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1575 return PCIBIOS_DEVICE_NOT_FOUND;
1579 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1582 return PCIBIOS_DEVICE_NOT_FOUND;
1585 static struct pci_ops null_pci_ops =
1587 .read = null_read_config,
1588 .write = null_write_config,
1592 * These functions are used early on before PCI scanning is done
1593 * and all of the pci_dev and pci_bus structures have been created.
1595 static struct pci_bus *
1596 fake_pci_bus(struct pci_controller *hose, int busnr)
1598 static struct pci_bus bus;
1601 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1605 bus.ops = hose? hose->ops: &null_pci_ops;
1609 #define EARLY_PCI_OP(rw, size, type) \
1610 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1611 int devfn, int offset, type value) \
1613 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1614 devfn, offset, value); \
1617 EARLY_PCI_OP(read, byte, u8 *)
1618 EARLY_PCI_OP(read, word, u16 *)
1619 EARLY_PCI_OP(read, dword, u32 *)
1620 EARLY_PCI_OP(write, byte, u8)
1621 EARLY_PCI_OP(write, word, u16)
1622 EARLY_PCI_OP(write, dword, u32)
1624 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1627 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1630 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1632 struct pci_controller *hose = bus->sysdata;
1634 return of_node_get(hose->dn);
1638 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1639 * @hose: Pointer to the PCI host controller instance structure
1641 void pcibios_scan_phb(struct pci_controller *hose)
1643 LIST_HEAD(resources);
1644 struct pci_bus *bus;
1645 struct device_node *node = hose->dn;
1648 pr_debug("PCI: Scanning PHB %pOF\n", node);
1650 /* Get some IO space for the new PHB */
1651 pcibios_setup_phb_io_space(hose);
1653 /* Wire up PHB bus resources */
1654 pcibios_setup_phb_resources(hose, &resources);
1656 hose->busn.start = hose->first_busno;
1657 hose->busn.end = hose->last_busno;
1658 hose->busn.flags = IORESOURCE_BUS;
1659 pci_add_resource(&resources, &hose->busn);
1661 /* Create an empty bus for the toplevel */
1662 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1663 hose->ops, hose, &resources);
1665 pr_err("Failed to create bus for PCI domain %04x\n",
1666 hose->global_number);
1667 pci_free_resource_list(&resources);
1672 /* Get probe mode and perform scan */
1673 mode = PCI_PROBE_NORMAL;
1674 if (node && hose->controller_ops.probe_mode)
1675 mode = hose->controller_ops.probe_mode(bus);
1676 pr_debug(" probe mode: %d\n", mode);
1677 if (mode == PCI_PROBE_DEVTREE)
1678 of_scan_bus(node, bus);
1680 if (mode == PCI_PROBE_NORMAL) {
1681 pci_bus_update_busn_res_end(bus, 255);
1682 hose->last_busno = pci_scan_child_bus(bus);
1683 pci_bus_update_busn_res_end(bus, hose->last_busno);
1686 /* Platform gets a chance to do some global fixups before
1687 * we proceed to resource allocation
1689 if (ppc_md.pcibios_fixup_phb)
1690 ppc_md.pcibios_fixup_phb(hose);
1692 /* Configure PCI Express settings */
1693 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1694 struct pci_bus *child;
1695 list_for_each_entry(child, &bus->children, node)
1696 pcie_bus_configure_settings(child);
1699 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1701 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1703 int i, class = dev->class >> 8;
1704 /* When configured as agent, programing interface = 1 */
1705 int prog_if = dev->class & 0xf;
1707 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1708 class == PCI_CLASS_BRIDGE_OTHER) &&
1709 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1711 (dev->bus->parent == NULL)) {
1712 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1713 dev->resource[i].start = 0;
1714 dev->resource[i].end = 0;
1715 dev->resource[i].flags = 0;
1719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1723 static int __init discover_phbs(void)
1725 if (ppc_md.discover_phbs)
1726 ppc_md.discover_phbs();
1730 core_initcall(discover_phbs);