2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 /* hose_spinlock protects accesses to the the phb_bitmap. */
45 static DEFINE_SPINLOCK(hose_spinlock);
48 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
49 #define MAX_PHBS 0x10000
52 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
53 * Accesses to this bitmap should be protected by hose_spinlock.
55 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
57 /* ISA Memory physical address */
58 resource_size_t isa_mem_base;
61 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
63 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
65 pci_dma_ops = dma_ops;
68 struct dma_map_ops *get_pci_dma_ops(void)
72 EXPORT_SYMBOL(get_pci_dma_ops);
75 * This function should run under locking protection, specifically
78 static int get_phb_number(struct device_node *dn)
84 * Try fixed PHB numbering first, by checking archs and reading
85 * the respective device-tree properties. Firstly, try powernv by
86 * reading "ibm,opal-phbid", only present in OPAL environment.
88 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
90 ret = of_property_read_u32_index(dn, "reg", 1, (u32 *)&prop);
93 phb_id = (int)(prop & (MAX_PHBS - 1));
95 /* We need to be sure to not use the same PHB number twice. */
96 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
100 * If not pseries nor powernv, or if fixed PHB numbering tried to add
101 * the same PHB number twice, then fallback to dynamic PHB numbering.
103 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
104 BUG_ON(phb_id >= MAX_PHBS);
105 set_bit(phb_id, phb_bitmap);
110 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
112 struct pci_controller *phb;
114 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
117 spin_lock(&hose_spinlock);
118 phb->global_number = get_phb_number(dev);
119 list_add_tail(&phb->list_node, &hose_list);
120 spin_unlock(&hose_spinlock);
122 phb->is_dynamic = slab_is_available();
125 int nid = of_node_to_nid(dev);
127 if (nid < 0 || !node_online(nid))
130 PHB_SET_NODE(phb, nid);
135 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
137 void pcibios_free_controller(struct pci_controller *phb)
139 spin_lock(&hose_spinlock);
141 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
142 if (phb->global_number < MAX_PHBS)
143 clear_bit(phb->global_number, phb_bitmap);
145 list_del(&phb->list_node);
146 spin_unlock(&hose_spinlock);
151 EXPORT_SYMBOL_GPL(pcibios_free_controller);
154 * The function is used to return the minimal alignment
155 * for memory or I/O windows of the associated P2P bridge.
156 * By default, 4KiB alignment for I/O windows and 1MiB for
159 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
162 struct pci_controller *phb = pci_bus_to_host(bus);
164 if (phb->controller_ops.window_alignment)
165 return phb->controller_ops.window_alignment(bus, type);
168 * PCI core will figure out the default
169 * alignment: 4KiB for I/O and 1MiB for
175 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
177 struct pci_controller *hose = pci_bus_to_host(bus);
179 if (hose->controller_ops.setup_bridge)
180 hose->controller_ops.setup_bridge(bus, type);
183 void pcibios_reset_secondary_bus(struct pci_dev *dev)
185 struct pci_controller *phb = pci_bus_to_host(dev->bus);
187 if (phb->controller_ops.reset_secondary_bus) {
188 phb->controller_ops.reset_secondary_bus(dev);
192 pci_reset_secondary_bus(dev);
195 #ifdef CONFIG_PCI_IOV
196 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
198 if (ppc_md.pcibios_iov_resource_alignment)
199 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
201 return pci_iov_resource_size(pdev, resno);
203 #endif /* CONFIG_PCI_IOV */
205 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
208 return hose->pci_io_size;
210 return resource_size(&hose->io_resource);
214 int pcibios_vaddr_is_ioport(void __iomem *address)
217 struct pci_controller *hose;
218 resource_size_t size;
220 spin_lock(&hose_spinlock);
221 list_for_each_entry(hose, &hose_list, list_node) {
222 size = pcibios_io_size(hose);
223 if (address >= hose->io_base_virt &&
224 address < (hose->io_base_virt + size)) {
229 spin_unlock(&hose_spinlock);
233 unsigned long pci_address_to_pio(phys_addr_t address)
235 struct pci_controller *hose;
236 resource_size_t size;
237 unsigned long ret = ~0;
239 spin_lock(&hose_spinlock);
240 list_for_each_entry(hose, &hose_list, list_node) {
241 size = pcibios_io_size(hose);
242 if (address >= hose->io_base_phys &&
243 address < (hose->io_base_phys + size)) {
245 (unsigned long)hose->io_base_virt - _IO_BASE;
246 ret = base + (address - hose->io_base_phys);
250 spin_unlock(&hose_spinlock);
254 EXPORT_SYMBOL_GPL(pci_address_to_pio);
257 * Return the domain number for this bus.
259 int pci_domain_nr(struct pci_bus *bus)
261 struct pci_controller *hose = pci_bus_to_host(bus);
263 return hose->global_number;
265 EXPORT_SYMBOL(pci_domain_nr);
267 /* This routine is meant to be used early during boot, when the
268 * PCI bus numbers have not yet been assigned, and you need to
269 * issue PCI config cycles to an OF device.
270 * It could also be used to "fix" RTAS config cycles if you want
271 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
274 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
277 struct pci_controller *hose, *tmp;
278 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
279 if (hose->dn == node)
287 * Reads the interrupt pin to determine if interrupt is use by card.
288 * If the interrupt is used, then gets the interrupt line from the
289 * openfirmware and sets it in the pci_dev and pci_config line.
291 static int pci_read_irq_line(struct pci_dev *pci_dev)
293 struct of_phandle_args oirq;
296 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
299 memset(&oirq, 0xff, sizeof(oirq));
301 /* Try to get a mapping from the device-tree */
302 if (of_irq_parse_pci(pci_dev, &oirq)) {
305 /* If that fails, lets fallback to what is in the config
306 * space and map that through the default controller. We
307 * also set the type to level low since that's what PCI
308 * interrupts are. If your platform does differently, then
309 * either provide a proper interrupt tree or don't use this
312 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
316 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
317 line == 0xff || line == 0) {
320 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
323 virq = irq_create_mapping(NULL, line);
325 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
327 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
328 oirq.args_count, oirq.args[0], oirq.args[1],
329 of_node_full_name(oirq.np));
331 virq = irq_create_of_mapping(&oirq);
334 pr_debug(" Failed to map !\n");
338 pr_debug(" Mapped to linux irq %d\n", virq);
346 * Platform support for /proc/bus/pci/X/Y mmap()s,
347 * modelled on the sparc64 implementation by Dave Miller.
352 * Adjust vm_pgoff of VMA such that it is the physical page offset
353 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
355 * Basically, the user finds the base address for his device which he wishes
356 * to mmap. They read the 32-bit value from the config space base register,
357 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
358 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
360 * Returns negative error code on failure, zero on success.
362 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
363 resource_size_t *offset,
364 enum pci_mmap_state mmap_state)
366 struct pci_controller *hose = pci_bus_to_host(dev->bus);
367 unsigned long io_offset = 0;
371 return NULL; /* should never happen */
373 /* If memory, add on the PCI bridge address offset */
374 if (mmap_state == pci_mmap_mem) {
375 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
376 *offset += hose->pci_mem_offset;
378 res_bit = IORESOURCE_MEM;
380 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
381 *offset += io_offset;
382 res_bit = IORESOURCE_IO;
386 * Check that the offset requested corresponds to one of the
387 * resources of the device.
389 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
390 struct resource *rp = &dev->resource[i];
391 int flags = rp->flags;
393 /* treat ROM as memory (should be already) */
394 if (i == PCI_ROM_RESOURCE)
395 flags |= IORESOURCE_MEM;
397 /* Active and same type? */
398 if ((flags & res_bit) == 0)
401 /* In the range of this resource? */
402 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
405 /* found it! construct the final physical address */
406 if (mmap_state == pci_mmap_io)
407 *offset += hose->io_base_phys - io_offset;
415 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
418 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
420 enum pci_mmap_state mmap_state,
424 /* Write combine is always 0 on non-memory space mappings. On
425 * memory space, if the user didn't pass 1, we check for a
426 * "prefetchable" resource. This is a bit hackish, but we use
427 * this to workaround the inability of /sysfs to provide a write
430 if (mmap_state != pci_mmap_mem)
432 else if (write_combine == 0) {
433 if (rp->flags & IORESOURCE_PREFETCH)
437 /* XXX would be nice to have a way to ask for write-through */
439 return pgprot_noncached_wc(protection);
441 return pgprot_noncached(protection);
445 * This one is used by /dev/mem and fbdev who have no clue about the
446 * PCI device, it tries to find the PCI device first and calls the
449 pgprot_t pci_phys_mem_access_prot(struct file *file,
454 struct pci_dev *pdev = NULL;
455 struct resource *found = NULL;
456 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
459 if (page_is_ram(pfn))
462 prot = pgprot_noncached(prot);
463 for_each_pci_dev(pdev) {
464 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
465 struct resource *rp = &pdev->resource[i];
466 int flags = rp->flags;
468 /* Active and same type? */
469 if ((flags & IORESOURCE_MEM) == 0)
471 /* In the range of this resource? */
472 if (offset < (rp->start & PAGE_MASK) ||
482 if (found->flags & IORESOURCE_PREFETCH)
483 prot = pgprot_noncached_wc(prot);
487 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
488 (unsigned long long)offset, pgprot_val(prot));
495 * Perform the actual remap of the pages for a PCI device mapping, as
496 * appropriate for this architecture. The region in the process to map
497 * is described by vm_start and vm_end members of VMA, the base physical
498 * address is found in vm_pgoff.
499 * The pci device structure is provided so that architectures may make mapping
500 * decisions on a per-device or per-bus basis.
502 * Returns a negative error code on failure, zero on success.
504 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
505 enum pci_mmap_state mmap_state, int write_combine)
507 resource_size_t offset =
508 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
512 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
516 vma->vm_pgoff = offset >> PAGE_SHIFT;
517 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
519 mmap_state, write_combine);
521 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
522 vma->vm_end - vma->vm_start, vma->vm_page_prot);
527 /* This provides legacy IO read access on a bus */
528 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
530 unsigned long offset;
531 struct pci_controller *hose = pci_bus_to_host(bus);
532 struct resource *rp = &hose->io_resource;
535 /* Check if port can be supported by that bus. We only check
536 * the ranges of the PHB though, not the bus itself as the rules
537 * for forwarding legacy cycles down bridges are not our problem
538 * here. So if the host bridge supports it, we do it.
540 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
543 if (!(rp->flags & IORESOURCE_IO))
545 if (offset < rp->start || (offset + size) > rp->end)
547 addr = hose->io_base_virt + port;
551 *((u8 *)val) = in_8(addr);
556 *((u16 *)val) = in_le16(addr);
561 *((u32 *)val) = in_le32(addr);
567 /* This provides legacy IO write access on a bus */
568 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
570 unsigned long offset;
571 struct pci_controller *hose = pci_bus_to_host(bus);
572 struct resource *rp = &hose->io_resource;
575 /* Check if port can be supported by that bus. We only check
576 * the ranges of the PHB though, not the bus itself as the rules
577 * for forwarding legacy cycles down bridges are not our problem
578 * here. So if the host bridge supports it, we do it.
580 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
583 if (!(rp->flags & IORESOURCE_IO))
585 if (offset < rp->start || (offset + size) > rp->end)
587 addr = hose->io_base_virt + port;
589 /* WARNING: The generic code is idiotic. It gets passed a pointer
590 * to what can be a 1, 2 or 4 byte quantity and always reads that
591 * as a u32, which means that we have to correct the location of
592 * the data read within those 32 bits for size 1 and 2
596 out_8(addr, val >> 24);
601 out_le16(addr, val >> 16);
612 /* This provides legacy IO or memory mmap access on a bus */
613 int pci_mmap_legacy_page_range(struct pci_bus *bus,
614 struct vm_area_struct *vma,
615 enum pci_mmap_state mmap_state)
617 struct pci_controller *hose = pci_bus_to_host(bus);
618 resource_size_t offset =
619 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
620 resource_size_t size = vma->vm_end - vma->vm_start;
623 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
624 pci_domain_nr(bus), bus->number,
625 mmap_state == pci_mmap_mem ? "MEM" : "IO",
626 (unsigned long long)offset,
627 (unsigned long long)(offset + size - 1));
629 if (mmap_state == pci_mmap_mem) {
632 * Because X is lame and can fail starting if it gets an error trying
633 * to mmap legacy_mem (instead of just moving on without legacy memory
634 * access) we fake it here by giving it anonymous memory, effectively
635 * behaving just like /dev/zero
637 if ((offset + size) > hose->isa_mem_size) {
639 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
640 current->comm, current->pid, pci_domain_nr(bus), bus->number);
641 if (vma->vm_flags & VM_SHARED)
642 return shmem_zero_setup(vma);
645 offset += hose->isa_mem_phys;
647 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
648 unsigned long roffset = offset + io_offset;
649 rp = &hose->io_resource;
650 if (!(rp->flags & IORESOURCE_IO))
652 if (roffset < rp->start || (roffset + size) > rp->end)
654 offset += hose->io_base_phys;
656 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
658 vma->vm_pgoff = offset >> PAGE_SHIFT;
659 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
660 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
661 vma->vm_end - vma->vm_start,
665 void pci_resource_to_user(const struct pci_dev *dev, int bar,
666 const struct resource *rsrc,
667 resource_size_t *start, resource_size_t *end)
669 struct pci_controller *hose = pci_bus_to_host(dev->bus);
670 resource_size_t offset = 0;
675 if (rsrc->flags & IORESOURCE_IO)
676 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
678 /* We pass a fully fixed up address to userland for MMIO instead of
679 * a BAR value because X is lame and expects to be able to use that
680 * to pass to /dev/mem !
682 * That means that we'll have potentially 64 bits values where some
683 * userland apps only expect 32 (like X itself since it thinks only
684 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
687 * Hopefully, the sysfs insterface is immune to that gunk. Once X
688 * has been fixed (and the fix spread enough), we can re-enable the
689 * 2 lines below and pass down a BAR value to userland. In that case
690 * we'll also have to re-enable the matching code in
691 * __pci_mmap_make_offset().
696 else if (rsrc->flags & IORESOURCE_MEM)
697 offset = hose->pci_mem_offset;
700 *start = rsrc->start - offset;
701 *end = rsrc->end - offset;
705 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
706 * @hose: newly allocated pci_controller to be setup
707 * @dev: device node of the host bridge
708 * @primary: set if primary bus (32 bits only, soon to be deprecated)
710 * This function will parse the "ranges" property of a PCI host bridge device
711 * node and setup the resource mapping of a pci controller based on its
714 * Life would be boring if it wasn't for a few issues that we have to deal
717 * - We can only cope with one IO space range and up to 3 Memory space
718 * ranges. However, some machines (thanks Apple !) tend to split their
719 * space into lots of small contiguous ranges. So we have to coalesce.
721 * - Some busses have IO space not starting at 0, which causes trouble with
722 * the way we do our IO resource renumbering. The code somewhat deals with
723 * it for 64 bits but I would expect problems on 32 bits.
725 * - Some 32 bits platforms such as 4xx can have physical space larger than
726 * 32 bits so we need to use 64 bits values for the parsing
728 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
729 struct device_node *dev, int primary)
732 struct resource *res;
733 struct of_pci_range range;
734 struct of_pci_range_parser parser;
736 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
737 dev->full_name, primary ? "(primary)" : "");
739 /* Check for ranges property */
740 if (of_pci_range_parser_init(&parser, dev))
744 for_each_of_pci_range(&parser, &range) {
745 /* If we failed translation or got a zero-sized region
746 * (some FW try to feed us with non sensical zero sized regions
747 * such as power3 which look like some kind of attempt at exposing
748 * the VGA memory hole)
750 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
753 /* Act based on address space type */
755 switch (range.flags & IORESOURCE_TYPE_BITS) {
758 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
759 range.cpu_addr, range.cpu_addr + range.size - 1,
762 /* We support only one IO range */
763 if (hose->pci_io_size) {
765 " \\--> Skipped (too many) !\n");
769 /* On 32 bits, limit I/O space to 16MB */
770 if (range.size > 0x01000000)
771 range.size = 0x01000000;
773 /* 32 bits needs to map IOs here */
774 hose->io_base_virt = ioremap(range.cpu_addr,
777 /* Expect trouble if pci_addr is not 0 */
780 (unsigned long)hose->io_base_virt;
781 #endif /* CONFIG_PPC32 */
782 /* pci_io_size and io_base_phys always represent IO
783 * space starting at 0 so we factor in pci_addr
785 hose->pci_io_size = range.pci_addr + range.size;
786 hose->io_base_phys = range.cpu_addr - range.pci_addr;
789 res = &hose->io_resource;
790 range.cpu_addr = range.pci_addr;
794 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
795 range.cpu_addr, range.cpu_addr + range.size - 1,
797 (range.pci_space & 0x40000000) ?
800 /* We support only 3 memory ranges */
803 " \\--> Skipped (too many) !\n");
806 /* Handles ISA memory hole space here */
807 if (range.pci_addr == 0) {
808 if (primary || isa_mem_base == 0)
809 isa_mem_base = range.cpu_addr;
810 hose->isa_mem_phys = range.cpu_addr;
811 hose->isa_mem_size = range.size;
815 hose->mem_offset[memno] = range.cpu_addr -
817 res = &hose->mem_resources[memno++];
821 res->name = dev->full_name;
822 res->flags = range.flags;
823 res->start = range.cpu_addr;
824 res->end = range.cpu_addr + range.size - 1;
825 res->parent = res->child = res->sibling = NULL;
830 /* Decide whether to display the domain number in /proc */
831 int pci_proc_domain(struct pci_bus *bus)
833 struct pci_controller *hose = pci_bus_to_host(bus);
835 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
837 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
838 return hose->global_number != 0;
842 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
844 if (ppc_md.pcibios_root_bridge_prepare)
845 return ppc_md.pcibios_root_bridge_prepare(bridge);
850 /* This header fixup will do the resource fixup for all devices as they are
851 * probed, but not for bridge ranges
853 static void pcibios_fixup_resources(struct pci_dev *dev)
855 struct pci_controller *hose = pci_bus_to_host(dev->bus);
859 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
867 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
868 struct resource *res = dev->resource + i;
869 struct pci_bus_region reg;
873 /* If we're going to re-assign everything, we mark all resources
874 * as unset (and 0-base them). In addition, we mark BARs starting
875 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
876 * since in that case, we don't want to re-assign anything
878 pcibios_resource_to_bus(dev->bus, ®, res);
879 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
880 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
881 /* Only print message if not re-assigning */
882 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
883 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
884 pci_name(dev), i, res);
885 res->end -= res->start;
887 res->flags |= IORESOURCE_UNSET;
891 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
894 /* Call machine specific resource fixup */
895 if (ppc_md.pcibios_fixup_resources)
896 ppc_md.pcibios_fixup_resources(dev);
898 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
900 /* This function tries to figure out if a bridge resource has been initialized
901 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
902 * things go more smoothly when it gets it right. It should covers cases such
903 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
905 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
906 struct resource *res)
908 struct pci_controller *hose = pci_bus_to_host(bus);
909 struct pci_dev *dev = bus->self;
910 resource_size_t offset;
911 struct pci_bus_region region;
915 /* We don't do anything if PCI_PROBE_ONLY is set */
916 if (pci_has_flag(PCI_PROBE_ONLY))
919 /* Job is a bit different between memory and IO */
920 if (res->flags & IORESOURCE_MEM) {
921 pcibios_resource_to_bus(dev->bus, ®ion, res);
923 /* If the BAR is non-0 then it's probably been initialized */
924 if (region.start != 0)
927 /* The BAR is 0, let's check if memory decoding is enabled on
928 * the bridge. If not, we consider it unassigned
930 pci_read_config_word(dev, PCI_COMMAND, &command);
931 if ((command & PCI_COMMAND_MEMORY) == 0)
934 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
935 * resources covers that starting address (0 then it's good enough for
936 * us for memory space)
938 for (i = 0; i < 3; i++) {
939 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
940 hose->mem_resources[i].start == hose->mem_offset[i])
944 /* Well, it starts at 0 and we know it will collide so we may as
945 * well consider it as unassigned. That covers the Apple case.
949 /* If the BAR is non-0, then we consider it assigned */
950 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
951 if (((res->start - offset) & 0xfffffffful) != 0)
954 /* Here, we are a bit different than memory as typically IO space
955 * starting at low addresses -is- valid. What we do instead if that
956 * we consider as unassigned anything that doesn't have IO enabled
957 * in the PCI command register, and that's it.
959 pci_read_config_word(dev, PCI_COMMAND, &command);
960 if (command & PCI_COMMAND_IO)
963 /* It's starting at 0 and IO is disabled in the bridge, consider
970 /* Fixup resources of a PCI<->PCI bridge */
971 static void pcibios_fixup_bridge(struct pci_bus *bus)
973 struct resource *res;
976 struct pci_dev *dev = bus->self;
978 pci_bus_for_each_resource(bus, res, i) {
979 if (!res || !res->flags)
981 if (i >= 3 && bus->self->transparent)
984 /* If we're going to reassign everything, we can
985 * shrink the P2P resource to have size as being
986 * of 0 in order to save space.
988 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
989 res->flags |= IORESOURCE_UNSET;
995 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
997 /* Try to detect uninitialized P2P bridge resources,
998 * and clear them out so they get re-assigned later
1000 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1002 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1007 void pcibios_setup_bus_self(struct pci_bus *bus)
1009 struct pci_controller *phb;
1011 /* Fix up the bus resources for P2P bridges */
1012 if (bus->self != NULL)
1013 pcibios_fixup_bridge(bus);
1015 /* Platform specific bus fixups. This is currently only used
1016 * by fsl_pci and I'm hoping to get rid of it at some point
1018 if (ppc_md.pcibios_fixup_bus)
1019 ppc_md.pcibios_fixup_bus(bus);
1021 /* Setup bus DMA mappings */
1022 phb = pci_bus_to_host(bus);
1023 if (phb->controller_ops.dma_bus_setup)
1024 phb->controller_ops.dma_bus_setup(bus);
1027 static void pcibios_setup_device(struct pci_dev *dev)
1029 struct pci_controller *phb;
1030 /* Fixup NUMA node as it may not be setup yet by the generic
1031 * code and is needed by the DMA init
1033 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1035 /* Hook up default DMA ops */
1036 set_dma_ops(&dev->dev, pci_dma_ops);
1037 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1039 /* Additional platform DMA/iommu setup */
1040 phb = pci_bus_to_host(dev->bus);
1041 if (phb->controller_ops.dma_dev_setup)
1042 phb->controller_ops.dma_dev_setup(dev);
1044 /* Read default IRQs and fixup if necessary */
1045 pci_read_irq_line(dev);
1046 if (ppc_md.pci_irq_fixup)
1047 ppc_md.pci_irq_fixup(dev);
1050 int pcibios_add_device(struct pci_dev *dev)
1053 * We can only call pcibios_setup_device() after bus setup is complete,
1054 * since some of the platform specific DMA setup code depends on it.
1056 if (dev->bus->is_added)
1057 pcibios_setup_device(dev);
1059 #ifdef CONFIG_PCI_IOV
1060 if (ppc_md.pcibios_fixup_sriov)
1061 ppc_md.pcibios_fixup_sriov(dev);
1062 #endif /* CONFIG_PCI_IOV */
1067 void pcibios_setup_bus_devices(struct pci_bus *bus)
1069 struct pci_dev *dev;
1071 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1072 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1074 list_for_each_entry(dev, &bus->devices, bus_list) {
1075 /* Cardbus can call us to add new devices to a bus, so ignore
1076 * those who are already fully discovered
1081 pcibios_setup_device(dev);
1085 void pcibios_set_master(struct pci_dev *dev)
1087 /* No special bus mastering setup handling */
1090 void pcibios_fixup_bus(struct pci_bus *bus)
1092 /* When called from the generic PCI probe, read PCI<->PCI bridge
1093 * bases. This is -not- called when generating the PCI tree from
1094 * the OF device-tree.
1096 pci_read_bridge_bases(bus);
1098 /* Now fixup the bus bus */
1099 pcibios_setup_bus_self(bus);
1101 /* Now fixup devices on that bus */
1102 pcibios_setup_bus_devices(bus);
1104 EXPORT_SYMBOL(pcibios_fixup_bus);
1106 void pci_fixup_cardbus(struct pci_bus *bus)
1108 /* Now fixup devices on that bus */
1109 pcibios_setup_bus_devices(bus);
1113 static int skip_isa_ioresource_align(struct pci_dev *dev)
1115 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1116 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1122 * We need to avoid collisions with `mirrored' VGA ports
1123 * and other strange ISA hardware, so we always want the
1124 * addresses to be allocated in the 0x000-0x0ff region
1127 * Why? Because some silly external IO cards only decode
1128 * the low 10 bits of the IO address. The 0x00-0xff region
1129 * is reserved for motherboard devices that decode all 16
1130 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1131 * but we want to try to avoid allocating at 0x2900-0x2bff
1132 * which might have be mirrored at 0x0100-0x03ff..
1134 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1135 resource_size_t size, resource_size_t align)
1137 struct pci_dev *dev = data;
1138 resource_size_t start = res->start;
1140 if (res->flags & IORESOURCE_IO) {
1141 if (skip_isa_ioresource_align(dev))
1144 start = (start + 0x3ff) & ~0x3ff;
1149 EXPORT_SYMBOL(pcibios_align_resource);
1152 * Reparent resource children of pr that conflict with res
1153 * under res, and make res replace those children.
1155 static int reparent_resources(struct resource *parent,
1156 struct resource *res)
1158 struct resource *p, **pp;
1159 struct resource **firstpp = NULL;
1161 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1162 if (p->end < res->start)
1164 if (res->end < p->start)
1166 if (p->start < res->start || p->end > res->end)
1167 return -1; /* not completely contained */
1168 if (firstpp == NULL)
1171 if (firstpp == NULL)
1172 return -1; /* didn't find any conflicting entries? */
1173 res->parent = parent;
1174 res->child = *firstpp;
1178 for (p = res->child; p != NULL; p = p->sibling) {
1180 pr_debug("PCI: Reparented %s %pR under %s\n",
1181 p->name, p, res->name);
1187 * Handle resources of PCI devices. If the world were perfect, we could
1188 * just allocate all the resource regions and do nothing more. It isn't.
1189 * On the other hand, we cannot just re-allocate all devices, as it would
1190 * require us to know lots of host bridge internals. So we attempt to
1191 * keep as much of the original configuration as possible, but tweak it
1192 * when it's found to be wrong.
1194 * Known BIOS problems we have to work around:
1195 * - I/O or memory regions not configured
1196 * - regions configured, but not enabled in the command register
1197 * - bogus I/O addresses above 64K used
1198 * - expansion ROMs left enabled (this may sound harmless, but given
1199 * the fact the PCI specs explicitly allow address decoders to be
1200 * shared between expansion ROMs and other resource regions, it's
1201 * at least dangerous)
1204 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1205 * This gives us fixed barriers on where we can allocate.
1206 * (2) Allocate resources for all enabled devices. If there is
1207 * a collision, just mark the resource as unallocated. Also
1208 * disable expansion ROMs during this step.
1209 * (3) Try to allocate resources for disabled devices. If the
1210 * resources were assigned correctly, everything goes well,
1211 * if they weren't, they won't disturb allocation of other
1213 * (4) Assign new addresses to resources which were either
1214 * not configured at all or misconfigured. If explicitly
1215 * requested by the user, configure expansion ROM address
1219 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1223 struct resource *res, *pr;
1225 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1226 pci_domain_nr(bus), bus->number);
1228 pci_bus_for_each_resource(bus, res, i) {
1229 if (!res || !res->flags || res->start > res->end || res->parent)
1232 /* If the resource was left unset at this point, we clear it */
1233 if (res->flags & IORESOURCE_UNSET)
1234 goto clear_resource;
1236 if (bus->parent == NULL)
1237 pr = (res->flags & IORESOURCE_IO) ?
1238 &ioport_resource : &iomem_resource;
1240 pr = pci_find_parent_resource(bus->self, res);
1242 /* this happens when the generic PCI
1243 * code (wrongly) decides that this
1244 * bridge is transparent -- paulus
1250 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1251 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1252 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1254 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1255 struct pci_dev *dev = bus->self;
1257 if (request_resource(pr, res) == 0)
1260 * Must be a conflict with an existing entry.
1261 * Move that entry (or entries) under the
1262 * bridge resource and try again.
1264 if (reparent_resources(pr, res) == 0)
1267 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1268 pci_claim_bridge_resource(dev,
1269 i + PCI_BRIDGE_RESOURCES) == 0)
1272 pr_warning("PCI: Cannot allocate resource region "
1273 "%d of PCI bridge %d, will remap\n", i, bus->number);
1275 /* The resource might be figured out when doing
1276 * reassignment based on the resources required
1277 * by the downstream PCI devices. Here we set
1278 * the size of the resource to be 0 in order to
1286 list_for_each_entry(b, &bus->children, node)
1287 pcibios_allocate_bus_resources(b);
1290 static inline void alloc_resource(struct pci_dev *dev, int idx)
1292 struct resource *pr, *r = &dev->resource[idx];
1294 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1295 pci_name(dev), idx, r);
1297 pr = pci_find_parent_resource(dev, r);
1298 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1299 request_resource(pr, r) < 0) {
1300 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1301 " of device %s, will remap\n", idx, pci_name(dev));
1303 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1304 /* We'll assign a new address later */
1305 r->flags |= IORESOURCE_UNSET;
1311 static void __init pcibios_allocate_resources(int pass)
1313 struct pci_dev *dev = NULL;
1318 for_each_pci_dev(dev) {
1319 pci_read_config_word(dev, PCI_COMMAND, &command);
1320 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1321 r = &dev->resource[idx];
1322 if (r->parent) /* Already allocated */
1324 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1325 continue; /* Not assigned at all */
1326 /* We only allocate ROMs on pass 1 just in case they
1327 * have been screwed up by firmware
1329 if (idx == PCI_ROM_RESOURCE )
1331 if (r->flags & IORESOURCE_IO)
1332 disabled = !(command & PCI_COMMAND_IO);
1334 disabled = !(command & PCI_COMMAND_MEMORY);
1335 if (pass == disabled)
1336 alloc_resource(dev, idx);
1340 r = &dev->resource[PCI_ROM_RESOURCE];
1342 /* Turn the ROM off, leave the resource region,
1343 * but keep it unregistered.
1346 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1347 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1348 pr_debug("PCI: Switching off ROM of %s\n",
1350 r->flags &= ~IORESOURCE_ROM_ENABLE;
1351 pci_write_config_dword(dev, dev->rom_base_reg,
1352 reg & ~PCI_ROM_ADDRESS_ENABLE);
1358 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1360 struct pci_controller *hose = pci_bus_to_host(bus);
1361 resource_size_t offset;
1362 struct resource *res, *pres;
1365 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1368 if (!(hose->io_resource.flags & IORESOURCE_IO))
1370 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1371 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1372 BUG_ON(res == NULL);
1373 res->name = "Legacy IO";
1374 res->flags = IORESOURCE_IO;
1375 res->start = offset;
1376 res->end = (offset + 0xfff) & 0xfffffffful;
1377 pr_debug("Candidate legacy IO: %pR\n", res);
1378 if (request_resource(&hose->io_resource, res)) {
1380 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1381 pci_domain_nr(bus), bus->number, res);
1386 /* Check for memory */
1387 for (i = 0; i < 3; i++) {
1388 pres = &hose->mem_resources[i];
1389 offset = hose->mem_offset[i];
1390 if (!(pres->flags & IORESOURCE_MEM))
1392 pr_debug("hose mem res: %pR\n", pres);
1393 if ((pres->start - offset) <= 0xa0000 &&
1394 (pres->end - offset) >= 0xbffff)
1399 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1400 BUG_ON(res == NULL);
1401 res->name = "Legacy VGA memory";
1402 res->flags = IORESOURCE_MEM;
1403 res->start = 0xa0000 + offset;
1404 res->end = 0xbffff + offset;
1405 pr_debug("Candidate VGA memory: %pR\n", res);
1406 if (request_resource(pres, res)) {
1408 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1409 pci_domain_nr(bus), bus->number, res);
1414 void __init pcibios_resource_survey(void)
1418 /* Allocate and assign resources */
1419 list_for_each_entry(b, &pci_root_buses, node)
1420 pcibios_allocate_bus_resources(b);
1421 pcibios_allocate_resources(0);
1422 pcibios_allocate_resources(1);
1424 /* Before we start assigning unassigned resource, we try to reserve
1425 * the low IO area and the VGA memory area if they intersect the
1426 * bus available resources to avoid allocating things on top of them
1428 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1429 list_for_each_entry(b, &pci_root_buses, node)
1430 pcibios_reserve_legacy_regions(b);
1433 /* Now, if the platform didn't decide to blindly trust the firmware,
1434 * we proceed to assigning things that were left unassigned
1436 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1437 pr_debug("PCI: Assigning unassigned resources...\n");
1438 pci_assign_unassigned_resources();
1441 /* Call machine dependent fixup */
1442 if (ppc_md.pcibios_fixup)
1443 ppc_md.pcibios_fixup();
1446 /* This is used by the PCI hotplug driver to allocate resource
1447 * of newly plugged busses. We can try to consolidate with the
1448 * rest of the code later, for now, keep it as-is as our main
1449 * resource allocation function doesn't deal with sub-trees yet.
1451 void pcibios_claim_one_bus(struct pci_bus *bus)
1453 struct pci_dev *dev;
1454 struct pci_bus *child_bus;
1456 list_for_each_entry(dev, &bus->devices, bus_list) {
1459 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1460 struct resource *r = &dev->resource[i];
1462 if (r->parent || !r->start || !r->flags)
1465 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1466 pci_name(dev), i, r);
1468 if (pci_claim_resource(dev, i) == 0)
1471 pci_claim_bridge_resource(dev, i);
1475 list_for_each_entry(child_bus, &bus->children, node)
1476 pcibios_claim_one_bus(child_bus);
1478 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1481 /* pcibios_finish_adding_to_bus
1483 * This is to be called by the hotplug code after devices have been
1484 * added to a bus, this include calling it for a PHB that is just
1487 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1489 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1490 pci_domain_nr(bus), bus->number);
1492 /* Allocate bus and devices resources */
1493 pcibios_allocate_bus_resources(bus);
1494 pcibios_claim_one_bus(bus);
1495 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1497 pci_assign_unassigned_bridge_resources(bus->self);
1499 pci_assign_unassigned_bus_resources(bus);
1503 eeh_add_device_tree_late(bus);
1505 /* Add new devices to global lists. Register in proc, sysfs. */
1506 pci_bus_add_devices(bus);
1508 /* sysfs files should only be added after devices are added */
1509 eeh_add_sysfs_files(bus);
1511 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1513 int pcibios_enable_device(struct pci_dev *dev, int mask)
1515 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1517 if (phb->controller_ops.enable_device_hook)
1518 if (!phb->controller_ops.enable_device_hook(dev))
1521 return pci_enable_resources(dev, mask);
1524 void pcibios_disable_device(struct pci_dev *dev)
1526 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1528 if (phb->controller_ops.disable_device)
1529 phb->controller_ops.disable_device(dev);
1532 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1534 return (unsigned long) hose->io_base_virt - _IO_BASE;
1537 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1538 struct list_head *resources)
1540 struct resource *res;
1541 resource_size_t offset;
1544 /* Hookup PHB IO resource */
1545 res = &hose->io_resource;
1548 pr_debug("PCI: I/O resource not set for host"
1549 " bridge %s (domain %d)\n",
1550 hose->dn->full_name, hose->global_number);
1552 offset = pcibios_io_space_offset(hose);
1554 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1555 res, (unsigned long long)offset);
1556 pci_add_resource_offset(resources, res, offset);
1559 /* Hookup PHB Memory resources */
1560 for (i = 0; i < 3; ++i) {
1561 res = &hose->mem_resources[i];
1564 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1565 "host bridge %s (domain %d)\n",
1566 hose->dn->full_name, hose->global_number);
1569 offset = hose->mem_offset[i];
1572 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1573 res, (unsigned long long)offset);
1575 pci_add_resource_offset(resources, res, offset);
1580 * Null PCI config access functions, for the case when we can't
1583 #define NULL_PCI_OP(rw, size, type) \
1585 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1587 return PCIBIOS_DEVICE_NOT_FOUND; \
1591 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1594 return PCIBIOS_DEVICE_NOT_FOUND;
1598 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1601 return PCIBIOS_DEVICE_NOT_FOUND;
1604 static struct pci_ops null_pci_ops =
1606 .read = null_read_config,
1607 .write = null_write_config,
1611 * These functions are used early on before PCI scanning is done
1612 * and all of the pci_dev and pci_bus structures have been created.
1614 static struct pci_bus *
1615 fake_pci_bus(struct pci_controller *hose, int busnr)
1617 static struct pci_bus bus;
1620 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1624 bus.ops = hose? hose->ops: &null_pci_ops;
1628 #define EARLY_PCI_OP(rw, size, type) \
1629 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1630 int devfn, int offset, type value) \
1632 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1633 devfn, offset, value); \
1636 EARLY_PCI_OP(read, byte, u8 *)
1637 EARLY_PCI_OP(read, word, u16 *)
1638 EARLY_PCI_OP(read, dword, u32 *)
1639 EARLY_PCI_OP(write, byte, u8)
1640 EARLY_PCI_OP(write, word, u16)
1641 EARLY_PCI_OP(write, dword, u32)
1643 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1646 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1649 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1651 struct pci_controller *hose = bus->sysdata;
1653 return of_node_get(hose->dn);
1657 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1658 * @hose: Pointer to the PCI host controller instance structure
1660 void pcibios_scan_phb(struct pci_controller *hose)
1662 LIST_HEAD(resources);
1663 struct pci_bus *bus;
1664 struct device_node *node = hose->dn;
1667 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1669 /* Get some IO space for the new PHB */
1670 pcibios_setup_phb_io_space(hose);
1672 /* Wire up PHB bus resources */
1673 pcibios_setup_phb_resources(hose, &resources);
1675 hose->busn.start = hose->first_busno;
1676 hose->busn.end = hose->last_busno;
1677 hose->busn.flags = IORESOURCE_BUS;
1678 pci_add_resource(&resources, &hose->busn);
1680 /* Create an empty bus for the toplevel */
1681 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1682 hose->ops, hose, &resources);
1684 pr_err("Failed to create bus for PCI domain %04x\n",
1685 hose->global_number);
1686 pci_free_resource_list(&resources);
1691 /* Get probe mode and perform scan */
1692 mode = PCI_PROBE_NORMAL;
1693 if (node && hose->controller_ops.probe_mode)
1694 mode = hose->controller_ops.probe_mode(bus);
1695 pr_debug(" probe mode: %d\n", mode);
1696 if (mode == PCI_PROBE_DEVTREE)
1697 of_scan_bus(node, bus);
1699 if (mode == PCI_PROBE_NORMAL) {
1700 pci_bus_update_busn_res_end(bus, 255);
1701 hose->last_busno = pci_scan_child_bus(bus);
1702 pci_bus_update_busn_res_end(bus, hose->last_busno);
1705 /* Platform gets a chance to do some global fixups before
1706 * we proceed to resource allocation
1708 if (ppc_md.pcibios_fixup_phb)
1709 ppc_md.pcibios_fixup_phb(hose);
1711 /* Configure PCI Express settings */
1712 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1713 struct pci_bus *child;
1714 list_for_each_entry(child, &bus->children, node)
1715 pcie_bus_configure_settings(child);
1718 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1720 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1722 int i, class = dev->class >> 8;
1723 /* When configured as agent, programing interface = 1 */
1724 int prog_if = dev->class & 0xf;
1726 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1727 class == PCI_CLASS_BRIDGE_OTHER) &&
1728 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1730 (dev->bus->parent == NULL)) {
1731 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1732 dev->resource[i].start = 0;
1733 dev->resource[i].end = 0;
1734 dev->resource[i].flags = 0;
1738 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1739 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1741 static void fixup_vga(struct pci_dev *pdev)
1745 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1746 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1747 vga_set_default_device(pdev);
1750 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1751 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);