1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
12 * Common pmac/prep/chrp pci routines. -- Cort
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/export.h>
21 #include <linux/of_address.h>
22 #include <linux/of_pci.h>
24 #include <linux/shmem_fs.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
30 #include <linux/vgaarb.h>
31 #include <linux/numa.h>
32 #include <linux/msi.h>
33 #include <linux/irqdomain.h>
35 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
39 #include <asm/machdep.h>
40 #include <asm/ppc-pci.h>
42 #include <asm/setup.h>
44 #include "../../../drivers/pci/pci.h"
46 /* hose_spinlock protects accesses to the phb_bitmap. */
47 static DEFINE_SPINLOCK(hose_spinlock);
50 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
51 #define MAX_PHBS 0x10000
54 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
55 * Accesses to this bitmap should be protected by hose_spinlock.
57 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
59 /* ISA Memory physical address */
60 resource_size_t isa_mem_base;
61 EXPORT_SYMBOL(isa_mem_base);
64 static const struct dma_map_ops *pci_dma_ops;
66 void __init set_pci_dma_ops(const struct dma_map_ops *dma_ops)
68 pci_dma_ops = dma_ops;
72 * This function should run under locking protection, specifically
75 static int get_phb_number(struct device_node *dn)
81 * Try fixed PHB numbering first, by checking archs and reading
82 * the respective device-tree properties. Firstly, try reading
83 * standard "linux,pci-domain", then try reading "ibm,opal-phbid"
84 * (only present in powernv OPAL environment), then try device-tree
85 * alias and as the last try to use lower bits of "reg" property.
87 ret = of_get_pci_domain_nr(dn);
93 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
96 ret = of_alias_get_id(dn, "pci");
104 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
109 phb_id = (int)(prop & (MAX_PHBS - 1));
111 /* We need to be sure to not use the same PHB number twice. */
112 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
115 /* If everything fails then fallback to dynamic PHB numbering. */
116 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
117 BUG_ON(phb_id >= MAX_PHBS);
118 set_bit(phb_id, phb_bitmap);
123 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
125 struct pci_controller *phb;
127 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
130 spin_lock(&hose_spinlock);
131 phb->global_number = get_phb_number(dev);
132 list_add_tail(&phb->list_node, &hose_list);
133 spin_unlock(&hose_spinlock);
135 phb->is_dynamic = slab_is_available();
138 int nid = of_node_to_nid(dev);
140 if (nid < 0 || !node_online(nid))
143 PHB_SET_NODE(phb, nid);
148 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
150 void pcibios_free_controller(struct pci_controller *phb)
152 spin_lock(&hose_spinlock);
154 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
155 if (phb->global_number < MAX_PHBS)
156 clear_bit(phb->global_number, phb_bitmap);
158 list_del(&phb->list_node);
159 spin_unlock(&hose_spinlock);
164 EXPORT_SYMBOL_GPL(pcibios_free_controller);
167 * This function is used to call pcibios_free_controller()
168 * in a deferred manner: a callback from the PCI subsystem.
170 * _*DO NOT*_ call pcibios_free_controller() explicitly if
171 * this is used (or it may access an invalid *phb pointer).
173 * The callback occurs when all references to the root bus
174 * are dropped (e.g., child buses/devices and their users).
176 * It's called as .release_fn() of 'struct pci_host_bridge'
177 * which is associated with the 'struct pci_controller.bus'
178 * (root bus) - it expects .release_data to hold a pointer
179 * to 'struct pci_controller'.
181 * In order to use it, register .release_fn()/release_data
184 * pci_set_host_bridge_release(bridge,
185 * pcibios_free_controller_deferred
188 * e.g. in the pcibios_root_bridge_prepare() callback from
189 * pci_create_root_bus().
191 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
193 struct pci_controller *phb = (struct pci_controller *)
194 bridge->release_data;
196 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
198 pcibios_free_controller(phb);
200 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
203 * The function is used to return the minimal alignment
204 * for memory or I/O windows of the associated P2P bridge.
205 * By default, 4KiB alignment for I/O windows and 1MiB for
208 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
211 struct pci_controller *phb = pci_bus_to_host(bus);
213 if (phb->controller_ops.window_alignment)
214 return phb->controller_ops.window_alignment(bus, type);
217 * PCI core will figure out the default
218 * alignment: 4KiB for I/O and 1MiB for
224 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
226 struct pci_controller *hose = pci_bus_to_host(bus);
228 if (hose->controller_ops.setup_bridge)
229 hose->controller_ops.setup_bridge(bus, type);
232 void pcibios_reset_secondary_bus(struct pci_dev *dev)
234 struct pci_controller *phb = pci_bus_to_host(dev->bus);
236 if (phb->controller_ops.reset_secondary_bus) {
237 phb->controller_ops.reset_secondary_bus(dev);
241 pci_reset_secondary_bus(dev);
244 resource_size_t pcibios_default_alignment(void)
246 if (ppc_md.pcibios_default_alignment)
247 return ppc_md.pcibios_default_alignment();
252 #ifdef CONFIG_PCI_IOV
253 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
255 if (ppc_md.pcibios_iov_resource_alignment)
256 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
258 return pci_iov_resource_size(pdev, resno);
261 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
263 if (ppc_md.pcibios_sriov_enable)
264 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
269 int pcibios_sriov_disable(struct pci_dev *pdev)
271 if (ppc_md.pcibios_sriov_disable)
272 return ppc_md.pcibios_sriov_disable(pdev);
277 #endif /* CONFIG_PCI_IOV */
279 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
282 return hose->pci_io_size;
284 return resource_size(&hose->io_resource);
288 int pcibios_vaddr_is_ioport(void __iomem *address)
291 struct pci_controller *hose;
292 resource_size_t size;
294 spin_lock(&hose_spinlock);
295 list_for_each_entry(hose, &hose_list, list_node) {
296 size = pcibios_io_size(hose);
297 if (address >= hose->io_base_virt &&
298 address < (hose->io_base_virt + size)) {
303 spin_unlock(&hose_spinlock);
307 unsigned long pci_address_to_pio(phys_addr_t address)
309 struct pci_controller *hose;
310 resource_size_t size;
311 unsigned long ret = ~0;
313 spin_lock(&hose_spinlock);
314 list_for_each_entry(hose, &hose_list, list_node) {
315 size = pcibios_io_size(hose);
316 if (address >= hose->io_base_phys &&
317 address < (hose->io_base_phys + size)) {
319 (unsigned long)hose->io_base_virt - _IO_BASE;
320 ret = base + (address - hose->io_base_phys);
324 spin_unlock(&hose_spinlock);
328 EXPORT_SYMBOL_GPL(pci_address_to_pio);
331 * Return the domain number for this bus.
333 int pci_domain_nr(struct pci_bus *bus)
335 struct pci_controller *hose = pci_bus_to_host(bus);
337 return hose->global_number;
339 EXPORT_SYMBOL(pci_domain_nr);
341 /* This routine is meant to be used early during boot, when the
342 * PCI bus numbers have not yet been assigned, and you need to
343 * issue PCI config cycles to an OF device.
344 * It could also be used to "fix" RTAS config cycles if you want
345 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
348 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
351 struct pci_controller *hose, *tmp;
352 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
353 if (hose->dn == node)
360 struct pci_controller *pci_find_controller_for_domain(int domain_nr)
362 struct pci_controller *hose;
364 list_for_each_entry(hose, &hose_list, list_node)
365 if (hose->global_number == domain_nr)
371 struct pci_intx_virq {
374 struct list_head list_node;
377 static LIST_HEAD(intx_list);
378 static DEFINE_MUTEX(intx_mutex);
380 static void ppc_pci_intx_release(struct kref *kref)
382 struct pci_intx_virq *vi = container_of(kref, struct pci_intx_virq, kref);
384 list_del(&vi->list_node);
385 irq_dispose_mapping(vi->virq);
389 static int ppc_pci_unmap_irq_line(struct notifier_block *nb,
390 unsigned long action, void *data)
392 struct pci_dev *pdev = to_pci_dev(data);
394 if (action == BUS_NOTIFY_DEL_DEVICE) {
395 struct pci_intx_virq *vi;
397 mutex_lock(&intx_mutex);
398 list_for_each_entry(vi, &intx_list, list_node) {
399 if (vi->virq == pdev->irq) {
400 kref_put(&vi->kref, ppc_pci_intx_release);
404 mutex_unlock(&intx_mutex);
410 static struct notifier_block ppc_pci_unmap_irq_notifier = {
411 .notifier_call = ppc_pci_unmap_irq_line,
414 static int ppc_pci_register_irq_notifier(void)
416 return bus_register_notifier(&pci_bus_type, &ppc_pci_unmap_irq_notifier);
418 arch_initcall(ppc_pci_register_irq_notifier);
421 * Reads the interrupt pin to determine if interrupt is use by card.
422 * If the interrupt is used, then gets the interrupt line from the
423 * openfirmware and sets it in the pci_dev and pci_config line.
425 static int pci_read_irq_line(struct pci_dev *pci_dev)
428 struct pci_intx_virq *vi, *vitmp;
430 /* Preallocate vi as rewind is complex if this fails after mapping */
431 vi = kzalloc(sizeof(struct pci_intx_virq), GFP_KERNEL);
435 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
437 /* Try to get a mapping from the device-tree */
438 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
442 /* If that fails, lets fallback to what is in the config
443 * space and map that through the default controller. We
444 * also set the type to level low since that's what PCI
445 * interrupts are. If your platform does differently, then
446 * either provide a proper interrupt tree or don't use this
449 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
453 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
454 line == 0xff || line == 0) {
457 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
460 virq = irq_create_mapping(NULL, line);
462 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
466 pr_debug(" Failed to map !\n");
470 pr_debug(" Mapped to linux irq %d\n", virq);
474 mutex_lock(&intx_mutex);
475 list_for_each_entry(vitmp, &intx_list, list_node) {
476 if (vitmp->virq == virq) {
477 kref_get(&vitmp->kref);
485 kref_init(&vi->kref);
486 list_add_tail(&vi->list_node, &intx_list);
488 mutex_unlock(&intx_mutex);
497 * Platform support for /proc/bus/pci/X/Y mmap()s.
500 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
502 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
503 resource_size_t ioaddr = pci_resource_start(pdev, bar);
508 /* Convert to an offset within this PCI controller */
509 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
511 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
516 * This one is used by /dev/mem and fbdev who have no clue about the
517 * PCI device, it tries to find the PCI device first and calls the
520 pgprot_t pci_phys_mem_access_prot(struct file *file,
525 struct pci_dev *pdev = NULL;
526 struct resource *found = NULL;
527 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
530 if (page_is_ram(pfn))
533 prot = pgprot_noncached(prot);
534 for_each_pci_dev(pdev) {
535 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
536 struct resource *rp = &pdev->resource[i];
537 int flags = rp->flags;
539 /* Active and same type? */
540 if ((flags & IORESOURCE_MEM) == 0)
542 /* In the range of this resource? */
543 if (offset < (rp->start & PAGE_MASK) ||
553 if (found->flags & IORESOURCE_PREFETCH)
554 prot = pgprot_noncached_wc(prot);
558 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
559 (unsigned long long)offset, pgprot_val(prot));
564 /* This provides legacy IO read access on a bus */
565 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
567 unsigned long offset;
568 struct pci_controller *hose = pci_bus_to_host(bus);
569 struct resource *rp = &hose->io_resource;
572 /* Check if port can be supported by that bus. We only check
573 * the ranges of the PHB though, not the bus itself as the rules
574 * for forwarding legacy cycles down bridges are not our problem
575 * here. So if the host bridge supports it, we do it.
577 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
580 if (!(rp->flags & IORESOURCE_IO))
582 if (offset < rp->start || (offset + size) > rp->end)
584 addr = hose->io_base_virt + port;
588 *((u8 *)val) = in_8(addr);
593 *((u16 *)val) = in_le16(addr);
598 *((u32 *)val) = in_le32(addr);
604 /* This provides legacy IO write access on a bus */
605 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
607 unsigned long offset;
608 struct pci_controller *hose = pci_bus_to_host(bus);
609 struct resource *rp = &hose->io_resource;
612 /* Check if port can be supported by that bus. We only check
613 * the ranges of the PHB though, not the bus itself as the rules
614 * for forwarding legacy cycles down bridges are not our problem
615 * here. So if the host bridge supports it, we do it.
617 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
620 if (!(rp->flags & IORESOURCE_IO))
622 if (offset < rp->start || (offset + size) > rp->end)
624 addr = hose->io_base_virt + port;
626 /* WARNING: The generic code is idiotic. It gets passed a pointer
627 * to what can be a 1, 2 or 4 byte quantity and always reads that
628 * as a u32, which means that we have to correct the location of
629 * the data read within those 32 bits for size 1 and 2
633 out_8(addr, val >> 24);
638 out_le16(addr, val >> 16);
649 /* This provides legacy IO or memory mmap access on a bus */
650 int pci_mmap_legacy_page_range(struct pci_bus *bus,
651 struct vm_area_struct *vma,
652 enum pci_mmap_state mmap_state)
654 struct pci_controller *hose = pci_bus_to_host(bus);
655 resource_size_t offset =
656 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
657 resource_size_t size = vma->vm_end - vma->vm_start;
660 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
661 pci_domain_nr(bus), bus->number,
662 mmap_state == pci_mmap_mem ? "MEM" : "IO",
663 (unsigned long long)offset,
664 (unsigned long long)(offset + size - 1));
666 if (mmap_state == pci_mmap_mem) {
669 * Because X is lame and can fail starting if it gets an error trying
670 * to mmap legacy_mem (instead of just moving on without legacy memory
671 * access) we fake it here by giving it anonymous memory, effectively
672 * behaving just like /dev/zero
674 if ((offset + size) > hose->isa_mem_size) {
676 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
677 current->comm, current->pid, pci_domain_nr(bus), bus->number);
678 if (vma->vm_flags & VM_SHARED)
679 return shmem_zero_setup(vma);
682 offset += hose->isa_mem_phys;
684 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
685 unsigned long roffset = offset + io_offset;
686 rp = &hose->io_resource;
687 if (!(rp->flags & IORESOURCE_IO))
689 if (roffset < rp->start || (roffset + size) > rp->end)
691 offset += hose->io_base_phys;
693 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
695 vma->vm_pgoff = offset >> PAGE_SHIFT;
696 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
697 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
698 vma->vm_end - vma->vm_start,
702 void pci_resource_to_user(const struct pci_dev *dev, int bar,
703 const struct resource *rsrc,
704 resource_size_t *start, resource_size_t *end)
706 struct pci_bus_region region;
708 if (rsrc->flags & IORESOURCE_IO) {
709 pcibios_resource_to_bus(dev->bus, ®ion,
710 (struct resource *) rsrc);
711 *start = region.start;
716 /* We pass a CPU physical address to userland for MMIO instead of a
717 * BAR value because X is lame and expects to be able to use that
718 * to pass to /dev/mem!
720 * That means we may have 64-bit values where some apps only expect
721 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
723 *start = rsrc->start;
728 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
729 * @hose: newly allocated pci_controller to be setup
730 * @dev: device node of the host bridge
731 * @primary: set if primary bus (32 bits only, soon to be deprecated)
733 * This function will parse the "ranges" property of a PCI host bridge device
734 * node and setup the resource mapping of a pci controller based on its
737 * Life would be boring if it wasn't for a few issues that we have to deal
740 * - We can only cope with one IO space range and up to 3 Memory space
741 * ranges. However, some machines (thanks Apple !) tend to split their
742 * space into lots of small contiguous ranges. So we have to coalesce.
744 * - Some busses have IO space not starting at 0, which causes trouble with
745 * the way we do our IO resource renumbering. The code somewhat deals with
746 * it for 64 bits but I would expect problems on 32 bits.
748 * - Some 32 bits platforms such as 4xx can have physical space larger than
749 * 32 bits so we need to use 64 bits values for the parsing
751 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
752 struct device_node *dev, int primary)
755 struct resource *res;
756 struct of_pci_range range;
757 struct of_pci_range_parser parser;
759 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
760 dev, primary ? "(primary)" : "");
762 /* Check for ranges property */
763 if (of_pci_range_parser_init(&parser, dev))
767 for_each_of_pci_range(&parser, &range) {
768 /* If we failed translation or got a zero-sized region
769 * (some FW try to feed us with non sensical zero sized regions
770 * such as power3 which look like some kind of attempt at exposing
771 * the VGA memory hole)
773 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
776 /* Act based on address space type */
778 switch (range.flags & IORESOURCE_TYPE_BITS) {
781 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
782 range.cpu_addr, range.cpu_addr + range.size - 1,
785 /* We support only one IO range */
786 if (hose->pci_io_size) {
788 " \\--> Skipped (too many) !\n");
792 /* On 32 bits, limit I/O space to 16MB */
793 if (range.size > 0x01000000)
794 range.size = 0x01000000;
796 /* 32 bits needs to map IOs here */
797 hose->io_base_virt = ioremap(range.cpu_addr,
800 /* Expect trouble if pci_addr is not 0 */
803 (unsigned long)hose->io_base_virt;
804 #endif /* CONFIG_PPC32 */
805 /* pci_io_size and io_base_phys always represent IO
806 * space starting at 0 so we factor in pci_addr
808 hose->pci_io_size = range.pci_addr + range.size;
809 hose->io_base_phys = range.cpu_addr - range.pci_addr;
812 res = &hose->io_resource;
813 range.cpu_addr = range.pci_addr;
817 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
818 range.cpu_addr, range.cpu_addr + range.size - 1,
820 (range.flags & IORESOURCE_PREFETCH) ?
823 /* We support only 3 memory ranges */
826 " \\--> Skipped (too many) !\n");
829 /* Handles ISA memory hole space here */
830 if (range.pci_addr == 0) {
831 if (primary || isa_mem_base == 0)
832 isa_mem_base = range.cpu_addr;
833 hose->isa_mem_phys = range.cpu_addr;
834 hose->isa_mem_size = range.size;
838 hose->mem_offset[memno] = range.cpu_addr -
840 res = &hose->mem_resources[memno++];
844 res->name = dev->full_name;
845 res->flags = range.flags;
846 res->start = range.cpu_addr;
847 res->end = range.cpu_addr + range.size - 1;
848 res->parent = res->child = res->sibling = NULL;
853 /* Decide whether to display the domain number in /proc */
854 int pci_proc_domain(struct pci_bus *bus)
856 struct pci_controller *hose = pci_bus_to_host(bus);
858 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
860 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
861 return hose->global_number != 0;
865 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
867 if (ppc_md.pcibios_root_bridge_prepare)
868 return ppc_md.pcibios_root_bridge_prepare(bridge);
873 /* This header fixup will do the resource fixup for all devices as they are
874 * probed, but not for bridge ranges
876 static void pcibios_fixup_resources(struct pci_dev *dev)
878 struct pci_controller *hose = pci_bus_to_host(dev->bus);
882 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
890 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
891 struct resource *res = dev->resource + i;
892 struct pci_bus_region reg;
896 /* If we're going to re-assign everything, we mark all resources
897 * as unset (and 0-base them). In addition, we mark BARs starting
898 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
899 * since in that case, we don't want to re-assign anything
901 pcibios_resource_to_bus(dev->bus, ®, res);
902 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
903 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
904 /* Only print message if not re-assigning */
905 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
906 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
907 pci_name(dev), i, res);
908 res->end -= res->start;
910 res->flags |= IORESOURCE_UNSET;
914 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
917 /* Call machine specific resource fixup */
918 if (ppc_md.pcibios_fixup_resources)
919 ppc_md.pcibios_fixup_resources(dev);
921 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
923 /* This function tries to figure out if a bridge resource has been initialized
924 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
925 * things go more smoothly when it gets it right. It should covers cases such
926 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
928 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
929 struct resource *res)
931 struct pci_controller *hose = pci_bus_to_host(bus);
932 struct pci_dev *dev = bus->self;
933 resource_size_t offset;
934 struct pci_bus_region region;
938 /* We don't do anything if PCI_PROBE_ONLY is set */
939 if (pci_has_flag(PCI_PROBE_ONLY))
942 /* Job is a bit different between memory and IO */
943 if (res->flags & IORESOURCE_MEM) {
944 pcibios_resource_to_bus(dev->bus, ®ion, res);
946 /* If the BAR is non-0 then it's probably been initialized */
947 if (region.start != 0)
950 /* The BAR is 0, let's check if memory decoding is enabled on
951 * the bridge. If not, we consider it unassigned
953 pci_read_config_word(dev, PCI_COMMAND, &command);
954 if ((command & PCI_COMMAND_MEMORY) == 0)
957 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
958 * resources covers that starting address (0 then it's good enough for
959 * us for memory space)
961 for (i = 0; i < 3; i++) {
962 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
963 hose->mem_resources[i].start == hose->mem_offset[i])
967 /* Well, it starts at 0 and we know it will collide so we may as
968 * well consider it as unassigned. That covers the Apple case.
972 /* If the BAR is non-0, then we consider it assigned */
973 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
974 if (((res->start - offset) & 0xfffffffful) != 0)
977 /* Here, we are a bit different than memory as typically IO space
978 * starting at low addresses -is- valid. What we do instead if that
979 * we consider as unassigned anything that doesn't have IO enabled
980 * in the PCI command register, and that's it.
982 pci_read_config_word(dev, PCI_COMMAND, &command);
983 if (command & PCI_COMMAND_IO)
986 /* It's starting at 0 and IO is disabled in the bridge, consider
993 /* Fixup resources of a PCI<->PCI bridge */
994 static void pcibios_fixup_bridge(struct pci_bus *bus)
996 struct resource *res;
999 struct pci_dev *dev = bus->self;
1001 pci_bus_for_each_resource(bus, res, i) {
1002 if (!res || !res->flags)
1004 if (i >= 3 && bus->self->transparent)
1007 /* If we're going to reassign everything, we can
1008 * shrink the P2P resource to have size as being
1009 * of 0 in order to save space.
1011 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1012 res->flags |= IORESOURCE_UNSET;
1018 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
1020 /* Try to detect uninitialized P2P bridge resources,
1021 * and clear them out so they get re-assigned later
1023 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1025 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1030 void pcibios_setup_bus_self(struct pci_bus *bus)
1032 struct pci_controller *phb;
1034 /* Fix up the bus resources for P2P bridges */
1035 if (bus->self != NULL)
1036 pcibios_fixup_bridge(bus);
1038 /* Platform specific bus fixups. This is currently only used
1039 * by fsl_pci and I'm hoping to get rid of it at some point
1041 if (ppc_md.pcibios_fixup_bus)
1042 ppc_md.pcibios_fixup_bus(bus);
1044 /* Setup bus DMA mappings */
1045 phb = pci_bus_to_host(bus);
1046 if (phb->controller_ops.dma_bus_setup)
1047 phb->controller_ops.dma_bus_setup(bus);
1050 void pcibios_bus_add_device(struct pci_dev *dev)
1052 struct pci_controller *phb;
1053 /* Fixup NUMA node as it may not be setup yet by the generic
1054 * code and is needed by the DMA init
1056 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1058 /* Hook up default DMA ops */
1059 set_dma_ops(&dev->dev, pci_dma_ops);
1060 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
1062 /* Additional platform DMA/iommu setup */
1063 phb = pci_bus_to_host(dev->bus);
1064 if (phb->controller_ops.dma_dev_setup)
1065 phb->controller_ops.dma_dev_setup(dev);
1067 /* Read default IRQs and fixup if necessary */
1068 pci_read_irq_line(dev);
1069 if (ppc_md.pci_irq_fixup)
1070 ppc_md.pci_irq_fixup(dev);
1072 if (ppc_md.pcibios_bus_add_device)
1073 ppc_md.pcibios_bus_add_device(dev);
1076 int pcibios_device_add(struct pci_dev *dev)
1078 struct irq_domain *d;
1080 #ifdef CONFIG_PCI_IOV
1081 if (ppc_md.pcibios_fixup_sriov)
1082 ppc_md.pcibios_fixup_sriov(dev);
1083 #endif /* CONFIG_PCI_IOV */
1085 d = dev_get_msi_domain(&dev->bus->dev);
1087 dev_set_msi_domain(&dev->dev, d);
1091 void pcibios_set_master(struct pci_dev *dev)
1093 /* No special bus mastering setup handling */
1096 void pcibios_fixup_bus(struct pci_bus *bus)
1098 /* When called from the generic PCI probe, read PCI<->PCI bridge
1099 * bases. This is -not- called when generating the PCI tree from
1100 * the OF device-tree.
1102 pci_read_bridge_bases(bus);
1104 /* Now fixup the bus */
1105 pcibios_setup_bus_self(bus);
1107 EXPORT_SYMBOL(pcibios_fixup_bus);
1109 static int skip_isa_ioresource_align(struct pci_dev *dev)
1111 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1112 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1118 * We need to avoid collisions with `mirrored' VGA ports
1119 * and other strange ISA hardware, so we always want the
1120 * addresses to be allocated in the 0x000-0x0ff region
1123 * Why? Because some silly external IO cards only decode
1124 * the low 10 bits of the IO address. The 0x00-0xff region
1125 * is reserved for motherboard devices that decode all 16
1126 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1127 * but we want to try to avoid allocating at 0x2900-0x2bff
1128 * which might have be mirrored at 0x0100-0x03ff..
1130 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1131 resource_size_t size, resource_size_t align)
1133 struct pci_dev *dev = data;
1134 resource_size_t start = res->start;
1136 if (res->flags & IORESOURCE_IO) {
1137 if (skip_isa_ioresource_align(dev))
1140 start = (start + 0x3ff) & ~0x3ff;
1145 EXPORT_SYMBOL(pcibios_align_resource);
1148 * Reparent resource children of pr that conflict with res
1149 * under res, and make res replace those children.
1151 static int reparent_resources(struct resource *parent,
1152 struct resource *res)
1154 struct resource *p, **pp;
1155 struct resource **firstpp = NULL;
1157 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1158 if (p->end < res->start)
1160 if (res->end < p->start)
1162 if (p->start < res->start || p->end > res->end)
1163 return -1; /* not completely contained */
1164 if (firstpp == NULL)
1167 if (firstpp == NULL)
1168 return -1; /* didn't find any conflicting entries? */
1169 res->parent = parent;
1170 res->child = *firstpp;
1174 for (p = res->child; p != NULL; p = p->sibling) {
1176 pr_debug("PCI: Reparented %s %pR under %s\n",
1177 p->name, p, res->name);
1183 * Handle resources of PCI devices. If the world were perfect, we could
1184 * just allocate all the resource regions and do nothing more. It isn't.
1185 * On the other hand, we cannot just re-allocate all devices, as it would
1186 * require us to know lots of host bridge internals. So we attempt to
1187 * keep as much of the original configuration as possible, but tweak it
1188 * when it's found to be wrong.
1190 * Known BIOS problems we have to work around:
1191 * - I/O or memory regions not configured
1192 * - regions configured, but not enabled in the command register
1193 * - bogus I/O addresses above 64K used
1194 * - expansion ROMs left enabled (this may sound harmless, but given
1195 * the fact the PCI specs explicitly allow address decoders to be
1196 * shared between expansion ROMs and other resource regions, it's
1197 * at least dangerous)
1200 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1201 * This gives us fixed barriers on where we can allocate.
1202 * (2) Allocate resources for all enabled devices. If there is
1203 * a collision, just mark the resource as unallocated. Also
1204 * disable expansion ROMs during this step.
1205 * (3) Try to allocate resources for disabled devices. If the
1206 * resources were assigned correctly, everything goes well,
1207 * if they weren't, they won't disturb allocation of other
1209 * (4) Assign new addresses to resources which were either
1210 * not configured at all or misconfigured. If explicitly
1211 * requested by the user, configure expansion ROM address
1215 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1219 struct resource *res, *pr;
1221 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1222 pci_domain_nr(bus), bus->number);
1224 pci_bus_for_each_resource(bus, res, i) {
1225 if (!res || !res->flags || res->start > res->end || res->parent)
1228 /* If the resource was left unset at this point, we clear it */
1229 if (res->flags & IORESOURCE_UNSET)
1230 goto clear_resource;
1232 if (bus->parent == NULL)
1233 pr = (res->flags & IORESOURCE_IO) ?
1234 &ioport_resource : &iomem_resource;
1236 pr = pci_find_parent_resource(bus->self, res);
1238 /* this happens when the generic PCI
1239 * code (wrongly) decides that this
1240 * bridge is transparent -- paulus
1246 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1247 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1248 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1250 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1251 struct pci_dev *dev = bus->self;
1253 if (request_resource(pr, res) == 0)
1256 * Must be a conflict with an existing entry.
1257 * Move that entry (or entries) under the
1258 * bridge resource and try again.
1260 if (reparent_resources(pr, res) == 0)
1263 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1264 pci_claim_bridge_resource(dev,
1265 i + PCI_BRIDGE_RESOURCES) == 0)
1268 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1271 /* The resource might be figured out when doing
1272 * reassignment based on the resources required
1273 * by the downstream PCI devices. Here we set
1274 * the size of the resource to be 0 in order to
1282 list_for_each_entry(b, &bus->children, node)
1283 pcibios_allocate_bus_resources(b);
1286 static inline void alloc_resource(struct pci_dev *dev, int idx)
1288 struct resource *pr, *r = &dev->resource[idx];
1290 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1291 pci_name(dev), idx, r);
1293 pr = pci_find_parent_resource(dev, r);
1294 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1295 request_resource(pr, r) < 0) {
1296 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1297 " of device %s, will remap\n", idx, pci_name(dev));
1299 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1300 /* We'll assign a new address later */
1301 r->flags |= IORESOURCE_UNSET;
1307 static void __init pcibios_allocate_resources(int pass)
1309 struct pci_dev *dev = NULL;
1314 for_each_pci_dev(dev) {
1315 pci_read_config_word(dev, PCI_COMMAND, &command);
1316 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1317 r = &dev->resource[idx];
1318 if (r->parent) /* Already allocated */
1320 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1321 continue; /* Not assigned at all */
1322 /* We only allocate ROMs on pass 1 just in case they
1323 * have been screwed up by firmware
1325 if (idx == PCI_ROM_RESOURCE )
1327 if (r->flags & IORESOURCE_IO)
1328 disabled = !(command & PCI_COMMAND_IO);
1330 disabled = !(command & PCI_COMMAND_MEMORY);
1331 if (pass == disabled)
1332 alloc_resource(dev, idx);
1336 r = &dev->resource[PCI_ROM_RESOURCE];
1338 /* Turn the ROM off, leave the resource region,
1339 * but keep it unregistered.
1342 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1343 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1344 pr_debug("PCI: Switching off ROM of %s\n",
1346 r->flags &= ~IORESOURCE_ROM_ENABLE;
1347 pci_write_config_dword(dev, dev->rom_base_reg,
1348 reg & ~PCI_ROM_ADDRESS_ENABLE);
1354 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1356 struct pci_controller *hose = pci_bus_to_host(bus);
1357 resource_size_t offset;
1358 struct resource *res, *pres;
1361 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1364 if (!(hose->io_resource.flags & IORESOURCE_IO))
1366 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1367 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1368 BUG_ON(res == NULL);
1369 res->name = "Legacy IO";
1370 res->flags = IORESOURCE_IO;
1371 res->start = offset;
1372 res->end = (offset + 0xfff) & 0xfffffffful;
1373 pr_debug("Candidate legacy IO: %pR\n", res);
1374 if (request_resource(&hose->io_resource, res)) {
1376 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1377 pci_domain_nr(bus), bus->number, res);
1382 /* Check for memory */
1383 for (i = 0; i < 3; i++) {
1384 pres = &hose->mem_resources[i];
1385 offset = hose->mem_offset[i];
1386 if (!(pres->flags & IORESOURCE_MEM))
1388 pr_debug("hose mem res: %pR\n", pres);
1389 if ((pres->start - offset) <= 0xa0000 &&
1390 (pres->end - offset) >= 0xbffff)
1395 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1396 BUG_ON(res == NULL);
1397 res->name = "Legacy VGA memory";
1398 res->flags = IORESOURCE_MEM;
1399 res->start = 0xa0000 + offset;
1400 res->end = 0xbffff + offset;
1401 pr_debug("Candidate VGA memory: %pR\n", res);
1402 if (request_resource(pres, res)) {
1404 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1405 pci_domain_nr(bus), bus->number, res);
1410 void __init pcibios_resource_survey(void)
1414 /* Allocate and assign resources */
1415 list_for_each_entry(b, &pci_root_buses, node)
1416 pcibios_allocate_bus_resources(b);
1417 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1418 pcibios_allocate_resources(0);
1419 pcibios_allocate_resources(1);
1422 /* Before we start assigning unassigned resource, we try to reserve
1423 * the low IO area and the VGA memory area if they intersect the
1424 * bus available resources to avoid allocating things on top of them
1426 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1427 list_for_each_entry(b, &pci_root_buses, node)
1428 pcibios_reserve_legacy_regions(b);
1431 /* Now, if the platform didn't decide to blindly trust the firmware,
1432 * we proceed to assigning things that were left unassigned
1434 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1435 pr_debug("PCI: Assigning unassigned resources...\n");
1436 pci_assign_unassigned_resources();
1440 /* This is used by the PCI hotplug driver to allocate resource
1441 * of newly plugged busses. We can try to consolidate with the
1442 * rest of the code later, for now, keep it as-is as our main
1443 * resource allocation function doesn't deal with sub-trees yet.
1445 void pcibios_claim_one_bus(struct pci_bus *bus)
1447 struct pci_dev *dev;
1448 struct pci_bus *child_bus;
1450 list_for_each_entry(dev, &bus->devices, bus_list) {
1453 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1454 struct resource *r = &dev->resource[i];
1456 if (r->parent || !r->start || !r->flags)
1459 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1460 pci_name(dev), i, r);
1462 if (pci_claim_resource(dev, i) == 0)
1465 pci_claim_bridge_resource(dev, i);
1469 list_for_each_entry(child_bus, &bus->children, node)
1470 pcibios_claim_one_bus(child_bus);
1472 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1475 /* pcibios_finish_adding_to_bus
1477 * This is to be called by the hotplug code after devices have been
1478 * added to a bus, this include calling it for a PHB that is just
1481 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1483 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1484 pci_domain_nr(bus), bus->number);
1486 /* Allocate bus and devices resources */
1487 pcibios_allocate_bus_resources(bus);
1488 pcibios_claim_one_bus(bus);
1489 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1491 pci_assign_unassigned_bridge_resources(bus->self);
1493 pci_assign_unassigned_bus_resources(bus);
1496 /* Add new devices to global lists. Register in proc, sysfs. */
1497 pci_bus_add_devices(bus);
1499 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1501 int pcibios_enable_device(struct pci_dev *dev, int mask)
1503 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1505 if (phb->controller_ops.enable_device_hook)
1506 if (!phb->controller_ops.enable_device_hook(dev))
1509 return pci_enable_resources(dev, mask);
1512 void pcibios_disable_device(struct pci_dev *dev)
1514 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1516 if (phb->controller_ops.disable_device)
1517 phb->controller_ops.disable_device(dev);
1520 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1522 return (unsigned long) hose->io_base_virt - _IO_BASE;
1525 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1526 struct list_head *resources)
1528 struct resource *res;
1529 resource_size_t offset;
1532 /* Hookup PHB IO resource */
1533 res = &hose->io_resource;
1536 pr_debug("PCI: I/O resource not set for host"
1537 " bridge %pOF (domain %d)\n",
1538 hose->dn, hose->global_number);
1540 offset = pcibios_io_space_offset(hose);
1542 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1543 res, (unsigned long long)offset);
1544 pci_add_resource_offset(resources, res, offset);
1547 /* Hookup PHB Memory resources */
1548 for (i = 0; i < 3; ++i) {
1549 res = &hose->mem_resources[i];
1553 offset = hose->mem_offset[i];
1554 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1555 res, (unsigned long long)offset);
1557 pci_add_resource_offset(resources, res, offset);
1562 * Null PCI config access functions, for the case when we can't
1565 #define NULL_PCI_OP(rw, size, type) \
1567 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1569 return PCIBIOS_DEVICE_NOT_FOUND; \
1573 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1576 return PCIBIOS_DEVICE_NOT_FOUND;
1580 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1583 return PCIBIOS_DEVICE_NOT_FOUND;
1586 static struct pci_ops null_pci_ops =
1588 .read = null_read_config,
1589 .write = null_write_config,
1593 * These functions are used early on before PCI scanning is done
1594 * and all of the pci_dev and pci_bus structures have been created.
1596 static struct pci_bus *
1597 fake_pci_bus(struct pci_controller *hose, int busnr)
1599 static struct pci_bus bus;
1602 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1606 bus.ops = hose? hose->ops: &null_pci_ops;
1610 #define EARLY_PCI_OP(rw, size, type) \
1611 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1612 int devfn, int offset, type value) \
1614 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1615 devfn, offset, value); \
1618 EARLY_PCI_OP(read, byte, u8 *)
1619 EARLY_PCI_OP(read, word, u16 *)
1620 EARLY_PCI_OP(read, dword, u32 *)
1621 EARLY_PCI_OP(write, byte, u8)
1622 EARLY_PCI_OP(write, word, u16)
1623 EARLY_PCI_OP(write, dword, u32)
1625 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1628 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1631 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1633 struct pci_controller *hose = bus->sysdata;
1635 return of_node_get(hose->dn);
1639 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1640 * @hose: Pointer to the PCI host controller instance structure
1642 void pcibios_scan_phb(struct pci_controller *hose)
1644 LIST_HEAD(resources);
1645 struct pci_bus *bus;
1646 struct device_node *node = hose->dn;
1649 pr_debug("PCI: Scanning PHB %pOF\n", node);
1651 /* Get some IO space for the new PHB */
1652 pcibios_setup_phb_io_space(hose);
1654 /* Wire up PHB bus resources */
1655 pcibios_setup_phb_resources(hose, &resources);
1657 hose->busn.start = hose->first_busno;
1658 hose->busn.end = hose->last_busno;
1659 hose->busn.flags = IORESOURCE_BUS;
1660 pci_add_resource(&resources, &hose->busn);
1662 /* Create an empty bus for the toplevel */
1663 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1664 hose->ops, hose, &resources);
1666 pr_err("Failed to create bus for PCI domain %04x\n",
1667 hose->global_number);
1668 pci_free_resource_list(&resources);
1673 /* Get probe mode and perform scan */
1674 mode = PCI_PROBE_NORMAL;
1675 if (node && hose->controller_ops.probe_mode)
1676 mode = hose->controller_ops.probe_mode(bus);
1677 pr_debug(" probe mode: %d\n", mode);
1678 if (mode == PCI_PROBE_DEVTREE)
1679 of_scan_bus(node, bus);
1681 if (mode == PCI_PROBE_NORMAL) {
1682 pci_bus_update_busn_res_end(bus, 255);
1683 hose->last_busno = pci_scan_child_bus(bus);
1684 pci_bus_update_busn_res_end(bus, hose->last_busno);
1687 /* Platform gets a chance to do some global fixups before
1688 * we proceed to resource allocation
1690 if (ppc_md.pcibios_fixup_phb)
1691 ppc_md.pcibios_fixup_phb(hose);
1693 /* Configure PCI Express settings */
1694 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1695 struct pci_bus *child;
1696 list_for_each_entry(child, &bus->children, node)
1697 pcie_bus_configure_settings(child);
1700 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1702 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1704 int i, class = dev->class >> 8;
1705 /* When configured as agent, programming interface = 1 */
1706 int prog_if = dev->class & 0xf;
1708 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1709 class == PCI_CLASS_BRIDGE_OTHER) &&
1710 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1712 (dev->bus->parent == NULL)) {
1713 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1714 dev->resource[i].start = 0;
1715 dev->resource[i].end = 0;
1716 dev->resource[i].flags = 0;
1720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1724 static int __init discover_phbs(void)
1726 if (ppc_md.discover_phbs)
1727 ppc_md.discover_phbs();
1731 core_initcall(discover_phbs);