2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
30 * Use unused space in the interrupt stack to save and restore
31 * registers for winkle support.
45 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
50 * Used by threads before entering deep idle states. Saves SPRs
51 * in interrupt stack frame
55 * Note all register i.e per-core, per-subcore or per-thread is saved
56 * here since any thread in the core might wake up first
60 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
70 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
91 * Used by threads when the lock bit of core_idle_state is set.
92 * Threads will spin in HMT_LOW until the lock bit is cleared.
93 * r14 - pointer to core_idle_state
94 * r15 - used to load contents of core_idle_state
95 * r9 - used as a temporary variable
101 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
105 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
106 bne- core_idle_lock_held
110 * Pass requested state in r3:
111 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
112 * - Requested PSSCR value in POWER9
114 * Address of idle handler to branch to in realmode in r4
116 pnv_powersave_common:
117 /* Use r3 to pass state nap/sleep/winkle */
118 /* NAP is a state loss, we create a regs frame on the
119 * stack, fill it up with the state we care about and
120 * stick a pointer to it in PACAR1. We really only
121 * need to save PC, some CR bits and the NV GPRs,
122 * but for now an interrupt frame will do.
128 stdu r1,-INT_FRAME_SIZE(r1)
132 /* We haven't lost state ... yet */
134 stb r0,PACA_NAPSTATELOST(r13)
136 /* Continue saving state */
144 * Go to real mode to do the nap, as required by the architecture.
145 * Also, we need to be in real mode before setting hwthread_state,
146 * because as soon as we do that, another thread can switch
147 * the MMU context to the guest.
149 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
153 .globl pnv_enter_arch207_idle_mode
154 pnv_enter_arch207_idle_mode:
155 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
156 /* Tell KVM we're entering idle */
157 li r4,KVM_HWTHREAD_IN_IDLE
158 /******************************************************/
159 /* N O T E W E L L ! ! ! N O T E W E L L */
160 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
161 /* MUST occur in real mode, i.e. with the MMU off, */
162 /* and the MMU must stay off until we clear this flag */
163 /* and test HSTATE_HWTHREAD_REQ(r13) in */
164 /* pnv_powersave_wakeup in this file. */
165 /* The reason is that another thread can switch the */
166 /* MMU to a guest context whenever this flag is set */
167 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
168 /* that would potentially cause this thread to start */
169 /* executing instructions from guest memory in */
170 /* hypervisor mode, leading to a host crash or data */
171 /* corruption, or worse. */
172 /******************************************************/
173 stb r4,HSTATE_HWTHREAD_STATE(r13)
175 stb r3,PACA_THREAD_IDLE_STATE(r13)
176 cmpwi cr3,r3,PNV_THREAD_SLEEP
178 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
181 /* Sleep or winkle */
182 lbz r7,PACA_THREAD_MASK(r13)
183 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
186 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
191 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
192 bnel- core_idle_lock_held
194 add r15,r15,r5 /* Add if winkle */
195 andc r15,r15,r7 /* Clear thread bit */
197 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
200 * If cr0 = 0, then current thread is the last thread of the core entering
201 * sleep. Last thread needs to execute the hardware bug workaround code if
202 * required by the platform.
203 * Make the workaround call unconditionally here. The below branch call is
204 * patched out when the idle states are discovered if the platform does not
207 .global pnv_fastsleep_workaround_at_entry
208 pnv_fastsleep_workaround_at_entry:
209 beq fastsleep_workaround_at_entry
215 common_enter: /* common code for all the threads entering sleep or winkle */
217 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
219 fastsleep_workaround_at_entry:
220 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
225 /* Fast sleep workaround */
228 bl opal_config_cpu_idle_state
231 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
237 bl save_sprs_to_stack
239 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
242 * r3 - PSSCR value corresponding to the requested stop state.
245 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
246 /* Tell KVM we're entering idle */
247 li r4,KVM_HWTHREAD_IN_IDLE
248 /* DO THIS IN REAL MODE! See comment above. */
249 stb r4,HSTATE_HWTHREAD_STATE(r13)
252 * Check if we are executing the lite variant with ESL=EC=0
254 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
255 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
256 bne .Lhandle_esl_ec_set
257 IDLE_STATE_ENTER_SEQ(PPC_STOP)
258 li r3,0 /* Since we didn't lose state, return 0 */
263 * Check if the requested state is a deep idle state.
265 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
266 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
268 bge .Lhandle_deep_stop
269 IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
272 * Entering deep idle state.
273 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
274 * stack and enter stop
276 lbz r7,PACA_THREAD_MASK(r13)
277 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
281 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
282 bnel- core_idle_lock_held
283 andc r15,r15,r7 /* Clear thread bit */
289 bl save_sprs_to_stack
291 IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
294 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
295 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE).
297 _GLOBAL(power7_idle_insn)
298 /* Now check if user or arch enabled NAP mode */
299 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode)
300 b pnv_powersave_common
302 #define CHECK_HMI_INTERRUPT \
303 BEGIN_FTR_SECTION_NESTED(66); \
304 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \
305 FTR_SECTION_ELSE_NESTED(66); \
306 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \
307 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
308 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
310 /* Invoke opal call to handle hmi */ \
311 ld r2,PACATOC(r13); \
313 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
314 li r3,0; /* NULL argument */ \
315 bl hmi_exception_realmode; \
317 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
321 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
322 * r3 contains desired PSSCR register value.
324 _GLOBAL(power9_idle_stop)
325 std r3, PACA_REQ_PSSCR(r13)
327 LOAD_REG_ADDR(r4,power_enter_stop)
328 b pnv_powersave_common
332 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
333 * HSPRG0 will be set to the HSPRG0 value of one of the
334 * threads in this core. Thus the value we have in r13
335 * may not be this thread's paca pointer.
337 * Fortunately, the TIR remains invariant. Since this thread's
338 * paca pointer is recorded in all its sibling's paca, we can
339 * correctly recover this thread's paca pointer if we
340 * know the index of this thread in the core.
342 * This index can be obtained from the TIR.
344 * i.e, thread's position in the core = TIR.
345 * If this value is i, then this thread's paca is
346 * paca->thread_sibling_pacas[i].
348 power9_dd1_recover_paca:
351 * Since each entry in thread_sibling_pacas is 8 bytes
352 * we need to left-shift by 3 bits. Thus r4 = i * 8
355 /* Get &paca->thread_sibling_pacas[0] in r5 */
356 ld r5, PACA_SIBLING_PACA_PTRS(r13)
357 /* Load paca->thread_sibling_pacas[i] into r13 */
361 * Indicate that we have lost NVGPR state
362 * which needs to be restored from the stack.
365 stb r3,PACA_NAPSTATELOST(r13)
369 * Called from machine check handler for powersave wakeups.
370 * Low level machine check processing has already been done. Now just
371 * go through the wake up path to get everything in order.
373 * r3 - The original SRR1 value.
374 * Original SRR[01] have been clobbered.
377 .global pnv_powersave_wakeup_mce
378 pnv_powersave_wakeup_mce:
379 /* Set cr3 for pnv_powersave_wakeup */
380 rlwinm r11,r3,47-31,30,31
384 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
385 * reason into r12, which allows reuse of the system reset wakeup
386 * code without being mistaken for another type of wakeup.
388 oris r12,r3,SRR1_WAKEMCE_RESVD@h
390 b pnv_powersave_wakeup
393 * Called from reset vector for powersave wakeups.
394 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
397 .global pnv_powersave_wakeup
398 pnv_powersave_wakeup:
402 BEGIN_FTR_SECTION_NESTED(70)
403 bl power9_dd1_recover_paca
404 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
405 bl pnv_restore_hyp_resource_arch300
407 bl pnv_restore_hyp_resource_arch207
408 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
410 li r0,PNV_THREAD_RUNNING
411 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
415 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
416 li r0,KVM_HWTHREAD_IN_KERNEL
417 stb r0,HSTATE_HWTHREAD_STATE(r13)
418 /* Order setting hwthread_state vs. testing hwthread_req */
420 lbz r0,HSTATE_HWTHREAD_REQ(r13)
427 /* Return SRR1 from power7_nap() */
428 blt cr3,pnv_wakeup_noloss
432 * Check whether we have woken up with hypervisor state loss.
433 * If yes, restore hypervisor state and return back to link.
435 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
437 pnv_restore_hyp_resource_arch300:
439 * POWER ISA 3. Use PSSCR to determine if we
440 * are waking up from deep idle state
442 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
443 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
445 BEGIN_FTR_SECTION_NESTED(71)
447 * Assume that we are waking up from the state
448 * same as the Requested Level (RL) in the PSSCR
449 * which are Bits 60-63
451 ld r5,PACA_REQ_PSSCR(r13)
453 FTR_SECTION_ELSE_NESTED(71)
455 * 0-3 bits correspond to Power-Saving Level Status
456 * which indicates the idle state we are waking up from
460 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71)
462 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
464 blr /* Waking up without hypervisor state loss. */
466 /* Same calling convention as arch300 */
467 pnv_restore_hyp_resource_arch207:
469 * POWER ISA 2.07 or less.
470 * Check if we slept with sleep or winkle.
472 lbz r4,PACA_THREAD_IDLE_STATE(r13)
473 cmpwi cr2,r4,PNV_THREAD_NAP
474 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
477 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
478 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
479 * indicates we are waking with hypervisor state loss from nap.
483 blr /* Waking up without hypervisor state loss */
486 * Called if waking up from idle state which can cause either partial or
487 * complete hyp state loss.
488 * In POWER8, called if waking up from fastsleep or winkle
489 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
492 * cr3 - gt if waking up with partial/complete hypervisor state loss
495 * cr4 - gt or eq if waking up from complete hypervisor state loss.
498 * r4 - PACA_THREAD_IDLE_STATE
503 * Before entering any idle state, the NVGPRs are saved in the stack.
504 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
505 * NVGPRs are restored. If we are here, it is likely that state is lost,
506 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
507 * here are the same as the test to restore NVGPRS:
508 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
509 * and SRR1 test for restoring NVGPRs.
511 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
512 * guarantee they will always be restored. This might be tightened
513 * with careful reading of specs (particularly for ISA300) but this
514 * is already a slow wakeup path and it's simpler to be safe.
517 stb r0,PACA_NAPSTATELOST(r13)
521 * Save SRR1 and LR in NVGPRs as they might be clobbered in
522 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
523 * to determine the wakeup reason if we branch to kvm_start_guest. LR
524 * is required to return back to reset vector after hypervisor state
525 * restore is complete.
532 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
534 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
535 lbz r7,PACA_THREAD_MASK(r13)
538 * Take the core lock to synchronize against other threads.
540 * Lock bit is set in one of the 2 cases-
541 * a. In the sleep/winkle enter path, the last thread is executing
542 * fastsleep workaround code.
543 * b. In the wake up path, another thread is executing fastsleep
544 * workaround undo code or resyncing timebase or restoring context
545 * In either case loop until the lock bit is cleared.
549 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
550 bnel- core_idle_lock_held
551 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
556 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
561 * cr2 - eq if first thread to wakeup in core
562 * cr3- gt if waking up with partial/complete hypervisor state loss
564 * cr4 - gt or eq if waking up from complete hypervisor state loss.
570 * If yes, check if all threads were in winkle, decrement our
571 * winkle count, set all thread winkle bits if all were in winkle.
572 * Check if our thread has a winkle bit set, and set cr4 accordingly
573 * (to match ISA300, above). Pseudo-code for core idle state
574 * transitions for ISA207 is as follows (everything happens atomically
575 * due to store conditional and/or lock bit):
582 * core_idle_state &= ~thread_in_core
587 * bool first_in_core, first_in_subcore;
589 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
590 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
592 * core_idle_state |= thread_in_core;
597 * core_idle_state &= ~thread_in_core;
598 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
603 * bool first_in_core, first_in_subcore, winkle_state_lost;
605 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
606 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
608 * core_idle_state |= thread_in_core;
610 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
611 * core_idle_state |= THREAD_WINKLE_BITS;
612 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
614 * winkle_state_lost = core_idle_state &
615 * (thread_in_core << WINKLE_THREAD_SHIFT);
616 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
620 cmpwi r18,PNV_THREAD_WINKLE
622 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
623 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
625 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
627 /* Shift thread bit to winkle mask, then test if this thread is set,
628 * and remove it from the winkle bits */
632 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
634 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
636 cmpwi r4,0 /* Check if first in subcore */
638 or r15,r15,r7 /* Set thread bit */
639 beq first_thread_in_subcore
640 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
642 or r15,r15,r7 /* Set thread bit */
643 beq cr2,first_thread_in_core
645 /* Not first thread in core or subcore to wake up */
648 first_thread_in_subcore:
650 * If waking up from sleep, subcore state is not lost. Hence
651 * skip subcore state restore
653 blt cr4,subcore_state_restored
655 /* Restore per-subcore state */
664 subcore_state_restored:
666 * Check if the thread is also the first thread in the core. If not,
667 * skip to clear_lock.
671 first_thread_in_core:
674 * First thread in the core waking up from any state which can cause
675 * partial or complete hypervisor state loss. It needs to
676 * call the fastsleep workaround code if the platform requires it.
677 * Call it unconditionally here. The below branch instruction will
678 * be patched out if the platform does not have fastsleep or does not
679 * require the workaround. Patching will be performed during the
680 * discovery of idle-states.
682 .global pnv_fastsleep_workaround_at_exit
683 pnv_fastsleep_workaround_at_exit:
684 b fastsleep_workaround_at_exit
688 * Use cr3 which indicates that we are waking up with atleast partial
689 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
691 ble cr3,.Ltb_resynced
692 /* Time base re-sync */
693 bl opal_resync_timebase;
695 * If waking up from sleep (POWER8), per core state
696 * is not lost, skip to clear_lock.
702 * First thread in the core to wake up and its waking up with
703 * complete hypervisor state loss. Restore per core hypervisor
711 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
719 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
725 * Common to all threads.
727 * If waking up from sleep, hypervisor state is not lost. Hence
728 * skip hypervisor state restore.
730 blt cr4,hypervisor_state_restored
732 /* Waking up from winkle */
734 BEGIN_MMU_FTR_SECTION
736 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
737 /* Restore SLB from PACA */
738 ld r8,PACA_SLBSHADOWPTR(r13)
741 li r3, SLBSHADOW_SAVEAREA
745 andis. r7,r5,SLB_ESID_V@h
752 /* Restore per thread state */
763 /* Call cur_cpu_spec->cpu_restore() */
764 LOAD_REG_ADDR(r4, cur_cpu_spec)
766 ld r12,CPU_SPEC_RESTORE(r4)
767 #ifdef PPC64_ELF_ABI_v1
776 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
777 hypervisor_state_restored:
781 blr /* return to pnv_powersave_wakeup */
783 fastsleep_workaround_at_exit:
786 bl opal_config_cpu_idle_state
790 * R3 here contains the value that will be returned to the caller
792 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
794 .global pnv_wakeup_loss
799 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
805 addi r1,r1,INT_FRAME_SIZE
812 * R3 here contains the value that will be returned to the caller
814 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
817 lbz r0,PACA_NAPSTATELOST(r13)
823 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
827 addi r1,r1,INT_FRAME_SIZE