3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/sys.h>
25 #include <linux/threads.h>
29 #include <asm/cputable.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/unistd.h>
34 #include <asm/ftrace.h>
35 #include <asm/ptrace.h>
36 #include <asm/export.h>
39 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
41 #if MSR_KERNEL >= 0x10000
42 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
44 #define LOAD_MSR_KERNEL(r, x) li r,(x)
48 .globl mcheck_transfer_to_handler
49 mcheck_transfer_to_handler:
56 .globl debug_transfer_to_handler
57 debug_transfer_to_handler:
64 .globl crit_transfer_to_handler
65 crit_transfer_to_handler:
66 #ifdef CONFIG_PPC_BOOK3E_MMU
77 #ifdef CONFIG_PHYS_64BIT
80 #endif /* CONFIG_PHYS_64BIT */
81 #endif /* CONFIG_PPC_BOOK3E_MMU */
91 /* set the stack limit to the current stack
92 * and set the limit to protect the thread_info
95 mfspr r8,SPRN_SPRG_THREAD
97 stw r0,SAVED_KSP_LIMIT(r11)
98 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
104 .globl crit_transfer_to_handler
105 crit_transfer_to_handler:
111 stw r0,crit_srr0@l(0)
113 stw r0,crit_srr1@l(0)
115 /* set the stack limit to the current stack
116 * and set the limit to protect the thread_info
119 mfspr r8,SPRN_SPRG_THREAD
121 stw r0,saved_ksp_limit@l(0)
122 rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
128 * This code finishes saving the registers to the exception frame
129 * and jumps to the appropriate handler for the exception, turning
130 * on address translation.
131 * Note that we rely on the caller having set cr0.eq iff the exception
132 * occurred in kernel mode (i.e. MSR:PR = 0).
134 .globl transfer_to_handler_full
135 transfer_to_handler_full:
139 .globl transfer_to_handler
149 mfspr r12,SPRN_SPRG_THREAD
151 tovirt(r2,r2) /* set r2 to current */
152 beq 2f /* if from user, fix up THREAD.regs */
153 addi r11,r1,STACK_FRAME_OVERHEAD
155 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
156 /* Check to see if the dbcr0 register is set up to debug. Use the
157 internal debug mode bit to do this. */
158 lwz r12,THREAD_DBCR0(r12)
159 andis. r12,r12,DBCR0_IDM@h
161 /* From user and task is ptraced - load up global dbcr0 */
162 li r12,-1 /* clear all pending debug events */
164 lis r11,global_dbcr0@ha
166 addi r11,r11,global_dbcr0@l
168 CURRENT_THREAD_INFO(r9, r1)
179 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
180 CURRENT_THREAD_INFO(r9, r1)
182 ACCOUNT_CPU_USER_ENTRY(r9, r11, r12)
187 2: /* if from kernel, check interrupted DOZE/NAP mode and
188 * check for stack overflow
190 lwz r9,KSP_LIMIT(r12)
191 cmplw r1,r9 /* if r1 <= ksp_limit */
192 ble- stack_ovf /* then the kernel stack overflowed */
194 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
195 CURRENT_THREAD_INFO(r9, r1)
196 tophys(r9,r9) /* check local flags */
197 lwz r12,TI_LOCAL_FLAGS(r9)
199 bt- 31-TLF_NAPPING,4f
200 bt- 31-TLF_SLEEPING,7f
201 #endif /* CONFIG_6xx || CONFIG_E500 */
202 .globl transfer_to_handler_cont
203 transfer_to_handler_cont:
206 lwz r11,0(r9) /* virtual address of handler */
207 lwz r9,4(r9) /* where to go when done */
208 #ifdef CONFIG_PPC_8xx_PERF_EVENT
211 #ifdef CONFIG_TRACE_IRQFLAGS
212 lis r12,reenable_mmu@h
213 ori r12,r12,reenable_mmu@l
218 reenable_mmu: /* re-enable mmu so we can */
222 andi. r10,r10,MSR_EE /* Did EE change? */
226 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
227 * If from user mode there is only one stack frame on the stack, and
228 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
229 * stack frame to make trace_hardirqs_off happy.
231 * This is handy because we also need to save a bunch of GPRs,
232 * r3 can be different from GPR3(r1) at this point, r9 and r11
233 * contains the old MSR and handler address respectively,
234 * r4 & r5 can contain page fault arguments that need to be passed
235 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
236 * they aren't useful past this point (aren't syscall arguments),
237 * the rest is restored from the exception frame.
245 bl trace_hardirqs_off
258 bctr /* jump to handler */
259 #else /* CONFIG_TRACE_IRQFLAGS */
264 RFI /* jump to handler, enable MMU */
265 #endif /* CONFIG_TRACE_IRQFLAGS */
267 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
268 4: rlwinm r12,r12,0,~_TLF_NAPPING
269 stw r12,TI_LOCAL_FLAGS(r9)
270 b power_save_ppc32_restore
272 7: rlwinm r12,r12,0,~_TLF_SLEEPING
273 stw r12,TI_LOCAL_FLAGS(r9)
274 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
275 rlwinm r9,r9,0,~MSR_EE
276 lwz r12,_LINK(r11) /* and return to address in LR */
277 b fast_exception_return
281 * On kernel stack overflow, load up an initial stack pointer
282 * and call StackOverflow(regs), which should not return.
285 /* sometimes we use a statically-allocated stack, which is OK. */
289 ble 5b /* r1 <= &_end is OK */
291 addi r3,r1,STACK_FRAME_OVERHEAD
292 lis r1,init_thread_union@ha
293 addi r1,r1,init_thread_union@l
294 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
295 lis r9,StackOverflow@ha
296 addi r9,r9,StackOverflow@l
297 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
298 #ifdef CONFIG_PPC_8xx_PERF_EVENT
307 * Handle a system call.
309 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
310 .stabs "entry_32.S",N_SO,0,0,0f
317 lwz r11,_CCR(r1) /* Clear SO bit in CR */
320 #ifdef CONFIG_TRACE_IRQFLAGS
321 /* Return from syscalls can (and generally will) hard enable
322 * interrupts. You aren't supposed to call a syscall with
323 * interrupts disabled in the first place. However, to ensure
324 * that we get it right vs. lockdep if it happens, we force
325 * that hard enable here with appropriate tracing if we see
326 * that we have been called with interrupts off
331 /* We came in with interrupts disabled, we enable them now */
344 #endif /* CONFIG_TRACE_IRQFLAGS */
345 CURRENT_THREAD_INFO(r10, r1)
346 lwz r11,TI_FLAGS(r10)
347 andi. r11,r11,_TIF_SYSCALL_DOTRACE
349 syscall_dotrace_cont:
350 cmplwi 0,r0,NR_syscalls
351 lis r10,sys_call_table@h
352 ori r10,r10,sys_call_table@l
355 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
357 addi r9,r1,STACK_FRAME_OVERHEAD
359 blrl /* Call handler */
360 .globl ret_from_syscall
363 CURRENT_THREAD_INFO(r12, r1)
364 /* disable interrupts so current_thread_info()->flags can't change */
365 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
366 /* Note: We don't bother telling lockdep about it */
371 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
372 bne- syscall_exit_work
374 blt+ syscall_exit_cont
375 lwz r11,_CCR(r1) /* Load CR */
377 oris r11,r11,0x1000 /* Set SO bit in CR */
381 #ifdef CONFIG_TRACE_IRQFLAGS
382 /* If we are going to return from the syscall with interrupts
383 * off, we trace that here. It shouldn't happen though but we
384 * want to catch the bugger if it does right ?
389 bl trace_hardirqs_off
392 #endif /* CONFIG_TRACE_IRQFLAGS */
393 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
394 /* If the process has its own DBCR0 value, load it up. The internal
395 debug mode bit tells us that dbcr0 should be loaded. */
396 lwz r0,THREAD+THREAD_DBCR0(r2)
397 andis. r10,r0,DBCR0_IDM@h
401 BEGIN_MMU_FTR_SECTION
402 lis r4,icache_44x_need_flush@ha
403 lwz r5,icache_44x_need_flush@l(r4)
407 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
408 #endif /* CONFIG_44x */
411 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
412 stwcx. r0,0,r1 /* to clear the reservation */
413 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
416 CURRENT_THREAD_INFO(r4, r1)
417 ACCOUNT_CPU_USER_EXIT(r4, r5, r7)
427 #ifdef CONFIG_PPC_8xx_PERF_EVENT
437 stw r7,icache_44x_need_flush@l(r4)
439 #endif /* CONFIG_44x */
451 .globl ret_from_kernel_thread
452 ret_from_kernel_thread:
462 /* Traced system call support */
467 addi r3,r1,STACK_FRAME_OVERHEAD
468 bl do_syscall_trace_enter
470 * Restore argument registers possibly just changed.
471 * We use the return value of do_syscall_trace_enter
472 * for call number to look up in the table (r0).
483 cmplwi r0,NR_syscalls
484 /* Return code is already in r3 thanks to do_syscall_trace_enter() */
485 bge- ret_from_syscall
486 b syscall_dotrace_cont
489 andi. r0,r9,_TIF_RESTOREALL
495 andi. r0,r9,_TIF_NOERROR
497 lwz r11,_CCR(r1) /* Load CR */
499 oris r11,r11,0x1000 /* Set SO bit in CR */
502 1: stw r6,RESULT(r1) /* Save result */
503 stw r3,GPR3(r1) /* Update return value */
504 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
507 /* Clear per-syscall TIF flags if any are set. */
509 li r11,_TIF_PERSYSCALL_MASK
510 addi r12,r12,TI_FLAGS
513 #ifdef CONFIG_IBM405_ERR77
518 subi r12,r12,TI_FLAGS
520 4: /* Anything which requires enabling interrupts? */
521 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
524 /* Re-enable interrupts. There is no need to trace that with
525 * lockdep as we are supposed to have IRQs on at this point
531 /* Save NVGPRS if they're not saved already */
539 addi r3,r1,STACK_FRAME_OVERHEAD
540 bl do_syscall_trace_leave
541 b ret_from_except_full
544 * The fork/clone functions need to copy the full register set into
545 * the child process. Therefore we need to save all the nonvolatile
546 * registers (r13 - r31) before calling the C code.
552 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
553 stw r0,_TRAP(r1) /* register set saved */
560 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
561 stw r0,_TRAP(r1) /* register set saved */
568 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
569 stw r0,_TRAP(r1) /* register set saved */
572 .globl ppc_swapcontext
576 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
577 stw r0,_TRAP(r1) /* register set saved */
581 * Top-level page fault handling.
582 * This is in assembler because if do_page_fault tells us that
583 * it is a bad kernel page fault, we want to save the non-volatile
584 * registers before calling bad_page_fault.
586 .globl handle_page_fault
589 addi r3,r1,STACK_FRAME_OVERHEAD
598 addi r3,r1,STACK_FRAME_OVERHEAD
601 b ret_from_except_full
604 * This routine switches between two different tasks. The process
605 * state of one is saved on its kernel stack. Then the state
606 * of the other is restored from its kernel stack. The memory
607 * management hardware is updated to the second process's state.
608 * Finally, we can return to the second process.
609 * On entry, r3 points to the THREAD for the current task, r4
610 * points to the THREAD for the new task.
612 * This routine is always called with interrupts disabled.
614 * Note: there are two ways to get to the "going out" portion
615 * of this code; either by coming in via the entry (_switch)
616 * or via "fork" which must set up an environment equivalent
617 * to the "_switch" path. If you change this , you'll have to
618 * change the fork code also.
620 * The code which creates the new task context is in 'copy_thread'
621 * in arch/ppc/kernel/process.c
624 stwu r1,-INT_FRAME_SIZE(r1)
626 stw r0,INT_FRAME_SIZE+4(r1)
627 /* r3-r12 are caller saved -- Cort */
629 stw r0,_NIP(r1) /* Return to switch caller */
631 li r0,MSR_FP /* Disable floating-point */
632 #ifdef CONFIG_ALTIVEC
634 oris r0,r0,MSR_VEC@h /* Disable altivec */
635 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
636 stw r12,THREAD+THREAD_VRSAVE(r2)
637 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
638 #endif /* CONFIG_ALTIVEC */
641 oris r0,r0,MSR_SPE@h /* Disable SPE */
642 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
643 stw r12,THREAD+THREAD_SPEFSCR(r2)
644 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
645 #endif /* CONFIG_SPE */
646 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
654 stw r1,KSP(r3) /* Set old stack pointer */
657 /* We need a sync somewhere here to make sure that if the
658 * previous task gets rescheduled on another CPU, it sees all
659 * stores it has performed on this one.
662 #endif /* CONFIG_SMP */
665 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
666 lwz r1,KSP(r4) /* Load new stack pointer */
668 /* save the old current 'last' for return value */
670 addi r2,r4,-THREAD /* Update current */
672 #ifdef CONFIG_ALTIVEC
674 lwz r0,THREAD+THREAD_VRSAVE(r2)
675 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
676 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
677 #endif /* CONFIG_ALTIVEC */
680 lwz r0,THREAD+THREAD_SPEFSCR(r2)
681 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
682 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
683 #endif /* CONFIG_SPE */
687 /* r3-r12 are destroyed -- Cort */
690 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
692 addi r1,r1,INT_FRAME_SIZE
695 .globl fast_exception_return
696 fast_exception_return:
697 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
698 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
699 beq 1f /* if not, we've got problems */
702 2: REST_4GPRS(3, r11)
709 #ifdef CONFIG_PPC_8xx_PERF_EVENT
720 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
721 /* check if the exception happened in a restartable section */
722 1: lis r3,exc_exit_restart_end@ha
723 addi r3,r3,exc_exit_restart_end@l
726 lis r4,exc_exit_restart@ha
727 addi r4,r4,exc_exit_restart@l
730 lis r3,fee_restarts@ha
732 lwz r5,fee_restarts@l(r3)
734 stw r5,fee_restarts@l(r3)
735 mr r12,r4 /* restart at exc_exit_restart */
744 /* aargh, a nonrecoverable interrupt, panic */
745 /* aargh, we don't know which trap this is */
746 /* but the 601 doesn't implement the RI bit, so assume it's OK */
750 END_FTR_SECTION_IFSET(CPU_FTR_601)
753 addi r3,r1,STACK_FRAME_OVERHEAD
755 ori r10,r10,MSR_KERNEL@l
756 bl transfer_to_handler_full
757 .long nonrecoverable_exception
758 .long ret_from_except
761 .globl ret_from_except_full
762 ret_from_except_full:
766 .globl ret_from_except
768 /* Hard-disable interrupts so that current_thread_info()->flags
769 * can't change between when we test it and when we return
770 * from the interrupt. */
771 /* Note: We don't bother telling lockdep about it */
772 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
773 SYNC /* Some chip revs have problems here... */
774 MTMSRD(r10) /* disable interrupts */
776 lwz r3,_MSR(r1) /* Returning to user mode? */
780 user_exc_return: /* r10 contains MSR_KERNEL here */
781 /* Check current_thread_info()->flags */
782 CURRENT_THREAD_INFO(r9, r1)
784 andi. r0,r9,_TIF_USER_WORK_MASK
788 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
789 /* Check whether this process has its own DBCR0 value. The internal
790 debug mode bit tells us that dbcr0 should be loaded. */
791 lwz r0,THREAD+THREAD_DBCR0(r2)
792 andis. r10,r0,DBCR0_IDM@h
795 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
796 CURRENT_THREAD_INFO(r9, r1)
797 ACCOUNT_CPU_USER_EXIT(r9, r10, r11)
802 /* N.B. the only way to get here is from the beq following ret_from_except. */
804 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
805 CURRENT_THREAD_INFO(r9, r1)
807 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
810 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
813 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
814 mr r4,r1 /* src: current exception frame */
815 mr r1,r3 /* Reroute the trampoline frame to r1 */
817 /* Copy from the original to the trampoline. */
818 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
819 li r6,0 /* start offset: 0 */
826 /* Do real store operation to complete stwu */
830 /* Clear _TIF_EMULATE_STACK_STORE flag */
831 lis r11,_TIF_EMULATE_STACK_STORE@h
835 #ifdef CONFIG_IBM405_ERR77
842 #ifdef CONFIG_PREEMPT
843 /* check current_thread_info->preempt_count */
844 lwz r0,TI_PREEMPT(r9)
845 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
847 andi. r8,r8,_TIF_NEED_RESCHED
850 andi. r0,r3,MSR_EE /* interrupts off? */
851 beq restore /* don't schedule if so */
852 #ifdef CONFIG_TRACE_IRQFLAGS
853 /* Lockdep thinks irqs are enabled, we need to call
854 * preempt_schedule_irq with IRQs off, so we inform lockdep
855 * now that we -did- turn them off already
857 bl trace_hardirqs_off
859 1: bl preempt_schedule_irq
860 CURRENT_THREAD_INFO(r9, r1)
862 andi. r0,r3,_TIF_NEED_RESCHED
864 #ifdef CONFIG_TRACE_IRQFLAGS
865 /* And now, to properly rebalance the above, we tell lockdep they
866 * are being turned back on, which will happen when we return
870 #endif /* CONFIG_PREEMPT */
872 /* interrupts are hard-disabled at this point */
875 BEGIN_MMU_FTR_SECTION
877 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
878 lis r4,icache_44x_need_flush@ha
879 lwz r5,icache_44x_need_flush@l(r4)
884 stw r6,icache_44x_need_flush@l(r4)
886 #endif /* CONFIG_44x */
889 #ifdef CONFIG_TRACE_IRQFLAGS
890 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
891 * off in this assembly code while peeking at TI_FLAGS() and such. However
892 * we need to inform it if the exception turned interrupts off, and we
893 * are about to trun them back on.
895 * The problem here sadly is that we don't know whether the exceptions was
896 * one that turned interrupts off or not. So we always tell lockdep about
897 * turning them on here when we go back to wherever we came from with EE
898 * on, even if that may meen some redudant calls being tracked. Maybe later
899 * we could encode what the exception did somewhere or test the exception
900 * type in the pt_regs but that sounds overkill
905 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
906 * which is the stack frame here, we need to force a stack frame
907 * in case we came from user space.
918 #endif /* CONFIG_TRACE_IRQFLAGS */
933 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
934 stwcx. r0,0,r1 /* to clear the reservation */
936 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
937 andi. r10,r9,MSR_RI /* check if this exception occurred */
938 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
946 * Once we put values in SRR0 and SRR1, we are in a state
947 * where exceptions are not recoverable, since taking an
948 * exception will trash SRR0 and SRR1. Therefore we clear the
949 * MSR:RI bit to indicate this. If we do take an exception,
950 * we can't return to the point of the exception but we
951 * can restart the exception exit path at the label
952 * exc_exit_restart below. -- paulus
954 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
956 MTMSRD(r10) /* clear the RI bit */
957 .globl exc_exit_restart
960 #ifdef CONFIG_PPC_8xx_PERF_EVENT
967 .globl exc_exit_restart_end
968 exc_exit_restart_end:
972 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
974 * This is a bit different on 4xx/Book-E because it doesn't have
975 * the RI bit in the MSR.
976 * The TLB miss handler checks if we have interrupted
977 * the exception exit path and restarts it if so
978 * (well maybe one day it will... :).
985 .globl exc_exit_restart
994 .globl exc_exit_restart_end
995 exc_exit_restart_end:
998 b . /* prevent prefetch past rfi */
1001 * Returning from a critical interrupt in user mode doesn't need
1002 * to be any different from a normal exception. For a critical
1003 * interrupt in the kernel, we just return (without checking for
1004 * preemption) since the interrupt may have happened at some crucial
1005 * place (e.g. inside the TLB miss handler), and because we will be
1006 * running with r1 pointing into critical_stack, not the current
1007 * process's kernel stack (and therefore current_thread_info() will
1008 * give the wrong answer).
1009 * We have to restore various SPRs that may have been in use at the
1010 * time of the critical interrupt.
1014 #define PPC_40x_TURN_OFF_MSR_DR \
1015 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1016 * assume the instructions here are mapped by a pinned TLB entry */ \
1022 #define PPC_40x_TURN_OFF_MSR_DR
1025 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1028 andi. r3,r3,MSR_PR; \
1029 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1030 bne user_exc_return; \
1033 REST_4GPRS(3, r1); \
1034 REST_2GPRS(7, r1); \
1037 mtspr SPRN_XER,r10; \
1039 PPC405_ERR77(0,r1); \
1040 stwcx. r0,0,r1; /* to clear the reservation */ \
1041 lwz r11,_LINK(r1); \
1045 PPC_40x_TURN_OFF_MSR_DR; \
1048 mtspr SPRN_DEAR,r9; \
1049 mtspr SPRN_ESR,r10; \
1052 mtspr exc_lvl_srr0,r11; \
1053 mtspr exc_lvl_srr1,r12; \
1055 lwz r12,GPR12(r1); \
1056 lwz r10,GPR10(r1); \
1057 lwz r11,GPR11(r1); \
1059 PPC405_ERR77_SYNC; \
1061 b .; /* prevent prefetch past exc_lvl_rfi */
1063 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1064 lwz r9,_##exc_lvl_srr0(r1); \
1065 lwz r10,_##exc_lvl_srr1(r1); \
1066 mtspr SPRN_##exc_lvl_srr0,r9; \
1067 mtspr SPRN_##exc_lvl_srr1,r10;
1069 #if defined(CONFIG_PPC_BOOK3E_MMU)
1070 #ifdef CONFIG_PHYS_64BIT
1071 #define RESTORE_MAS7 \
1073 mtspr SPRN_MAS7,r11;
1075 #define RESTORE_MAS7
1076 #endif /* CONFIG_PHYS_64BIT */
1077 #define RESTORE_MMU_REGS \
1081 mtspr SPRN_MAS0,r9; \
1083 mtspr SPRN_MAS1,r10; \
1085 mtspr SPRN_MAS2,r11; \
1086 mtspr SPRN_MAS3,r9; \
1087 mtspr SPRN_MAS6,r10; \
1089 #elif defined(CONFIG_44x)
1090 #define RESTORE_MMU_REGS \
1092 mtspr SPRN_MMUCR,r9;
1094 #define RESTORE_MMU_REGS
1098 .globl ret_from_crit_exc
1100 mfspr r9,SPRN_SPRG_THREAD
1101 lis r10,saved_ksp_limit@ha;
1102 lwz r10,saved_ksp_limit@l(r10);
1104 stw r10,KSP_LIMIT(r9)
1105 lis r9,crit_srr0@ha;
1106 lwz r9,crit_srr0@l(r9);
1107 lis r10,crit_srr1@ha;
1108 lwz r10,crit_srr1@l(r10);
1110 mtspr SPRN_SRR1,r10;
1111 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1112 #endif /* CONFIG_40x */
1115 .globl ret_from_crit_exc
1117 mfspr r9,SPRN_SPRG_THREAD
1118 lwz r10,SAVED_KSP_LIMIT(r1)
1119 stw r10,KSP_LIMIT(r9)
1120 RESTORE_xSRR(SRR0,SRR1);
1122 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1124 .globl ret_from_debug_exc
1126 mfspr r9,SPRN_SPRG_THREAD
1127 lwz r10,SAVED_KSP_LIMIT(r1)
1128 stw r10,KSP_LIMIT(r9)
1129 lwz r9,THREAD_INFO-THREAD(r9)
1130 CURRENT_THREAD_INFO(r10, r1)
1131 lwz r10,TI_PREEMPT(r10)
1132 stw r10,TI_PREEMPT(r9)
1133 RESTORE_xSRR(SRR0,SRR1);
1134 RESTORE_xSRR(CSRR0,CSRR1);
1136 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1138 .globl ret_from_mcheck_exc
1139 ret_from_mcheck_exc:
1140 mfspr r9,SPRN_SPRG_THREAD
1141 lwz r10,SAVED_KSP_LIMIT(r1)
1142 stw r10,KSP_LIMIT(r9)
1143 RESTORE_xSRR(SRR0,SRR1);
1144 RESTORE_xSRR(CSRR0,CSRR1);
1145 RESTORE_xSRR(DSRR0,DSRR1);
1147 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1148 #endif /* CONFIG_BOOKE */
1151 * Load the DBCR0 value for a task that is being ptraced,
1152 * having first saved away the global DBCR0. Note that r0
1153 * has the dbcr0 value to set upon entry to this.
1156 mfmsr r10 /* first disable debug exceptions */
1157 rlwinm r10,r10,0,~MSR_DE
1160 mfspr r10,SPRN_DBCR0
1161 lis r11,global_dbcr0@ha
1162 addi r11,r11,global_dbcr0@l
1164 CURRENT_THREAD_INFO(r9, r1)
1175 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1183 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1185 do_work: /* r10 contains MSR_KERNEL here */
1186 andi. r0,r9,_TIF_NEED_RESCHED
1189 do_resched: /* r10 contains MSR_KERNEL here */
1190 /* Note: We don't need to inform lockdep that we are enabling
1191 * interrupts here. As far as it knows, they are already enabled
1195 MTMSRD(r10) /* hard-enable interrupts */
1198 /* Note: And we don't tell it we are disabling them again
1199 * neither. Those disable/enable cycles used to peek at
1200 * TI_FLAGS aren't advertised.
1202 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1204 MTMSRD(r10) /* disable interrupts */
1205 CURRENT_THREAD_INFO(r9, r1)
1207 andi. r0,r9,_TIF_NEED_RESCHED
1209 andi. r0,r9,_TIF_USER_WORK_MASK
1211 do_user_signal: /* r10 contains MSR_KERNEL here */
1214 MTMSRD(r10) /* hard-enable interrupts */
1215 /* save r13-r31 in the exception frame, if not already done */
1222 2: addi r3,r1,STACK_FRAME_OVERHEAD
1229 * We come here when we are at the end of handling an exception
1230 * that occurred at a place where taking an exception will lose
1231 * state information, such as the contents of SRR0 and SRR1.
1234 lis r10,exc_exit_restart_end@ha
1235 addi r10,r10,exc_exit_restart_end@l
1238 lis r11,exc_exit_restart@ha
1239 addi r11,r11,exc_exit_restart@l
1242 lis r10,ee_restarts@ha
1243 lwz r12,ee_restarts@l(r10)
1245 stw r12,ee_restarts@l(r10)
1246 mr r12,r11 /* restart at exc_exit_restart */
1248 3: /* OK, we can't recover, kill this process */
1249 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1252 END_FTR_SECTION_IFSET(CPU_FTR_601)
1259 4: addi r3,r1,STACK_FRAME_OVERHEAD
1260 bl nonrecoverable_exception
1261 /* shouldn't return */
1271 * PROM code for specific machines follows. Put it
1272 * here so it's easy to add arch-specific sections later.
1275 #ifdef CONFIG_PPC_RTAS
1277 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1278 * called with the MMU off.
1281 stwu r1,-INT_FRAME_SIZE(r1)
1283 stw r0,INT_FRAME_SIZE+4(r1)
1284 LOAD_REG_ADDR(r4, rtas)
1285 lis r6,1f@ha /* physical return address for rtas */
1289 lwz r8,RTASENTRY(r4)
1293 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1294 SYNC /* disable interrupts so SRR0/1 */
1295 MTMSRD(r0) /* don't get trashed */
1296 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1298 mtspr SPRN_SPRG_RTAS,r7
1303 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1304 lwz r9,8(r9) /* original msr value */
1305 addi r1,r1,INT_FRAME_SIZE
1307 mtspr SPRN_SPRG_RTAS,r0
1310 RFI /* return to caller */
1312 .globl machine_check_in_rtas
1313 machine_check_in_rtas:
1315 /* XXX load up BATs and panic */
1317 #endif /* CONFIG_PPC_RTAS */
1319 #ifdef CONFIG_FUNCTION_TRACER
1320 #ifdef CONFIG_DYNAMIC_FTRACE
1324 * It is required that _mcount on PPC32 must preserve the
1325 * link register. But we have r0 to play with. We use r0
1326 * to push the return address back to the caller of mcount
1327 * into the ctr register, restore the link register and
1328 * then jump back using the ctr register.
1336 _GLOBAL(ftrace_caller)
1338 /* r3 ends up with link register */
1339 subi r3, r3, MCOUNT_INSN_SIZE
1344 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1345 .globl ftrace_graph_call
1348 _GLOBAL(ftrace_graph_stub)
1350 MCOUNT_RESTORE_FRAME
1351 /* old link register ends up in ctr reg */
1359 subi r3, r3, MCOUNT_INSN_SIZE
1360 LOAD_REG_ADDR(r5, ftrace_trace_function)
1367 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1368 b ftrace_graph_caller
1370 MCOUNT_RESTORE_FRAME
1373 EXPORT_SYMBOL(_mcount)
1375 _GLOBAL(ftrace_stub)
1378 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1379 _GLOBAL(ftrace_graph_caller)
1380 /* load r4 with local address */
1382 subi r4, r4, MCOUNT_INSN_SIZE
1384 /* Grab the LR out of the caller stack frame */
1387 bl prepare_ftrace_return
1391 * prepare_ftrace_return gives us the address we divert to.
1392 * Change the LR in the callers stack frame to this.
1396 MCOUNT_RESTORE_FRAME
1397 /* old link register ends up in ctr reg */
1400 _GLOBAL(return_to_handler)
1401 /* need to save return values */
1408 bl ftrace_return_to_handler
1411 /* return value has real return address */
1419 /* Jump back to real return address */
1421 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1423 #endif /* CONFIG_FUNCTION_TRACER */