2 * This file contains low level CPU setup functions.
3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cache.h>
18 #include <asm/book3s/64/mmu-hash.h>
20 /* Entry: r3 = crap, r4 = ptr to cputable entry
22 * Note that we can be called twice for pseudo-PVRs
24 _GLOBAL(__setup_cpu_power7)
37 _GLOBAL(__restore_cpu_power7)
50 _GLOBAL(__setup_cpu_power8)
61 ori r3, r3, LPCR_PECEDH
66 bl __init_PMU_HV_ISA207
70 _GLOBAL(__restore_cpu_power8)
82 ori r3, r3, LPCR_PECEDH
87 bl __init_PMU_HV_ISA207
91 _GLOBAL(__setup_cpu_power9)
102 ori r3, r3, LPCR_PECEDH
103 ori r3, r3, LPCR_HVICE
111 _GLOBAL(__restore_cpu_power9)
123 ori r3, r3, LPCR_PECEDH
124 ori r3, r3, LPCR_HVICE
133 /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
137 ld r5,CPU_SPEC_FEATURES(r4)
138 LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
140 std r5,CPU_SPEC_FEATURES(r4)
144 /* Setup a sane LPCR:
145 * Called with initial LPCR in R3
147 * LPES = 0b01 (HSRR0/1 used for 0x500)
151 * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
152 * VRMASD = 0b10000 (L=1, LP=00)
154 * Other bits untouched for now
157 rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
158 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
160 rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
161 clrrdi r3,r3,1 /* clear HDICE */
163 rldimi r3,r5, LPCR_VC_SH, 0
165 rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
172 ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
178 ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
179 HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
184 * Clear the TLB using the specified IS form of tlbiel instruction
185 * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
188 li r6,POWER7_TLB_SETS
190 li r7,0xc00 /* IS field = 0b11 */
199 li r6,POWER8_TLB_SETS
201 li r7,0xc00 /* IS field = 0b11 */
210 li r6,POWER9_TLB_SETS_HASH
212 li r7,0xc00 /* IS field = 0b11 */
225 __init_PMU_HV_ISA207: