2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/stringify.h>
8 #include <asm/asm-compat.h>
9 #include <asm/processor.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/firmware.h>
12 #include <asm/feature-fixups.h>
13 #include <asm/extable.h>
17 #define SZL (BITS_PER_LONG/8)
20 * Macros for storing registers into and loading registers from
24 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
25 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
26 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
27 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
29 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
30 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
31 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
32 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); REST_10GPRS(22, base)
35 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
36 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
37 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
38 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
39 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
40 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
41 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
42 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
44 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
45 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
46 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
47 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
48 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
49 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
50 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
51 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
52 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
53 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
54 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
55 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
57 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
58 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
59 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
60 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
61 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
62 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
63 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
64 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
65 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
66 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
67 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
68 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
71 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
72 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
74 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
78 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
81 /* Save the lower 32 VSRs in the thread VSR region */
82 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
83 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
84 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
85 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
86 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
87 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
88 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
89 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
90 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
91 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
92 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
93 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
96 * b = base register for addressing, o = base offset from register of 1st EVR
97 * n = first EVR, s = scratch
99 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
100 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
101 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
102 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
103 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
104 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
105 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
106 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
107 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
108 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
109 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
110 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
112 /* Macros to adjust thread priority for hardware multithreading */
113 #define HMT_VERY_LOW or 31,31,31 # very low priority
114 #define HMT_LOW or 1,1,1
115 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
116 #define HMT_MEDIUM or 2,2,2
117 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
118 #define HMT_HIGH or 3,3,3
119 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only
126 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
127 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
132 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
133 * version below in the else case of the ifdef.
137 #define STACKFRAMESIZE 256
138 #define __STK_REG(i) (112 + ((i)-14)*8)
139 #define STK_REG(i) __STK_REG(__REG_##i)
141 #ifdef PPC64_ELF_ABI_v2
143 #define __STK_PARAM(i) (32 + ((i)-3)*8)
146 #define __STK_PARAM(i) (48 + ((i)-3)*8)
148 #define STK_PARAM(i) __STK_PARAM(__REG_##i)
150 #ifdef PPC64_ELF_ABI_v2
152 #define _GLOBAL(name) \
154 .type name,@function; \
158 #define _GLOBAL_TOC(name) \
160 .type name,@function; \
163 0: addis r2,r12,(.TOC.-0b)@ha; \
164 addi r2,r2,(.TOC.-0b)@l; \
165 .localentry name,.-name
171 #define XGLUE(a,b) a##b
172 #define GLUE(a,b) XGLUE(a,b)
174 #define _GLOBAL(name) \
177 .globl GLUE(.,name); \
178 .pushsection ".opd","aw"; \
180 .quad GLUE(.,name); \
181 .quad .TOC.@tocbase; \
184 .type GLUE(.,name),@function; \
187 #define _GLOBAL_TOC(name) _GLOBAL(name)
189 #define DOTSYM(a) GLUE(.,a)
200 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
204 #define _GLOBAL_TOC(name) _GLOBAL(name)
211 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
212 * section, which gets emitted at the end of regular text.
214 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
215 * a blacklist. The former is for core kprobe functions/data, the
216 * latter is for those that incdentially must be excluded from probing
217 * and allows them to be linked at more optimal location within text.
219 #ifdef CONFIG_KPROBES
220 #define _ASM_NOKPROBE_SYMBOL(entry) \
221 .pushsection "_kprobe_blacklist","aw"; \
225 #define _ASM_NOKPROBE_SYMBOL(entry)
228 #define FUNC_START(name) _GLOBAL(name)
229 #define FUNC_END(name)
232 * LOAD_REG_IMMEDIATE(rn, expr)
233 * Loads the value of the constant expression 'expr' into register 'rn'
234 * using immediate instructions only. Use this when it's important not
235 * to reference other data (i.e. on ppc64 when the TOC pointer is not
236 * valid) and when 'expr' is a constant or absolute address.
238 * LOAD_REG_ADDR(rn, name)
239 * Loads the address of label 'name' into register 'rn'. Use this when
240 * you don't particularly need immediate instructions only, but you need
241 * the whole address in one register (e.g. it's a structure address and
242 * you want to access various offsets within it). On ppc32 this is
243 * identical to LOAD_REG_IMMEDIATE.
245 * LOAD_REG_ADDR_PIC(rn, name)
246 * Loads the address of label 'name' into register 'run'. Use this when
247 * the kernel doesn't run at the linked or relocated address. Please
248 * note that this macro will clobber the lr register.
250 * LOAD_REG_ADDRBASE(rn, name)
252 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
253 * register 'rn'. ADDROFF(name) returns the remainder of the address as
254 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
255 * in size, so is suitable for use directly as an offset in load and store
256 * instructions. Use this when loading/storing a single word or less as:
257 * LOAD_REG_ADDRBASE(rX, name)
258 * ld rY,ADDROFF(name)(rX)
261 /* Be careful, this will clobber the lr register. */
262 #define LOAD_REG_ADDR_PIC(reg, name) \
265 addis reg,reg,(name - 0b)@ha; \
266 addi reg,reg,(name - 0b)@l;
268 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
269 #define __AS_ATHIGH high
271 #define __AS_ATHIGH h
274 .macro __LOAD_REG_IMMEDIATE_32 r, x
275 .if (\x) >= 0x8000 || (\x) < -0x8000
276 lis \r, (\x)@__AS_ATHIGH
277 .if (\x) & 0xffff != 0
285 .macro __LOAD_REG_IMMEDIATE r, x
286 .if (\x) >= 0x80000000 || (\x) < -0x80000000
287 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
289 .if (\x) & 0xffff0000 != 0
290 oris \r, \r, (\x)@__AS_ATHIGH
292 .if (\x) & 0xffff != 0
296 __LOAD_REG_IMMEDIATE_32 \r, \x
302 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
304 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
305 lis tmp, (expr)@highest; \
306 lis reg, (expr)@__AS_ATHIGH; \
307 ori tmp, tmp, (expr)@higher; \
308 ori reg, reg, (expr)@l; \
309 rldimi reg, tmp, 32, 0
311 #define LOAD_REG_ADDR(reg,name) \
314 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
315 #define ADDROFF(name) 0
317 /* offsets for stack frame layout */
322 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
324 #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \
326 addi reg,reg,(expr)@l;
328 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name)
330 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
331 #define ADDROFF(name) name@l
333 /* offsets for stack frame layout */
338 /* various errata or part fixups */
339 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
341 90: mfspr dest, SPRN_TBRL; \
342 BEGIN_FTR_SECTION_NESTED(96); \
345 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
347 #define MFTB(dest) MFTBL(dest)
350 #ifdef CONFIG_PPC_8xx
351 #define MFTBL(dest) mftb dest
352 #define MFTBU(dest) mftbu dest
354 #define MFTBL(dest) mfspr dest, SPRN_TBRL
355 #define MFTBU(dest) mfspr dest, SPRN_TBRU
361 #define TLBSYNC tlbsync; sync
365 #define MTOCRF(FXM, RS) \
366 BEGIN_FTR_SECTION_NESTED(848); \
368 FTR_SECTION_ELSE_NESTED(848); \
370 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
374 * This instruction is not implemented on the PPC 603 or 601; however, on
375 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
376 * All of these instructions exist in the 8xx, they have magical powers,
377 * and they must be used.
380 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
384 lis r4,KERNELBASE@h; \
394 #ifdef CONFIG_IBM440EP_ERR42
395 #define PPC440EP_ERR42 isync
397 #define PPC440EP_ERR42
400 /* The following stops all load and store data streams associated with stream
401 * ID (ie. streams created explicitly). The embedded and server mnemonics for
402 * dcbt are different so this must only be used for server.
404 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \
405 lis scratch,0x60000000@h; \
406 dcbt 0,scratch,0b01010
409 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
410 * keep the address intact to be compatible with code shared with
413 * On the other hand, I find it useful to have them behave as expected
414 * by their name (ie always do the addition) on 64-bit BookE
416 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
421 * We use addis to ensure compatibility with the "classic" ppc versions of
422 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
423 * converting the address in r0, and so this version has to do that too
424 * (i.e. set register rd to 0 when rs == 0).
426 #define tophys(rd,rs) \
429 #define tovirt(rd,rs) \
432 #elif defined(CONFIG_PPC64)
433 #define toreal(rd) /* we can access c000... in real mode */
436 #define tophys(rd,rs) \
439 #define tovirt(rd,rs) \
441 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
444 #define toreal(rd) tophys(rd,rd)
445 #define fromreal(rd) tovirt(rd,rd)
447 #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h
448 #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h
451 #ifdef CONFIG_PPC_BOOK3S_64
452 #define MTMSRD(r) mtmsrd r
453 #define MTMSR_EERI(reg) mtmsrd reg,1
455 #define MTMSRD(r) mtmsr r
456 #define MTMSR_EERI(reg) mtmsr reg
459 #endif /* __KERNEL__ */
461 /* The boring bits... */
463 /* Condition Register Bit Fields */
476 * General Purpose Registers (GPRs)
478 * The lower case r0-r31 should be used in preference to the upper
479 * case R0-R31 as they provide more error checking in the assembler.
480 * Use R0-31 only when really nessesary.
517 /* Floating Point Registers (FPRs) */
552 /* AltiVec Registers (VPRs) */
587 /* VSX Registers (VSRs) */
654 /* SPE Registers (EVPRs) */
689 /* some stab codes */
695 #define RFSCV .long 0x4c0000a4
698 * Create an endian fixup trampoline
700 * This starts with a "tdi 0,0,0x48" instruction which is
701 * essentially a "trap never", and thus akin to a nop.
703 * The opcode for this instruction read with the wrong endian
704 * however results in a b . + 8
706 * So essentially we use that trick to execute the following
707 * trampoline in "reverse endian" if we are running with the
708 * MSR_LE bit set the "wrong" way for whatever endianness the
709 * kernel is built for.
712 #ifdef CONFIG_PPC_BOOK3E
716 * This version may be used in HV or non-HV context.
717 * MSR[EE] must be disabled.
719 #define FIXUP_ENDIAN \
720 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
721 b 191f; /* Skip trampoline if endian is good */ \
722 .long 0xa600607d; /* mfmsr r11 */ \
723 .long 0x01006b69; /* xori r11,r11,1 */ \
724 .long 0x00004039; /* li r10,0 */ \
725 .long 0x6401417d; /* mtmsrd r10,1 */ \
726 .long 0x05009f42; /* bcl 20,31,$+4 */ \
727 .long 0xa602487d; /* mflr r10 */ \
728 .long 0x14004a39; /* addi r10,r10,20 */ \
729 .long 0xa6035a7d; /* mtsrr0 r10 */ \
730 .long 0xa6037b7d; /* mtsrr1 r11 */ \
731 .long 0x2400004c; /* rfid */ \
735 * This version that may only be used with MSR[HV]=1
736 * - Does not clear MSR[RI], so more robust.
737 * - Slightly smaller and faster.
739 #define FIXUP_ENDIAN_HV \
740 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
741 b 191f; /* Skip trampoline if endian is good */ \
742 .long 0xa600607d; /* mfmsr r11 */ \
743 .long 0x01006b69; /* xori r11,r11,1 */ \
744 .long 0x05009f42; /* bcl 20,31,$+4 */ \
745 .long 0xa602487d; /* mflr r10 */ \
746 .long 0x14004a39; /* addi r10,r10,20 */ \
747 .long 0xa64b5a7d; /* mthsrr0 r10 */ \
748 .long 0xa64b7b7d; /* mthsrr1 r11 */ \
749 .long 0x2402004c; /* hrfid */ \
752 #endif /* !CONFIG_PPC_BOOK3E */
754 #endif /* __ASSEMBLY__ */
756 #define SOFT_MASK_TABLE(_start, _end) \
757 stringify_in_c(.section __soft_mask_table,"a";)\
758 stringify_in_c(.balign 8;) \
759 stringify_in_c(.llong (_start);) \
760 stringify_in_c(.llong (_end);) \
761 stringify_in_c(.previous)
763 #define RESTART_TABLE(_start, _end, _target) \
764 stringify_in_c(.section __restart_table,"a";)\
765 stringify_in_c(.balign 8;) \
766 stringify_in_c(.llong (_start);) \
767 stringify_in_c(.llong (_end);) \
768 stringify_in_c(.llong (_target);) \
769 stringify_in_c(.previous)
771 #ifdef CONFIG_PPC_FSL_BOOK3E
772 #define BTB_FLUSH(reg) \
773 lis reg,BUCSR_INIT@h; \
774 ori reg,reg,BUCSR_INIT@l; \
775 mtspr SPRN_BUCSR,reg; \
778 #define BTB_FLUSH(reg)
779 #endif /* CONFIG_PPC_FSL_BOOK3E */
781 #endif /* _ASM_POWERPC_PPC_ASM_H */