3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
13 /* Memory mapped register */
14 #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
16 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
17 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
19 #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
22 #define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */
23 #define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */
24 #define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
25 #define OCM0_DSARC 0x001a /* OCM D-side address compare */
26 #define OCM0_DSCNTL 0x001b /* OCM D-side control */
27 #define CPC0_PLLMR 0x00b0 /* PLL mode register */
28 #define CPC0_CR0 0x00b1 /* chip control register 0 */
29 #define CPC0_CR1 0x00b2 /* chip control register 1 */
30 #define CPC0_PSR 0x00b4 /* chip pin strapping reg */
31 #define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */
32 #define CPC0_SR 0x00b8 /* Power management status */
33 #define CPC0_ER 0x00b9 /* Power management enable */
34 #define CPC0_FR 0x00ba /* Power management force */
35 #define CPC0_ECR 0x00aa /* edge conditioner register */
37 /* values for kiar register - indirect addressing of these regs */
38 #define KCONF 0x40 /* decompression core config register */
40 #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
41 #define PLLMR_FWD_DIV_BYPASS 0xE0000000
42 #define PLLMR_FWD_DIV_3 0xA0000000
43 #define PLLMR_FWD_DIV_4 0x80000000
44 #define PLLMR_FWD_DIV_6 0x40000000
46 #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
47 #define PLLMR_FB_DIV_1 0x02000000
48 #define PLLMR_FB_DIV_2 0x04000000
49 #define PLLMR_FB_DIV_3 0x06000000
50 #define PLLMR_FB_DIV_4 0x08000000
52 #define PLLMR_TUNING_MASK 0x01F80000
54 #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
55 #define PLLMR_CPU_PLB_DIV_1 0x00000000
56 #define PLLMR_CPU_PLB_DIV_2 0x00020000
57 #define PLLMR_CPU_PLB_DIV_3 0x00040000
58 #define PLLMR_CPU_PLB_DIV_4 0x00060000
60 #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
61 #define PLLMR_OPB_PLB_DIV_1 0x00000000
62 #define PLLMR_OPB_PLB_DIV_2 0x00008000
63 #define PLLMR_OPB_PLB_DIV_3 0x00010000
64 #define PLLMR_OPB_PLB_DIV_4 0x00018000
66 #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
67 #define PLLMR_PCI_PLB_DIV_1 0x00000000
68 #define PLLMR_PCI_PLB_DIV_2 0x00002000
69 #define PLLMR_PCI_PLB_DIV_3 0x00004000
70 #define PLLMR_PCI_PLB_DIV_4 0x00006000
72 #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
73 #define PLLMR_EXB_PLB_DIV_2 0x00000000
74 #define PLLMR_EXB_PLB_DIV_3 0x00000800
75 #define PLLMR_EXB_PLB_DIV_4 0x00001000
76 #define PLLMR_EXB_PLB_DIV_5 0x00001800
78 /* definitions for PPC405GPr (new mode strapping) */
79 #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
81 #define PSR_PLL_FWD_MASK 0xC0000000
82 #define PSR_PLL_FDBACK_MASK 0x30000000
83 #define PSR_PLL_TUNING_MASK 0x0E000000
84 #define PSR_PLB_CPU_MASK 0x01800000
85 #define PSR_OPB_PLB_MASK 0x00600000
86 #define PSR_PCI_PLB_MASK 0x00180000
87 #define PSR_EB_PLB_MASK 0x00060000
88 #define PSR_ROM_WIDTH_MASK 0x00018000
89 #define PSR_ROM_LOC 0x00004000
90 #define PSR_PCI_ASYNC_EN 0x00001000
91 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
92 #define PSR_PCI_ARBIT_EN 0x00000400
93 #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
95 #endif /* _PPC405GP_H_ */