2 * This control block defines the PACA which defines the processor
3 * specific data for each logical processor on the system.
4 * There are some pointers defined that are utilized by PLIC.
6 * C 2001 PPC 64 Team, IBM Corp
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
13 #ifndef _ASM_POWERPC_PACA_H
14 #define _ASM_POWERPC_PACA_H
19 #include <linux/string.h>
20 #include <asm/types.h>
21 #include <asm/lppaca.h>
24 #ifdef CONFIG_PPC_BOOK3E
25 #include <asm/exception-64e.h>
27 #include <asm/exception-64s.h>
29 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
30 #include <asm/kvm_book3s_asm.h>
32 #include <asm/accounting.h>
34 #include <asm/cpuidle.h>
36 register struct paca_struct *local_paca asm("r13");
38 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
39 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
41 * Add standard checks that preemption cannot occur when using get_paca():
42 * otherwise the paca_struct it points to may be the wrong one just after.
44 #define get_paca() ((void) debug_smp_processor_id(), local_paca)
46 #define get_paca() local_paca
49 #define get_lppaca() (get_paca()->lppaca_ptr)
50 #define get_slb_shadow() (get_paca()->slb_shadow_ptr)
55 * Defines the layout of the paca.
57 * This structure is not directly accessed by firmware or the service
61 #ifdef CONFIG_PPC_BOOK3S
63 * Because hw_cpu_id, unlike other paca fields, is accessed
64 * routinely from other CPUs (from the IRQ code), we stick to
65 * read-only (after boot) fields in the first cacheline to
66 * avoid cacheline bouncing.
69 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
70 #endif /* CONFIG_PPC_BOOK3S */
72 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
73 * load lock_token and paca_index with a single lwz
74 * instruction. They must travel together and be properly
78 u16 lock_token; /* Constant 0x8000, used in locks */
79 u16 paca_index; /* Logical processor number */
81 u16 paca_index; /* Logical processor number */
82 u16 lock_token; /* Constant 0x8000, used in locks */
85 u64 kernel_toc; /* Kernel TOC address */
86 u64 kernelbase; /* Base address of kernel */
87 u64 kernel_msr; /* MSR while running in kernel */
88 void *emergency_sp; /* pointer to emergency stack */
89 u64 data_offset; /* per cpu data offset */
90 s16 hw_cpu_id; /* Physical processor number */
91 u8 cpu_start; /* At startup, processor spins until */
92 /* this becomes non-zero. */
93 u8 kexec_state; /* set when kexec down has irqs off */
94 #ifdef CONFIG_PPC_STD_MMU_64
95 struct slb_shadow *slb_shadow_ptr;
96 struct dtl_entry *dispatch_log;
97 struct dtl_entry *dispatch_log_end;
98 #endif /* CONFIG_PPC_STD_MMU_64 */
99 u64 dscr_default; /* per-CPU default DSCR */
101 #ifdef CONFIG_PPC_STD_MMU_64
103 * Now, starting in cacheline 2, the exception save areas
105 /* used for most interrupts/exceptions */
106 u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
107 u64 exslb[EX_SIZE]; /* used for SLB/segment table misses
108 * on the linear mapping */
109 /* SLB related definitions */
112 u32 slb_cache[SLB_CACHE_ENTRIES];
113 #endif /* CONFIG_PPC_STD_MMU_64 */
115 #ifdef CONFIG_PPC_BOOK3E
116 u64 exgen[8] __aligned(0x40);
117 /* Keep pgd in the same cacheline as the start of extlb */
118 pgd_t *pgd __aligned(0x40); /* Current PGD */
119 pgd_t *kernel_pgd; /* Kernel PGD */
121 /* Shared by all threads of a core -- points to tcd of first thread */
122 struct tlb_core_data *tcd_ptr;
125 * We can have up to 3 levels of reentrancy in the TLB miss handler,
126 * in each of four exception levels (normal, crit, mcheck, debug).
128 u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
129 u64 exmc[8]; /* used for machine checks */
130 u64 excrit[8]; /* used for crit interrupts */
131 u64 exdbg[8]; /* used for debug interrupts */
133 /* Kernel stack pointers for use by special exceptions */
138 struct tlb_core_data tcd;
139 #endif /* CONFIG_PPC_BOOK3E */
141 #ifdef CONFIG_PPC_BOOK3S
142 mm_context_id_t mm_ctx_id;
143 #ifdef CONFIG_PPC_MM_SLICES
144 u64 mm_ctx_low_slices_psize;
145 unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
146 unsigned long addr_limit;
148 u16 mm_ctx_user_psize;
154 * then miscellaneous read-write fields
156 struct task_struct *__current; /* Pointer to current */
157 u64 kstack; /* Saved Kernel stack addr */
158 u64 stab_rr; /* stab/slb round-robin counter */
159 u64 saved_r1; /* r1 save for RTAS calls or PM */
160 u64 saved_msr; /* MSR saved here by enter_rtas */
161 u16 trap_save; /* Used when bad stack is encountered */
162 u8 soft_enabled; /* irq soft-enable flag */
163 u8 irq_happened; /* irq happened while soft-disabled */
164 u8 io_sync; /* writel() needs spin_unlock sync */
165 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
166 u8 nap_state_lost; /* NV GPR values lost in power7_idle */
167 u64 sprg_vdso; /* Saved user-visible sprg */
168 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
169 u64 tm_scratch; /* TM scratch area for reclaim */
172 #ifdef CONFIG_PPC_POWERNV
173 /* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */
174 u32 *core_idle_state_ptr;
175 u8 thread_idle_state; /* PNV_THREAD_RUNNING/NAP/SLEEP */
176 /* Mask to indicate thread id in core */
178 /* Mask to denote subcore sibling threads */
179 u8 subcore_sibling_mask;
181 * Pointer to an array which contains pointer
182 * to the sibling threads' paca.
184 struct paca_struct **thread_sibling_pacas;
185 /* The PSSCR value that the kernel requested before going to stop */
189 * Save area for additional SPRs that need to be
190 * saved/restored during cpuidle stop.
192 struct stop_sprs stop_sprs;
195 #ifdef CONFIG_PPC_STD_MMU_64
196 /* Non-maskable exceptions that are not performance critical */
197 u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */
198 u64 exmc[EX_SIZE]; /* used for machine checks */
200 #ifdef CONFIG_PPC_BOOK3S_64
201 /* Exclusive stacks for system reset and machine check exception. */
202 void *nmi_emergency_sp;
203 void *mc_emergency_sp;
205 u16 in_nmi; /* In nmi handler */
208 * Flag to check whether we are in machine check early handler
209 * and already using emergency stack.
212 u8 hmi_event_available; /* HMI event is available */
215 /* Stuff for accurate time accounting */
216 struct cpu_accounting_data accounting;
217 u64 dtl_ridx; /* read index in dispatch log */
218 struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */
220 #ifdef CONFIG_KVM_BOOK3S_HANDLER
221 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
222 /* We use this to store guest state in */
223 struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
225 struct kvmppc_host_state kvm_hstate;
226 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
228 * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
231 struct sibling_subcore_state *sibling_subcore_state;
236 extern void copy_mm_to_paca(struct mm_struct *mm);
237 extern struct paca_struct *paca;
238 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
239 extern void setup_paca(struct paca_struct *new_paca);
240 extern void allocate_pacas(void);
241 extern void free_unused_pacas(void);
243 #else /* CONFIG_PPC64 */
245 static inline void allocate_pacas(void) { };
246 static inline void free_unused_pacas(void) { };
248 #endif /* CONFIG_PPC64 */
250 #endif /* __KERNEL__ */
251 #endif /* _ASM_POWERPC_PACA_H */