2 * PowerNV OPAL definitions.
4 * Copyright 2011 IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
15 /****** Takeover interface ********/
17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
20 * This is exclusively used in prom_init.c
25 struct opal_takeover_args {
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
36 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
38 extern long opal_do_takeover(struct opal_takeover_args *args);
41 extern int opal_enter_rtas(struct rtas_args *args,
45 #endif /* __ASSEMBLY__ */
47 /****** OPAL APIs ******/
50 #define OPAL_SUCCESS 0
51 #define OPAL_PARAMETER -1
53 #define OPAL_PARTIAL -3
54 #define OPAL_CONSTRAINED -4
55 #define OPAL_CLOSED -5
56 #define OPAL_HARDWARE -6
57 #define OPAL_UNSUPPORTED -7
58 #define OPAL_PERMISSION -8
59 #define OPAL_NO_MEM -9
60 #define OPAL_RESOURCE -10
61 #define OPAL_INTERNAL_ERROR -11
62 #define OPAL_BUSY_EVENT -12
63 #define OPAL_HARDWARE_FROZEN -13
65 /* API Tokens (in r0) */
66 #define OPAL_CONSOLE_WRITE 1
67 #define OPAL_CONSOLE_READ 2
68 #define OPAL_RTC_READ 3
69 #define OPAL_RTC_WRITE 4
70 #define OPAL_CEC_POWER_DOWN 5
71 #define OPAL_CEC_REBOOT 6
72 #define OPAL_READ_NVRAM 7
73 #define OPAL_WRITE_NVRAM 8
74 #define OPAL_HANDLE_INTERRUPT 9
75 #define OPAL_POLL_EVENTS 10
76 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
77 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
78 #define OPAL_PCI_CONFIG_READ_BYTE 13
79 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
80 #define OPAL_PCI_CONFIG_READ_WORD 15
81 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
82 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
83 #define OPAL_PCI_CONFIG_WRITE_WORD 18
84 #define OPAL_SET_XIVE 19
85 #define OPAL_GET_XIVE 20
86 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
87 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
88 #define OPAL_PCI_EEH_FREEZE_STATUS 23
89 #define OPAL_PCI_SHPC 24
90 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
91 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
92 #define OPAL_PCI_PHB_MMIO_ENABLE 27
93 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
94 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
95 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
96 #define OPAL_PCI_SET_PE 31
97 #define OPAL_PCI_SET_PELTV 32
98 #define OPAL_PCI_SET_MVE 33
99 #define OPAL_PCI_SET_MVE_ENABLE 34
100 #define OPAL_PCI_GET_XIVE_REISSUE 35
101 #define OPAL_PCI_SET_XIVE_REISSUE 36
102 #define OPAL_PCI_SET_XIVE_PE 37
103 #define OPAL_GET_XIVE_SOURCE 38
104 #define OPAL_GET_MSI_32 39
105 #define OPAL_GET_MSI_64 40
106 #define OPAL_START_CPU 41
107 #define OPAL_QUERY_CPU_STATUS 42
108 #define OPAL_WRITE_OPPANEL 43
109 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
110 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
111 #define OPAL_PCI_RESET 49
112 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
113 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
114 #define OPAL_PCI_FENCE_PHB 52
115 #define OPAL_PCI_REINIT 53
116 #define OPAL_PCI_MASK_PE_ERROR 54
117 #define OPAL_SET_SLOT_LED_STATUS 55
118 #define OPAL_GET_EPOW_STATUS 56
119 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
120 #define OPAL_RESERVED1 58
121 #define OPAL_RESERVED2 59
122 #define OPAL_PCI_NEXT_ERROR 60
123 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
124 #define OPAL_PCI_POLL 62
125 #define OPAL_PCI_MSI_EOI 63
126 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
127 #define OPAL_XSCOM_READ 65
128 #define OPAL_XSCOM_WRITE 66
129 #define OPAL_LPC_READ 67
130 #define OPAL_LPC_WRITE 68
135 enum OpalVendorApiTokens {
136 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
139 enum OpalFreezeState {
140 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
141 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
142 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
143 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
144 OPAL_EEH_STOPPED_RESET = 4,
145 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
146 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
149 enum OpalEehFreezeActionToken {
150 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
151 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
152 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
155 enum OpalPciStatusToken {
156 OPAL_EEH_NO_ERROR = 0,
157 OPAL_EEH_IOC_ERROR = 1,
158 OPAL_EEH_PHB_ERROR = 2,
159 OPAL_EEH_PE_ERROR = 3,
160 OPAL_EEH_PE_MMIO_ERROR = 4,
161 OPAL_EEH_PE_DMA_ERROR = 5
164 enum OpalPciErrorSeverity {
165 OPAL_EEH_SEV_NO_ERROR = 0,
166 OPAL_EEH_SEV_IOC_DEAD = 1,
167 OPAL_EEH_SEV_PHB_DEAD = 2,
168 OPAL_EEH_SEV_PHB_FENCED = 3,
169 OPAL_EEH_SEV_PE_ER = 4,
173 enum OpalShpcAction {
174 OPAL_SHPC_GET_LINK_STATE = 0,
175 OPAL_SHPC_GET_SLOT_STATE = 1
178 enum OpalShpcLinkState {
179 OPAL_SHPC_LINK_DOWN = 0,
180 OPAL_SHPC_LINK_UP = 1
183 enum OpalMmioWindowType {
184 OPAL_M32_WINDOW_TYPE = 1,
185 OPAL_M64_WINDOW_TYPE = 2,
186 OPAL_IO_WINDOW_TYPE = 3
189 enum OpalShpcSlotState {
190 OPAL_SHPC_DEV_NOT_PRESENT = 0,
191 OPAL_SHPC_DEV_PRESENT = 1
194 enum OpalExceptionHandler {
195 OPAL_MACHINE_CHECK_HANDLER = 1,
196 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
197 OPAL_SOFTPATCH_HANDLER = 3
200 enum OpalPendingState {
201 OPAL_EVENT_OPAL_INTERNAL = 0x1,
202 OPAL_EVENT_NVRAM = 0x2,
203 OPAL_EVENT_RTC = 0x4,
204 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
205 OPAL_EVENT_CONSOLE_INPUT = 0x10,
206 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
207 OPAL_EVENT_ERROR_LOG = 0x40,
208 OPAL_EVENT_EPOW = 0x80,
209 OPAL_EVENT_LED_STATUS = 0x100,
210 OPAL_EVENT_PCI_ERROR = 0x200
213 /* Machine check related definitions */
214 enum OpalMCE_Version {
218 enum OpalMCE_Severity {
219 OpalMCE_SEV_NO_ERROR = 0,
220 OpalMCE_SEV_WARNING = 1,
221 OpalMCE_SEV_ERROR_SYNC = 2,
222 OpalMCE_SEV_FATAL = 3,
225 enum OpalMCE_Disposition {
226 OpalMCE_DISPOSITION_RECOVERED = 0,
227 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
230 enum OpalMCE_Initiator {
231 OpalMCE_INITIATOR_UNKNOWN = 0,
232 OpalMCE_INITIATOR_CPU = 1,
235 enum OpalMCE_ErrorType {
236 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
237 OpalMCE_ERROR_TYPE_UE = 1,
238 OpalMCE_ERROR_TYPE_SLB = 2,
239 OpalMCE_ERROR_TYPE_ERAT = 3,
240 OpalMCE_ERROR_TYPE_TLB = 4,
243 enum OpalMCE_UeErrorType {
244 OpalMCE_UE_ERROR_INDETERMINATE = 0,
245 OpalMCE_UE_ERROR_IFETCH = 1,
246 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
247 OpalMCE_UE_ERROR_LOAD_STORE = 3,
248 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
251 enum OpalMCE_SlbErrorType {
252 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
253 OpalMCE_SLB_ERROR_PARITY = 1,
254 OpalMCE_SLB_ERROR_MULTIHIT = 2,
257 enum OpalMCE_EratErrorType {
258 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
259 OpalMCE_ERAT_ERROR_PARITY = 1,
260 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
263 enum OpalMCE_TlbErrorType {
264 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
265 OpalMCE_TLB_ERROR_PARITY = 1,
266 OpalMCE_TLB_ERROR_MULTIHIT = 2,
269 enum OpalThreadStatus {
270 OPAL_THREAD_INACTIVE = 0x0,
271 OPAL_THREAD_STARTED = 0x1,
272 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
275 enum OpalPciBusCompare {
276 OpalPciBusAny = 0, /* Any bus number match */
277 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
278 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
279 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
280 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
281 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
282 OpalPciBusAll = 7, /* Match bus number exactly */
285 enum OpalDeviceCompare {
286 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
287 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
290 enum OpalFuncCompare {
291 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
292 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
300 enum OpalPeltvAction {
301 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
302 OPAL_ADD_PE_TO_DOMAIN = 1
305 enum OpalMveEnableAction {
306 OPAL_DISABLE_MVE = 0,
310 enum OpalPciResetAndReinitScope {
311 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
312 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
313 OPAL_PCI_IODA_TABLE_RESET = 6,
316 enum OpalPciResetState {
317 OPAL_DEASSERT_RESET = 0,
318 OPAL_ASSERT_RESET = 1
321 enum OpalPciMaskAction {
322 OPAL_UNMASK_ERROR_TYPE = 0,
323 OPAL_MASK_ERROR_TYPE = 1
326 enum OpalSlotLedType {
327 OPAL_SLOT_LED_ID_TYPE = 0,
328 OPAL_SLOT_LED_FAULT_TYPE = 1
332 OPAL_TURN_OFF_LED = 0,
333 OPAL_TURN_ON_LED = 1,
334 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
337 enum OpalEpowStatus {
340 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
341 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
345 * Address cycle types for LPC accesses. These also correspond
346 * to the content of the first cell of the "reg" property for
347 * device nodes on the LPC bus
349 enum OpalLPCAddressType {
355 struct opal_machine_check_event {
356 enum OpalMCE_Version version:8; /* 0x00 */
357 uint8_t in_use; /* 0x01 */
358 enum OpalMCE_Severity severity:8; /* 0x02 */
359 enum OpalMCE_Initiator initiator:8; /* 0x03 */
360 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
361 enum OpalMCE_Disposition disposition:8; /* 0x05 */
362 uint8_t reserved_1[2]; /* 0x06 */
363 uint64_t gpr3; /* 0x08 */
364 uint64_t srr0; /* 0x10 */
365 uint64_t srr1; /* 0x18 */
368 enum OpalMCE_UeErrorType ue_error_type:8;
369 uint8_t effective_address_provided;
370 uint8_t physical_address_provided;
371 uint8_t reserved_1[5];
372 uint64_t effective_address;
373 uint64_t physical_address;
374 uint8_t reserved_2[8];
378 enum OpalMCE_SlbErrorType slb_error_type:8;
379 uint8_t effective_address_provided;
380 uint8_t reserved_1[6];
381 uint64_t effective_address;
382 uint8_t reserved_2[16];
386 enum OpalMCE_EratErrorType erat_error_type:8;
387 uint8_t effective_address_provided;
388 uint8_t reserved_1[6];
389 uint64_t effective_address;
390 uint8_t reserved_2[16];
394 enum OpalMCE_TlbErrorType tlb_error_type:8;
395 uint8_t effective_address_provided;
396 uint8_t reserved_1[6];
397 uint64_t effective_address;
398 uint8_t reserved_2[16];
404 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
405 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
406 OPAL_P7IOC_DIAG_TYPE_BI = 2,
407 OPAL_P7IOC_DIAG_TYPE_CI = 3,
408 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
409 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
410 OPAL_P7IOC_DIAG_TYPE_LAST = 6
413 struct OpalIoP7IOCErrorData {
431 struct OpalIoP7IOCRgcErrorData {
432 uint64_t rgcStatus; /* 3E1C10 */
433 uint64_t rgcLdcp; /* 3E1C18 */
435 struct OpalIoP7IOCBiErrorData {
436 uint64_t biLdcp0; /* 3C0100, 3C0118 */
437 uint64_t biLdcp1; /* 3C0108, 3C0120 */
438 uint64_t biLdcp2; /* 3C0110, 3C0128 */
439 uint64_t biFenceStatus; /* 3C0130, 3C0130 */
441 uint8_t biDownbound; /* BI Downbound or Upbound */
443 struct OpalIoP7IOCCiErrorData {
444 uint64_t ciPortStatus; /* 3Dn008 */
445 uint64_t ciPortLdcp; /* 3Dn010 */
447 uint8_t ciPort; /* Index of CI port: 0/1 */
453 * This structure defines the overlay which will be used to store PHB error
457 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
461 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
465 OPAL_P7IOC_NUM_PEST_REGS = 128,
468 struct OpalIoPhbErrorCommon {
474 struct OpalIoP7IOCPhbErrorData {
475 struct OpalIoPhbErrorCommon common;
480 uint32_t portStatusReg;
481 uint32_t rootCmplxStatus;
482 uint32_t busAgentStatus;
485 uint32_t deviceStatus;
488 uint32_t devCmdStatus;
489 uint32_t devSecStatus;
492 uint32_t rootErrorStatus;
493 uint32_t uncorrErrorStatus;
494 uint32_t corrErrorStatus;
503 // Record data about the call to allocate a buffer.
507 //P7IOC MMIO Error Regs
508 uint64_t p7iocPlssr; // n120
509 uint64_t p7iocCsr; // n110
510 uint64_t lemFir; // nC00
511 uint64_t lemErrorMask; // nC18
512 uint64_t lemWOF; // nC40
513 uint64_t phbErrorStatus; // nC80
514 uint64_t phbFirstErrorStatus; // nC88
515 uint64_t phbErrorLog0; // nCC0
516 uint64_t phbErrorLog1; // nCC8
517 uint64_t mmioErrorStatus; // nD00
518 uint64_t mmioFirstErrorStatus; // nD08
519 uint64_t mmioErrorLog0; // nD40
520 uint64_t mmioErrorLog1; // nD48
521 uint64_t dma0ErrorStatus; // nD80
522 uint64_t dma0FirstErrorStatus; // nD88
523 uint64_t dma0ErrorLog0; // nDC0
524 uint64_t dma0ErrorLog1; // nDC8
525 uint64_t dma1ErrorStatus; // nE00
526 uint64_t dma1FirstErrorStatus; // nE08
527 uint64_t dma1ErrorLog0; // nE40
528 uint64_t dma1ErrorLog1; // nE48
529 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
530 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
533 typedef struct oppanel_line {
539 int64_t opal_console_write(int64_t term_number, int64_t *length,
540 const uint8_t *buffer);
541 int64_t opal_console_read(int64_t term_number, int64_t *length,
543 int64_t opal_console_write_buffer_space(int64_t term_number,
545 int64_t opal_rtc_read(uint32_t *year_month_day,
546 uint64_t *hour_minute_second_millisecond);
547 int64_t opal_rtc_write(uint32_t year_month_day,
548 uint64_t hour_minute_second_millisecond);
549 int64_t opal_cec_power_down(uint64_t request);
550 int64_t opal_cec_reboot(void);
551 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
552 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
553 int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
554 int64_t opal_poll_events(uint64_t *outstanding_event_mask);
555 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
556 uint64_t tce_mem_size);
557 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
558 uint64_t tce_mem_size);
559 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
560 uint64_t offset, uint8_t *data);
561 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
562 uint64_t offset, uint16_t *data);
563 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
564 uint64_t offset, uint32_t *data);
565 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
566 uint64_t offset, uint8_t data);
567 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
568 uint64_t offset, uint16_t data);
569 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
570 uint64_t offset, uint32_t data);
571 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
572 int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
573 int64_t opal_register_exception_handler(uint64_t opal_exception,
574 uint64_t handler_address,
575 uint64_t glue_cache_line);
576 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
577 uint8_t *freeze_state,
578 uint16_t *pci_error_type,
579 uint64_t *phb_status);
580 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
581 uint64_t eeh_action_token);
582 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
586 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
587 uint16_t window_num, uint16_t enable);
588 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
590 uint64_t starting_real_address,
591 uint64_t starting_pci_address,
592 uint16_t segment_size);
593 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
594 uint16_t window_type, uint16_t window_num,
595 uint16_t segment_num);
596 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
597 uint64_t ivt_addr, uint64_t ivt_len,
598 uint64_t reject_array_addr,
599 uint64_t peltv_addr);
600 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
601 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
603 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
605 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
606 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
608 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
609 uint8_t *p_bit, uint8_t *q_bit);
610 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
611 uint8_t p_bit, uint8_t q_bit);
612 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
613 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
615 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
616 int32_t *interrupt_source_number);
617 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
618 uint8_t msi_range, uint32_t *msi_address,
619 uint32_t *message_data);
620 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
621 uint32_t xive_num, uint8_t msi_range,
622 uint64_t *msi_address, uint32_t *message_data);
623 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
624 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
625 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
626 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
627 uint16_t tce_levels, uint64_t tce_table_addr,
628 uint64_t tce_table_size, uint64_t tce_page_size);
629 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
630 uint16_t dma_window_number, uint64_t pci_start_addr,
631 uint64_t pci_mem_size);
632 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
634 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
635 uint64_t diag_buffer_len);
636 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
637 uint64_t diag_buffer_len);
638 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
639 uint64_t diag_buffer_len);
640 int64_t opal_pci_fence_phb(uint64_t phb_id);
641 int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
642 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
643 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
644 int64_t opal_get_epow_status(uint64_t *status);
645 int64_t opal_set_system_attention_led(uint8_t led_action);
646 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
647 uint16_t *pci_error_type, uint16_t *severity);
648 int64_t opal_pci_poll(uint64_t phb_id);
650 int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val);
651 int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val);
653 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
654 uint32_t addr, uint32_t data, uint32_t sz);
655 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
656 uint32_t addr, uint32_t *data, uint32_t sz);
658 /* Internal functions */
659 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
661 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
662 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
664 extern void hvc_opal_init_early(void);
666 /* Internal functions */
667 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
668 int depth, void *data);
670 extern int opal_notifier_register(struct notifier_block *nb);
671 extern void opal_notifier_enable(void);
672 extern void opal_notifier_disable(void);
673 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
675 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
676 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
678 extern void hvc_opal_init_early(void);
681 extern int opal_set_rtc_time(struct rtc_time *tm);
682 extern void opal_get_rtc_time(struct rtc_time *tm);
683 extern unsigned long opal_get_boot_time(void);
684 extern void opal_nvram_init(void);
686 extern int opal_machine_check(struct pt_regs *regs);
688 extern void opal_shutdown(void);
690 extern void opal_lpc_init(void);
692 #endif /* __ASSEMBLY__ */
694 #endif /* __OPAL_H */