1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H
3 #define _ASM_POWERPC_NOHASH_32_PGTABLE_H
5 #define __ARCH_USE_5LEVEL_HACK
6 #include <asm-generic/pgtable-nopmd.h>
9 #include <linux/sched.h>
10 #include <linux/threads.h>
11 #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
13 extern unsigned long ioremap_bot;
16 extern int icache_44x_need_flush;
19 #endif /* __ASSEMBLY__ */
21 #define PTE_INDEX_SIZE PTE_SHIFT
22 #define PMD_INDEX_SIZE 0
23 #define PUD_INDEX_SIZE 0
24 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
26 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
27 #define PUD_CACHE_INDEX PUD_INDEX_SIZE
30 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
31 #define PMD_TABLE_SIZE 0
32 #define PUD_TABLE_SIZE 0
33 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
34 #endif /* __ASSEMBLY__ */
36 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
37 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
40 * The normal case is that PTEs are 32-bits and we have a 1-page
41 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
43 * For any >32-bit physical address platform, we can use the following
44 * two level page table layout where the pgdir is 8KB and the MS 13 bits
45 * are an index to the second level table. The combined pgdir/pmd first
46 * level has 2048 entries and the second level has 512 64-bit PTE entries.
49 /* PGDIR_SHIFT determines what a top-level page table entry can map */
50 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
51 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
52 #define PGDIR_MASK (~(PGDIR_SIZE-1))
54 /* Bits to mask out from a PGD to get to the PUD page */
55 #define PGD_MASKED_BITS 0
57 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
58 #define FIRST_USER_ADDRESS 0UL
60 #define pte_ERROR(e) \
61 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
62 (unsigned long long)pte_val(e))
63 #define pgd_ERROR(e) \
64 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
67 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
68 * value (for now) on others, from where we can start layout kernel
69 * virtual space that goes below PKMAP and FIXMAP
72 #define KVIRT_TOP PKMAP_BASE
74 #define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */
78 * ioremap_bot starts at that address. Early ioremaps move down from there,
79 * until mem_init() at which point this becomes the top of the vmalloc
82 #ifdef CONFIG_NOT_COHERENT_CACHE
83 #define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
85 #define IOREMAP_TOP KVIRT_TOP
89 * Just any arbitrary offset to the start of the vmalloc VM area: the
90 * current 16MB value just means that there will be a 64MB "hole" after the
91 * physical memory until the kernel virtual memory starts. That means that
92 * any out-of-bounds memory accesses will hopefully be caught.
93 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
94 * area for the same reason. ;)
96 * We no longer map larger than phys RAM with the BATs so we don't have
97 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
98 * about clashes between our early calls to ioremap() that start growing down
99 * from IOREMAP_TOP being run into the VM area allocations (growing upwards
100 * from VMALLOC_START). For this reason we have ioremap_bot to check when
101 * we actually run into our mappings setup in the early boot with the VM
102 * system. This really does become a problem for machines with good amounts
105 #define VMALLOC_OFFSET (0x1000000) /* 16M */
107 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
109 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
111 #define VMALLOC_END ioremap_bot
114 * Bits in a linux-style PTE. These match the bits in the
115 * (hardware-defined) PowerPC PTE as closely as possible.
118 #if defined(CONFIG_40x)
119 #include <asm/nohash/32/pte-40x.h>
120 #elif defined(CONFIG_44x)
121 #include <asm/nohash/32/pte-44x.h>
122 #elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
123 #include <asm/nohash/pte-book3e.h>
124 #elif defined(CONFIG_FSL_BOOKE)
125 #include <asm/nohash/32/pte-fsl-booke.h>
126 #elif defined(CONFIG_PPC_8xx)
127 #include <asm/nohash/32/pte-8xx.h>
130 /* And here we include common definitions */
131 #include <asm/pte-common.h>
135 #define pte_clear(mm, addr, ptep) \
136 do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
138 #define pmd_none(pmd) (!pmd_val(pmd))
139 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
140 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
141 static inline void pmd_clear(pmd_t *pmdp)
149 * When flushing the tlb entry for a page, we also need to flush the hash
150 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
152 extern int flush_hash_pages(unsigned context, unsigned long va,
153 unsigned long pmdval, int count);
155 /* Add an HPTE to the hash table */
156 extern void add_hash_page(unsigned context, unsigned long va,
157 unsigned long pmdval);
159 /* Flush an entry from the TLB/hash table */
160 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
161 unsigned long address);
164 * PTE updates. This function is called whenever an existing
165 * valid PTE is updated. This does -not- include set_pte_at()
166 * which nowadays only sets a new PTE.
168 * Depending on the type of MMU, we may need to use atomic updates
169 * and the PTE may be either 32 or 64 bit wide. In the later case,
170 * when using atomic updates, only the low part of the PTE is
171 * accessed atomically.
173 * In addition, on 44x, we also maintain a global flag indicating
174 * that an executable user mapping was modified, which is needed
175 * to properly flush the virtually tagged instruction cache of
176 * those implementations.
178 #ifndef CONFIG_PTE_64BIT
179 static inline unsigned long pte_update(pte_t *p,
183 #ifdef PTE_ATOMIC_UPDATES
184 unsigned long old, tmp;
186 __asm__ __volatile__("\
193 : "=&r" (old), "=&r" (tmp), "=m" (*p)
194 : "r" (p), "r" (clr), "r" (set), "m" (*p)
196 #else /* PTE_ATOMIC_UPDATES */
197 unsigned long old = pte_val(*p);
198 *p = __pte((old & ~clr) | set);
199 #endif /* !PTE_ATOMIC_UPDATES */
202 if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
203 icache_44x_need_flush = 1;
207 #else /* CONFIG_PTE_64BIT */
208 static inline unsigned long long pte_update(pte_t *p,
212 #ifdef PTE_ATOMIC_UPDATES
213 unsigned long long old;
216 __asm__ __volatile__("\
224 : "=&r" (old), "=&r" (tmp), "=m" (*p)
225 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
227 #else /* PTE_ATOMIC_UPDATES */
228 unsigned long long old = pte_val(*p);
229 *p = __pte((old & ~(unsigned long long)clr) | set);
230 #endif /* !PTE_ATOMIC_UPDATES */
233 if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
234 icache_44x_need_flush = 1;
238 #endif /* CONFIG_PTE_64BIT */
241 * 2.6 calls this without flushing the TLB entry; this is wrong
242 * for our hash-based implementation, we fix that up here.
244 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
245 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
248 old = pte_update(ptep, _PAGE_ACCESSED, 0);
249 #if _PAGE_HASHPTE != 0
250 if (old & _PAGE_HASHPTE) {
251 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
252 flush_hash_pages(context, addr, ptephys, 1);
255 return (old & _PAGE_ACCESSED) != 0;
257 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
258 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
260 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
261 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
264 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
267 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
268 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
271 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), _PAGE_RO);
273 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
274 unsigned long addr, pte_t *ptep)
276 ptep_set_wrprotect(mm, addr, ptep);
280 static inline void __ptep_set_access_flags(struct mm_struct *mm,
281 pte_t *ptep, pte_t entry,
282 unsigned long address)
284 unsigned long set = pte_val(entry) &
285 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
286 unsigned long clr = ~pte_val(entry) & (_PAGE_RO | _PAGE_NA);
288 pte_update(ptep, clr, set);
291 #define __HAVE_ARCH_PTE_SAME
292 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
295 * Note that on Book E processors, the pmd contains the kernel virtual
296 * (lowmem) address of the pte page. The physical address is less useful
297 * because everything runs with translation enabled (even the TLB miss
298 * handler). On everything else the pmd contains the physical address
299 * of the pte page. -- paulus
302 #define pmd_page_vaddr(pmd) \
303 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
304 #define pmd_page(pmd) \
305 pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
307 #define pmd_page_vaddr(pmd) \
308 ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
309 #define pmd_page(pmd) \
310 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
313 /* to find an entry in a kernel page-table-directory */
314 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
316 /* to find an entry in a page-table-directory */
317 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
318 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
320 /* Find an entry in the third-level page table.. */
321 #define pte_index(address) \
322 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
323 #define pte_offset_kernel(dir, addr) \
324 (pmd_bad(*(dir)) ? NULL : (pte_t *)pmd_page_vaddr(*(dir)) + \
326 #define pte_offset_map(dir, addr) \
327 ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
328 #define pte_unmap(pte) kunmap_atomic(pte)
331 * Encode and decode a swap entry.
332 * Note that the bits we use in a PTE for representing a swap entry
333 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used).
336 #define __swp_type(entry) ((entry).val & 0x1f)
337 #define __swp_offset(entry) ((entry).val >> 5)
338 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) })
339 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
340 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
342 int map_kernel_page(unsigned long va, phys_addr_t pa, int flags);
344 #endif /* !__ASSEMBLY__ */
346 #endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */