1 #ifndef _ASM_POWERPC_IO_H
2 #define _ASM_POWERPC_IO_H
5 #define ARCH_HAS_IOREMAP_WC
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
22 * has legacy ISA devices ?
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL)
27 #include <linux/device.h>
30 #include <linux/compiler.h>
32 #include <asm/byteorder.h>
33 #include <asm/synch.h>
34 #include <asm/delay.h>
37 #include <asm-generic/iomap.h>
43 #define SIO_CONFIG_RA 0x398
44 #define SIO_CONFIG_RD 0x399
48 /* 32 bits uses slightly different variables for the various IO
49 * bases. Most of this file only uses _IO_BASE though which we
50 * define properly based on the platform
54 #define _ISA_MEM_BASE 0
55 #define PCI_DRAM_OFFSET 0
56 #elif defined(CONFIG_PPC32)
57 #define _IO_BASE isa_io_base
58 #define _ISA_MEM_BASE isa_mem_base
59 #define PCI_DRAM_OFFSET pci_dram_offset
61 #define _IO_BASE pci_io_base
62 #define _ISA_MEM_BASE isa_mem_base
63 #define PCI_DRAM_OFFSET 0
66 extern unsigned long isa_io_base;
67 extern unsigned long pci_io_base;
68 extern unsigned long pci_dram_offset;
70 extern resource_size_t isa_mem_base;
73 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
74 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
80 * Low level MMIO accessors
82 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
83 * specific and thus shouldn't be used in generic code. The accessors
86 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
87 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
88 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
90 * Those operate directly on a kernel virtual address. Note that the prototype
91 * for the out_* accessors has the arguments in opposite order from the usual
92 * linux PCI accessors. Unlike those, they take the address first and the value
95 * Note: I might drop the _ns suffix on the stream operations soon as it is
96 * simply normal for stream operations to not swap in the first place.
101 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
103 #define IO_SET_SYNC_FLAG()
106 /* gcc 4.0 and older doesn't have 'Z' constraint */
107 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
108 #define DEF_MMIO_IN_LE(name, size, insn) \
109 static inline u##size name(const volatile u##size __iomem *addr) \
112 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
113 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
117 #define DEF_MMIO_OUT_LE(name, size, insn) \
118 static inline void name(volatile u##size __iomem *addr, u##size val) \
120 __asm__ __volatile__("sync;"#insn" %1,0,%2" \
121 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
122 IO_SET_SYNC_FLAG(); \
124 #else /* newer gcc */
125 #define DEF_MMIO_IN_LE(name, size, insn) \
126 static inline u##size name(const volatile u##size __iomem *addr) \
129 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
130 : "=r" (ret) : "Z" (*addr) : "memory"); \
134 #define DEF_MMIO_OUT_LE(name, size, insn) \
135 static inline void name(volatile u##size __iomem *addr, u##size val) \
137 __asm__ __volatile__("sync;"#insn" %1,%y0" \
138 : "=Z" (*addr) : "r" (val) : "memory"); \
139 IO_SET_SYNC_FLAG(); \
143 #define DEF_MMIO_IN_BE(name, size, insn) \
144 static inline u##size name(const volatile u##size __iomem *addr) \
147 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
148 : "=r" (ret) : "m" (*addr) : "memory"); \
152 #define DEF_MMIO_OUT_BE(name, size, insn) \
153 static inline void name(volatile u##size __iomem *addr, u##size val) \
155 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
156 : "=m" (*addr) : "r" (val) : "memory"); \
157 IO_SET_SYNC_FLAG(); \
161 DEF_MMIO_IN_BE(in_8, 8, lbz);
162 DEF_MMIO_IN_BE(in_be16, 16, lhz);
163 DEF_MMIO_IN_BE(in_be32, 32, lwz);
164 DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
165 DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
167 DEF_MMIO_OUT_BE(out_8, 8, stb);
168 DEF_MMIO_OUT_BE(out_be16, 16, sth);
169 DEF_MMIO_OUT_BE(out_be32, 32, stw);
170 DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
171 DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
174 DEF_MMIO_OUT_BE(out_be64, 64, std);
175 DEF_MMIO_IN_BE(in_be64, 64, ld);
177 /* There is no asm instructions for 64 bits reverse loads and stores */
178 static inline u64 in_le64(const volatile u64 __iomem *addr)
180 return swab64(in_be64(addr));
183 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
185 out_be64(addr, swab64(val));
187 #endif /* __powerpc64__ */
190 * Low level IO stream instructions are defined out of line for now
192 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
193 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
194 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
195 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
196 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
197 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
199 /* The _ns naming is historical and will be removed. For now, just #define
200 * the non _ns equivalent names
202 #define _insw _insw_ns
203 #define _insl _insl_ns
204 #define _outsw _outsw_ns
205 #define _outsl _outsl_ns
209 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
212 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
213 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
215 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
220 * PCI and standard ISA accessors
222 * Those are globally defined linux accessors for devices on PCI or ISA
223 * busses. They follow the Linux defined semantics. The current implementation
224 * for PowerPC is as close as possible to the x86 version of these, and thus
225 * provides fairly heavy weight barriers for the non-raw versions
227 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
228 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
229 * own implementation of some or all of the accessors.
233 * Include the EEH definitions when EEH is enabled only so they don't get
234 * in the way when building for 32 bits
240 /* Shortcut to the MMIO argument pointer */
241 #define PCI_IO_ADDR volatile void __iomem *
243 /* Indirect IO address tokens:
245 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
246 * on all MMIOs. (Note that this is all 64 bits only for now)
248 * To help platforms who may need to differenciate MMIO addresses in
249 * their hooks, a bitfield is reserved for use by the platform near the
250 * top of MMIO addresses (not PIO, those have to cope the hard way).
252 * This bit field is 12 bits and is at the top of the IO virtual
253 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
255 * The kernel virtual space is thus:
257 * 0xD000000000000000 : vmalloc
258 * 0xD000080000000000 : PCI PHB IO space
259 * 0xD000080080000000 : ioremap
260 * 0xD0000fffffffffff : end of ioremap region
262 * Since the top 4 bits are reserved as the region ID, we use thus
263 * the next 12 bits and keep 4 bits available for the future if the
264 * virtual address space is ever to be extended.
266 * The direct IO mapping operations will then mask off those bits
267 * before doing the actual access, though that only happen when
268 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
271 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
272 * all PIO functions call through a hook.
275 #ifdef CONFIG_PPC_INDIRECT_MMIO
276 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
277 #define PCI_IO_IND_TOKEN_SHIFT 48
278 #define PCI_FIX_ADDR(addr) \
279 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
280 #define PCI_GET_ADDR_TOKEN(addr) \
281 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
282 PCI_IO_IND_TOKEN_SHIFT)
283 #define PCI_SET_ADDR_TOKEN(addr, token) \
285 unsigned long __a = (unsigned long)(addr); \
286 __a &= ~PCI_IO_IND_TOKEN_MASK; \
287 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
288 (addr) = (void __iomem *)__a; \
291 #define PCI_FIX_ADDR(addr) (addr)
296 * Non ordered and non-swapping "raw" accessors
299 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
301 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
303 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
305 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
307 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
309 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
311 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
313 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
315 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
317 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
319 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
321 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
325 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
327 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
329 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
331 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
333 #endif /* __powerpc64__ */
337 * PCI PIO and MMIO accessors.
340 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
341 * machine checks (which they occasionally do when probing non existing
342 * IO ports on some platforms, like PowerMac and 8xx).
343 * I always found it to be of dubious reliability and I am tempted to get
344 * rid of it one of these days. So if you think it's important to keep it,
345 * please voice up asap. We never had it for 64 bits and I do not intend
351 #define __do_in_asm(name, op) \
352 static inline unsigned int name(unsigned int port) \
355 __asm__ __volatile__( \
357 "0:" op " %0,0,%1\n" \
362 ".section .fixup,\"ax\"\n" \
366 ".section __ex_table,\"a\"\n" \
374 : "r" (port + _IO_BASE) \
379 #define __do_out_asm(name, op) \
380 static inline void name(unsigned int val, unsigned int port) \
382 __asm__ __volatile__( \
384 "0:" op " %0,0,%1\n" \
387 ".section __ex_table,\"a\"\n" \
392 : : "r" (val), "r" (port + _IO_BASE) \
396 __do_in_asm(_rec_inb, "lbzx")
397 __do_in_asm(_rec_inw, "lhbrx")
398 __do_in_asm(_rec_inl, "lwbrx")
399 __do_out_asm(_rec_outb, "stbx")
400 __do_out_asm(_rec_outw, "sthbrx")
401 __do_out_asm(_rec_outl, "stwbrx")
403 #endif /* CONFIG_PPC32 */
405 /* The "__do_*" operations below provide the actual "base" implementation
406 * for each of the defined accessors. Some of them use the out_* functions
407 * directly, some of them still use EEH, though we might change that in the
408 * future. Those macros below provide the necessary argument swapping and
409 * handling of the IO base for PIO.
411 * They are themselves used by the macros that define the actual accessors
412 * and can be used by the hooks if any.
414 * Note that PIO operations are always defined in terms of their corresonding
415 * MMIO operations. That allows platforms like iSeries who want to modify the
416 * behaviour of both to only hook on the MMIO version and get both. It's also
417 * possible to hook directly at the toplevel PIO operation if they have to
418 * be handled differently
420 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
421 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
422 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
423 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
424 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
425 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
426 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
429 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
430 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
431 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
432 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
433 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
434 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
435 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
436 #else /* CONFIG_EEH */
437 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
438 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
439 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
440 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
441 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
442 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
443 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
444 #endif /* !defined(CONFIG_EEH) */
447 #define __do_outb(val, port) _rec_outb(val, port)
448 #define __do_outw(val, port) _rec_outw(val, port)
449 #define __do_outl(val, port) _rec_outl(val, port)
450 #define __do_inb(port) _rec_inb(port)
451 #define __do_inw(port) _rec_inw(port)
452 #define __do_inl(port) _rec_inl(port)
453 #else /* CONFIG_PPC32 */
454 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
455 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
456 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
457 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
458 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
459 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
460 #endif /* !CONFIG_PPC32 */
463 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
464 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
465 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
466 #else /* CONFIG_EEH */
467 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
468 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
469 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
470 #endif /* !CONFIG_EEH */
471 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
472 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
473 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
475 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
476 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
477 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
478 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
479 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
480 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
482 #define __do_memset_io(addr, c, n) \
483 _memset_io(PCI_FIX_ADDR(addr), c, n)
484 #define __do_memcpy_toio(dst, src, n) \
485 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
488 #define __do_memcpy_fromio(dst, src, n) \
489 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
490 #else /* CONFIG_EEH */
491 #define __do_memcpy_fromio(dst, src, n) \
492 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
493 #endif /* !CONFIG_EEH */
495 #ifdef CONFIG_PPC_INDIRECT_PIO
496 #define DEF_PCI_HOOK_pio(x) x
498 #define DEF_PCI_HOOK_pio(x) NULL
501 #ifdef CONFIG_PPC_INDIRECT_MMIO
502 #define DEF_PCI_HOOK_mem(x) x
504 #define DEF_PCI_HOOK_mem(x) NULL
507 /* Structure containing all the hooks */
508 extern struct ppc_pci_io {
510 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
511 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
513 #include <asm/io-defs.h>
515 #undef DEF_PCI_AC_RET
516 #undef DEF_PCI_AC_NORET
520 /* The inline wrappers */
521 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
522 static inline ret name at \
524 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
525 return ppc_pci_io.name al; \
526 return __do_##name al; \
529 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
530 static inline void name at \
532 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
533 ppc_pci_io.name al; \
538 #include <asm/io-defs.h>
540 #undef DEF_PCI_AC_RET
541 #undef DEF_PCI_AC_NORET
543 /* Some drivers check for the presence of readq & writeq with
544 * a #ifdef, so we make them happy here.
548 #define writeq writeq
552 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
555 #define xlate_dev_mem_ptr(p) __va(p)
558 * Convert a virtual cached pointer to an uncached pointer
560 #define xlate_dev_kmem_ptr(p) p
563 * We don't do relaxed operations yet, at least not with this semantic
565 #define readb_relaxed(addr) readb(addr)
566 #define readw_relaxed(addr) readw(addr)
567 #define readl_relaxed(addr) readl(addr)
568 #define readq_relaxed(addr) readq(addr)
574 * Enforce synchronisation of stores vs. spin_unlock
575 * (this does it explicitly, though our implementation of spin_unlock
576 * does it implicitely too)
578 static inline void mmiowb(void)
582 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
583 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
586 #endif /* !CONFIG_PPC32 */
588 static inline void iosync(void)
590 __asm__ __volatile__ ("sync" : : : "memory");
593 /* Enforce in-order execution of data I/O.
594 * No distinction between read/write on PPC; use eieio for all three.
595 * Those are fairly week though. They don't provide a barrier between
596 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
597 * they only provide barriers between 2 __raw MMIO operations and
598 * possibly break write combining.
600 #define iobarrier_rw() eieio()
601 #define iobarrier_r() eieio()
602 #define iobarrier_w() eieio()
606 * output pause versions need a delay at least for the
607 * w83c105 ide controller in a p610.
609 #define inb_p(port) inb(port)
610 #define outb_p(val, port) (udelay(1), outb((val), (port)))
611 #define inw_p(port) inw(port)
612 #define outw_p(val, port) (udelay(1), outw((val), (port)))
613 #define inl_p(port) inl(port)
614 #define outl_p(val, port) (udelay(1), outl((val), (port)))
617 #define IO_SPACE_LIMIT ~(0UL)
621 * ioremap - map bus memory into CPU space
622 * @address: bus address of the memory
623 * @size: size of the resource to map
625 * ioremap performs a platform specific sequence of operations to
626 * make bus memory CPU accessible via the readb/readw/readl/writeb/
627 * writew/writel functions and the other mmio helpers. The returned
628 * address is not guaranteed to be usable directly as a virtual
631 * We provide a few variations of it:
633 * * ioremap is the standard one and provides non-cacheable guarded mappings
634 * and can be hooked by the platform via ppc_md
636 * * ioremap_prot allows to specify the page flags as an argument and can
637 * also be hooked by the platform via ppc_md.
639 * * ioremap_nocache is identical to ioremap
641 * * ioremap_wc enables write combining
643 * * iounmap undoes such a mapping and can be hooked
645 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
646 * create hand-made mappings for use only by the PCI code and cannot
647 * currently be hooked. Must be page aligned.
649 * * __ioremap is the low level implementation used by ioremap and
650 * ioremap_prot and cannot be hooked (but can be used by a hook on one
651 * of the previous ones)
653 * * __ioremap_caller is the same as above but takes an explicit caller
654 * reference rather than using __builtin_return_address(0)
656 * * __iounmap, is the low level implementation used by iounmap and cannot
657 * be hooked (but can be used by a hook on iounmap)
660 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
661 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
662 unsigned long flags);
663 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
664 #define ioremap_nocache(addr, size) ioremap((addr), (size))
666 extern void iounmap(volatile void __iomem *addr);
668 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
669 unsigned long flags);
670 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
671 unsigned long flags, void *caller);
673 extern void __iounmap(volatile void __iomem *addr);
675 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
676 unsigned long size, unsigned long flags);
677 extern void __iounmap_at(void *ea, unsigned long size);
680 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
681 * which needs some additional definitions here. They basically allow PIO
682 * space overall to be 1GB. This will work as long as we never try to use
683 * iomap to map MMIO below 1GB which should be fine on ppc64
685 #define HAVE_ARCH_PIO_SIZE 1
686 #define PIO_OFFSET 0x00000000UL
687 #define PIO_MASK (FULL_IO_SIZE - 1)
688 #define PIO_RESERVED (FULL_IO_SIZE)
690 #define mmio_read16be(addr) readw_be(addr)
691 #define mmio_read32be(addr) readl_be(addr)
692 #define mmio_write16be(val, addr) writew_be(val, addr)
693 #define mmio_write32be(val, addr) writel_be(val, addr)
694 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
695 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
696 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
697 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
698 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
699 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
702 * virt_to_phys - map virtual addresses to physical
703 * @address: address to remap
705 * The returned physical address is the physical (CPU) mapping for
706 * the memory address given. It is only valid to use this function on
707 * addresses directly mapped or allocated via kmalloc.
709 * This function does not give bus mappings for DMA transfers. In
710 * almost all conceivable cases a device driver should not be using
713 static inline unsigned long virt_to_phys(volatile void * address)
715 return __pa((unsigned long)address);
719 * phys_to_virt - map physical address to virtual
720 * @address: address to remap
722 * The returned virtual address is a current CPU mapping for
723 * the memory address given. It is only valid to use this function on
724 * addresses that have a kernel mapping
726 * This function does not handle bus mappings for DMA transfers. In
727 * almost all conceivable cases a device driver should not be using
730 static inline void * phys_to_virt(unsigned long address)
732 return (void *)__va(address);
736 * Change "struct page" to physical address.
738 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
741 * 32 bits still uses virt_to_bus() for it's implementation of DMA
742 * mappings se we have to keep it defined here. We also have some old
743 * drivers (shame shame shame) that use bus_to_virt() and haven't been
744 * fixed yet so I need to define it here.
748 static inline unsigned long virt_to_bus(volatile void * address)
752 return __pa(address) + PCI_DRAM_OFFSET;
755 static inline void * bus_to_virt(unsigned long address)
759 return __va(address - PCI_DRAM_OFFSET);
762 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
764 #endif /* CONFIG_PPC32 */
767 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
768 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
770 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
771 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
773 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
774 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
776 /* Clear and set bits in one shot. These macros can be used to clear and
777 * set multiple bits in a register using a single read-modify-write. These
778 * macros can also be used to set a multiple-bit bit pattern using a mask,
779 * by specifying the mask in the 'clear' parameter and the new bit pattern
780 * in the 'set' parameter.
783 #define clrsetbits(type, addr, clear, set) \
784 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
787 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
788 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
791 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
792 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
794 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
795 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
797 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
799 void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
800 size_t size, unsigned long flags);
802 #endif /* __KERNEL__ */
804 #endif /* _ASM_POWERPC_IO_H */