2 * Copyright 2010 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
61 QSGMII_FM1_A, /* A indicates MACs 1-4 */
62 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
70 SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */
76 QSGMII_SW1_A, /* SW indicates on L2 swtich */
87 int is_serdes_configured(enum srds_prtcl device);
88 void fsl_serdes_init(void);
89 const char *serdes_clock_to_string(u32 clock);
91 #ifdef CONFIG_FSL_CORENET
92 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
93 int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
94 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
96 int serdes_get_first_lane(enum srds_prtcl device);
98 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
99 void serdes_reset_rx(enum srds_prtcl device);
103 #endif /* __FSL_SERDES_H */